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/arch/powerpc/include/asm/fsl_lbc.h

http://github.com/mirrors/linux
C Header | 296 lines | 248 code | 18 blank | 30 comment | 1 complexity | eab59321bba883a5f8923f4e33f624e2 MD5 | raw file
  1/* SPDX-License-Identifier: GPL-2.0-or-later */
  2/* Freescale Local Bus Controller
  3 *
  4 * Copyright © 2006-2007, 2010 Freescale Semiconductor
  5 *
  6 * Authors: Nick Spence <nick.spence@freescale.com>,
  7 *          Scott Wood <scottwood@freescale.com>
  8 *          Jack Lan <jack.lan@freescale.com>
  9 */
 10
 11#ifndef __ASM_FSL_LBC_H
 12#define __ASM_FSL_LBC_H
 13
 14#include <linux/compiler.h>
 15#include <linux/types.h>
 16#include <linux/io.h>
 17#include <linux/device.h>
 18#include <linux/spinlock.h>
 19
 20struct fsl_lbc_bank {
 21	__be32 br;             /**< Base Register  */
 22#define BR_BA           0xFFFF8000
 23#define BR_BA_SHIFT             15
 24#define BR_PS           0x00001800
 25#define BR_PS_SHIFT             11
 26#define BR_PS_8         0x00000800  /* Port Size 8 bit */
 27#define BR_PS_16        0x00001000  /* Port Size 16 bit */
 28#define BR_PS_32        0x00001800  /* Port Size 32 bit */
 29#define BR_DECC         0x00000600
 30#define BR_DECC_SHIFT            9
 31#define BR_DECC_OFF     0x00000000  /* HW ECC checking and generation off */
 32#define BR_DECC_CHK     0x00000200  /* HW ECC checking on, generation off */
 33#define BR_DECC_CHK_GEN 0x00000400  /* HW ECC checking and generation on */
 34#define BR_WP           0x00000100
 35#define BR_WP_SHIFT              8
 36#define BR_MSEL         0x000000E0
 37#define BR_MSEL_SHIFT            5
 38#define BR_MS_GPCM      0x00000000  /* GPCM */
 39#define BR_MS_FCM       0x00000020  /* FCM */
 40#define BR_MS_SDRAM     0x00000060  /* SDRAM */
 41#define BR_MS_UPMA      0x00000080  /* UPMA */
 42#define BR_MS_UPMB      0x000000A0  /* UPMB */
 43#define BR_MS_UPMC      0x000000C0  /* UPMC */
 44#define BR_V            0x00000001
 45#define BR_V_SHIFT               0
 46#define BR_RES          ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V)
 47
 48	__be32 or;             /**< Base Register  */
 49#define OR0 0x5004
 50#define OR1 0x500C
 51#define OR2 0x5014
 52#define OR3 0x501C
 53#define OR4 0x5024
 54#define OR5 0x502C
 55#define OR6 0x5034
 56#define OR7 0x503C
 57
 58#define OR_FCM_AM               0xFFFF8000
 59#define OR_FCM_AM_SHIFT                 15
 60#define OR_FCM_BCTLD            0x00001000
 61#define OR_FCM_BCTLD_SHIFT              12
 62#define OR_FCM_PGS              0x00000400
 63#define OR_FCM_PGS_SHIFT                10
 64#define OR_FCM_CSCT             0x00000200
 65#define OR_FCM_CSCT_SHIFT                9
 66#define OR_FCM_CST              0x00000100
 67#define OR_FCM_CST_SHIFT                 8
 68#define OR_FCM_CHT              0x00000080
 69#define OR_FCM_CHT_SHIFT                 7
 70#define OR_FCM_SCY              0x00000070
 71#define OR_FCM_SCY_SHIFT                 4
 72#define OR_FCM_SCY_1            0x00000010
 73#define OR_FCM_SCY_2            0x00000020
 74#define OR_FCM_SCY_3            0x00000030
 75#define OR_FCM_SCY_4            0x00000040
 76#define OR_FCM_SCY_5            0x00000050
 77#define OR_FCM_SCY_6            0x00000060
 78#define OR_FCM_SCY_7            0x00000070
 79#define OR_FCM_RST              0x00000008
 80#define OR_FCM_RST_SHIFT                 3
 81#define OR_FCM_TRLX             0x00000004
 82#define OR_FCM_TRLX_SHIFT                2
 83#define OR_FCM_EHTR             0x00000002
 84#define OR_FCM_EHTR_SHIFT                1
 85
 86#define OR_GPCM_AM		0xFFFF8000
 87#define OR_GPCM_AM_SHIFT		15
 88};
 89
 90struct fsl_lbc_regs {
 91	struct fsl_lbc_bank bank[12];
 92	u8 res0[0x8];
 93	__be32 mar;             /**< UPM Address Register */
 94	u8 res1[0x4];
 95	__be32 mamr;            /**< UPMA Mode Register */
 96#define MxMR_OP_NO	(0 << 28) /**< normal operation */
 97#define MxMR_OP_WA	(1 << 28) /**< write array */
 98#define MxMR_OP_RA	(2 << 28) /**< read array */
 99#define MxMR_OP_RP	(3 << 28) /**< run pattern */
100#define MxMR_MAD	0x3f      /**< machine address */
101	__be32 mbmr;            /**< UPMB Mode Register */
102	__be32 mcmr;            /**< UPMC Mode Register */
103	u8 res2[0x8];
104	__be32 mrtpr;           /**< Memory Refresh Timer Prescaler Register */
105	__be32 mdr;             /**< UPM Data Register */
106	u8 res3[0x4];
107	__be32 lsor;            /**< Special Operation Initiation Register */
108	__be32 lsdmr;           /**< SDRAM Mode Register */
109	u8 res4[0x8];
110	__be32 lurt;            /**< UPM Refresh Timer */
111	__be32 lsrt;            /**< SDRAM Refresh Timer */
112	u8 res5[0x8];
113	__be32 ltesr;           /**< Transfer Error Status Register */
114#define LTESR_BM   0x80000000
115#define LTESR_FCT  0x40000000
116#define LTESR_PAR  0x20000000
117#define LTESR_WP   0x04000000
118#define LTESR_ATMW 0x00800000
119#define LTESR_ATMR 0x00400000
120#define LTESR_CS   0x00080000
121#define LTESR_UPM  0x00000002
122#define LTESR_CC   0x00000001
123#define LTESR_NAND_MASK (LTESR_FCT | LTESR_PAR | LTESR_CC)
124#define LTESR_MASK      (LTESR_BM | LTESR_FCT | LTESR_PAR | LTESR_WP \
125			 | LTESR_ATMW | LTESR_ATMR | LTESR_CS | LTESR_UPM \
126			 | LTESR_CC)
127#define LTESR_CLEAR	0xFFFFFFFF
128#define LTECCR_CLEAR	0xFFFFFFFF
129#define LTESR_STATUS	LTESR_MASK
130#define LTEIR_ENABLE	LTESR_MASK
131#define LTEDR_ENABLE	0x00000000
132	__be32 ltedr;           /**< Transfer Error Disable Register */
133	__be32 lteir;           /**< Transfer Error Interrupt Register */
134	__be32 lteatr;          /**< Transfer Error Attributes Register */
135	__be32 ltear;           /**< Transfer Error Address Register */
136	__be32 lteccr;          /**< Transfer Error ECC Register */
137	u8 res6[0x8];
138	__be32 lbcr;            /**< Configuration Register */
139#define LBCR_LDIS  0x80000000
140#define LBCR_LDIS_SHIFT    31
141#define LBCR_BCTLC 0x00C00000
142#define LBCR_BCTLC_SHIFT   22
143#define LBCR_AHD   0x00200000
144#define LBCR_LPBSE 0x00020000
145#define LBCR_LPBSE_SHIFT   17
146#define LBCR_EPAR  0x00010000
147#define LBCR_EPAR_SHIFT    16
148#define LBCR_BMT   0x0000FF00
149#define LBCR_BMT_SHIFT      8
150#define LBCR_BMTPS 0x0000000F
151#define LBCR_BMTPS_SHIFT    0
152#define LBCR_INIT  0x00040000
153	__be32 lcrr;            /**< Clock Ratio Register */
154#define LCRR_DBYP    0x80000000
155#define LCRR_DBYP_SHIFT      31
156#define LCRR_BUFCMDC 0x30000000
157#define LCRR_BUFCMDC_SHIFT   28
158#define LCRR_ECL     0x03000000
159#define LCRR_ECL_SHIFT       24
160#define LCRR_EADC    0x00030000
161#define LCRR_EADC_SHIFT      16
162#define LCRR_CLKDIV  0x0000000F
163#define LCRR_CLKDIV_SHIFT     0
164	u8 res7[0x8];
165	__be32 fmr;             /**< Flash Mode Register */
166#define FMR_CWTO     0x0000F000
167#define FMR_CWTO_SHIFT       12
168#define FMR_BOOT     0x00000800
169#define FMR_ECCM     0x00000100
170#define FMR_AL       0x00000030
171#define FMR_AL_SHIFT          4
172#define FMR_OP       0x00000003
173#define FMR_OP_SHIFT          0
174	__be32 fir;             /**< Flash Instruction Register */
175#define FIR_OP0      0xF0000000
176#define FIR_OP0_SHIFT        28
177#define FIR_OP1      0x0F000000
178#define FIR_OP1_SHIFT        24
179#define FIR_OP2      0x00F00000
180#define FIR_OP2_SHIFT        20
181#define FIR_OP3      0x000F0000
182#define FIR_OP3_SHIFT        16
183#define FIR_OP4      0x0000F000
184#define FIR_OP4_SHIFT        12
185#define FIR_OP5      0x00000F00
186#define FIR_OP5_SHIFT         8
187#define FIR_OP6      0x000000F0
188#define FIR_OP6_SHIFT         4
189#define FIR_OP7      0x0000000F
190#define FIR_OP7_SHIFT         0
191#define FIR_OP_NOP   0x0	/* No operation and end of sequence */
192#define FIR_OP_CA    0x1        /* Issue current column address */
193#define FIR_OP_PA    0x2        /* Issue current block+page address */
194#define FIR_OP_UA    0x3        /* Issue user defined address */
195#define FIR_OP_CM0   0x4        /* Issue command from FCR[CMD0] */
196#define FIR_OP_CM1   0x5        /* Issue command from FCR[CMD1] */
197#define FIR_OP_CM2   0x6        /* Issue command from FCR[CMD2] */
198#define FIR_OP_CM3   0x7        /* Issue command from FCR[CMD3] */
199#define FIR_OP_WB    0x8        /* Write FBCR bytes from FCM buffer */
200#define FIR_OP_WS    0x9        /* Write 1 or 2 bytes from MDR[AS] */
201#define FIR_OP_RB    0xA        /* Read FBCR bytes to FCM buffer */
202#define FIR_OP_RS    0xB        /* Read 1 or 2 bytes to MDR[AS] */
203#define FIR_OP_CW0   0xC        /* Wait then issue FCR[CMD0] */
204#define FIR_OP_CW1   0xD        /* Wait then issue FCR[CMD1] */
205#define FIR_OP_RBW   0xE        /* Wait then read FBCR bytes */
206#define FIR_OP_RSW   0xE        /* Wait then read 1 or 2 bytes */
207	__be32 fcr;             /**< Flash Command Register */
208#define FCR_CMD0     0xFF000000
209#define FCR_CMD0_SHIFT       24
210#define FCR_CMD1     0x00FF0000
211#define FCR_CMD1_SHIFT       16
212#define FCR_CMD2     0x0000FF00
213#define FCR_CMD2_SHIFT        8
214#define FCR_CMD3     0x000000FF
215#define FCR_CMD3_SHIFT        0
216	__be32 fbar;            /**< Flash Block Address Register */
217#define FBAR_BLK     0x00FFFFFF
218	__be32 fpar;            /**< Flash Page Address Register */
219#define FPAR_SP_PI   0x00007C00
220#define FPAR_SP_PI_SHIFT     10
221#define FPAR_SP_MS   0x00000200
222#define FPAR_SP_CI   0x000001FF
223#define FPAR_SP_CI_SHIFT      0
224#define FPAR_LP_PI   0x0003F000
225#define FPAR_LP_PI_SHIFT     12
226#define FPAR_LP_MS   0x00000800
227#define FPAR_LP_CI   0x000007FF
228#define FPAR_LP_CI_SHIFT      0
229	__be32 fbcr;            /**< Flash Byte Count Register */
230#define FBCR_BC      0x00000FFF
231};
232
233/*
234 * FSL UPM routines
235 */
236struct fsl_upm {
237	__be32 __iomem *mxmr;
238	int width;
239};
240
241extern u32 fsl_lbc_addr(phys_addr_t addr_base);
242extern int fsl_lbc_find(phys_addr_t addr_base);
243extern int fsl_upm_find(phys_addr_t addr_base, struct fsl_upm *upm);
244
245/**
246 * fsl_upm_start_pattern - start UPM patterns execution
247 * @upm:	pointer to the fsl_upm structure obtained via fsl_upm_find
248 * @pat_offset:	UPM pattern offset for the command to be executed
249 *
250 * This routine programmes UPM so the next memory access that hits an UPM
251 * will trigger pattern execution, starting at pat_offset.
252 */
253static inline void fsl_upm_start_pattern(struct fsl_upm *upm, u8 pat_offset)
254{
255	clrsetbits_be32(upm->mxmr, MxMR_MAD, MxMR_OP_RP | pat_offset);
256}
257
258/**
259 * fsl_upm_end_pattern - end UPM patterns execution
260 * @upm:	pointer to the fsl_upm structure obtained via fsl_upm_find
261 *
262 * This routine reverts UPM to normal operation mode.
263 */
264static inline void fsl_upm_end_pattern(struct fsl_upm *upm)
265{
266	clrbits32(upm->mxmr, MxMR_OP_RP);
267
268	while (in_be32(upm->mxmr) & MxMR_OP_RP)
269		cpu_relax();
270}
271
272/* overview of the fsl lbc controller */
273
274struct fsl_lbc_ctrl {
275	/* device info */
276	struct device			*dev;
277	struct fsl_lbc_regs __iomem	*regs;
278	int				irq[2];
279	wait_queue_head_t		irq_wait;
280	spinlock_t			lock;
281	void				*nand;
282
283	/* status read from LTESR by irq handler */
284	unsigned int			irq_status;
285
286#ifdef CONFIG_SUSPEND
287	/* save regs when system go to deep-sleep */
288	struct fsl_lbc_regs		*saved_regs;
289#endif
290};
291
292extern int fsl_upm_run_pattern(struct fsl_upm *upm, void __iomem *io_base,
293			       u32 mar);
294extern struct fsl_lbc_ctrl *fsl_lbc_ctrl_dev;
295
296#endif /* __ASM_FSL_LBC_H */