/arch/powerpc/include/asm/pci-bridge.h

http://github.com/mirrors/linux · C Header · 299 lines · 199 code · 50 blank · 50 comment · 1 complexity · b38aca5c77792399b3c806f0bff805ce MD5 · raw file

  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. #ifndef _ASM_POWERPC_PCI_BRIDGE_H
  3. #define _ASM_POWERPC_PCI_BRIDGE_H
  4. #ifdef __KERNEL__
  5. /*
  6. */
  7. #include <linux/pci.h>
  8. #include <linux/list.h>
  9. #include <linux/ioport.h>
  10. #include <linux/numa.h>
  11. struct device_node;
  12. /*
  13. * PCI controller operations
  14. */
  15. struct pci_controller_ops {
  16. void (*dma_dev_setup)(struct pci_dev *pdev);
  17. void (*dma_bus_setup)(struct pci_bus *bus);
  18. bool (*iommu_bypass_supported)(struct pci_dev *pdev,
  19. u64 mask);
  20. int (*probe_mode)(struct pci_bus *bus);
  21. /* Called when pci_enable_device() is called. Returns true to
  22. * allow assignment/enabling of the device. */
  23. bool (*enable_device_hook)(struct pci_dev *pdev);
  24. void (*disable_device)(struct pci_dev *pdev);
  25. void (*release_device)(struct pci_dev *pdev);
  26. /* Called during PCI resource reassignment */
  27. resource_size_t (*window_alignment)(struct pci_bus *bus,
  28. unsigned long type);
  29. void (*setup_bridge)(struct pci_bus *bus,
  30. unsigned long type);
  31. void (*reset_secondary_bus)(struct pci_dev *pdev);
  32. #ifdef CONFIG_PCI_MSI
  33. int (*setup_msi_irqs)(struct pci_dev *pdev,
  34. int nvec, int type);
  35. void (*teardown_msi_irqs)(struct pci_dev *pdev);
  36. #endif
  37. void (*shutdown)(struct pci_controller *hose);
  38. };
  39. /*
  40. * Structure of a PCI controller (host bridge)
  41. */
  42. struct pci_controller {
  43. struct pci_bus *bus;
  44. char is_dynamic;
  45. #ifdef CONFIG_PPC64
  46. int node;
  47. #endif
  48. struct device_node *dn;
  49. struct list_head list_node;
  50. struct device *parent;
  51. int first_busno;
  52. int last_busno;
  53. int self_busno;
  54. struct resource busn;
  55. void __iomem *io_base_virt;
  56. #ifdef CONFIG_PPC64
  57. void *io_base_alloc;
  58. #endif
  59. resource_size_t io_base_phys;
  60. resource_size_t pci_io_size;
  61. /* Some machines have a special region to forward the ISA
  62. * "memory" cycles such as VGA memory regions. Left to 0
  63. * if unsupported
  64. */
  65. resource_size_t isa_mem_phys;
  66. resource_size_t isa_mem_size;
  67. struct pci_controller_ops controller_ops;
  68. struct pci_ops *ops;
  69. unsigned int __iomem *cfg_addr;
  70. void __iomem *cfg_data;
  71. /*
  72. * Used for variants of PCI indirect handling and possible quirks:
  73. * SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
  74. * EXT_REG - provides access to PCI-e extended registers
  75. * SURPRESS_PRIMARY_BUS - we suppress the setting of PCI_PRIMARY_BUS
  76. * on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
  77. * to determine which bus number to match on when generating type0
  78. * config cycles
  79. * NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
  80. * hanging if we don't have link and try to do config cycles to
  81. * anything but the PHB. Only allow talking to the PHB if this is
  82. * set.
  83. * BIG_ENDIAN - cfg_addr is a big endian register
  84. * BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on
  85. * the PLB4. Effectively disable MRM commands by setting this.
  86. * FSL_CFG_REG_LINK - Freescale controller version in which the PCIe
  87. * link status is in a RC PCIe cfg register (vs being a SoC register)
  88. */
  89. #define PPC_INDIRECT_TYPE_SET_CFG_TYPE 0x00000001
  90. #define PPC_INDIRECT_TYPE_EXT_REG 0x00000002
  91. #define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS 0x00000004
  92. #define PPC_INDIRECT_TYPE_NO_PCIE_LINK 0x00000008
  93. #define PPC_INDIRECT_TYPE_BIG_ENDIAN 0x00000010
  94. #define PPC_INDIRECT_TYPE_BROKEN_MRM 0x00000020
  95. #define PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK 0x00000040
  96. u32 indirect_type;
  97. /* Currently, we limit ourselves to 1 IO range and 3 mem
  98. * ranges since the common pci_bus structure can't handle more
  99. */
  100. struct resource io_resource;
  101. struct resource mem_resources[3];
  102. resource_size_t mem_offset[3];
  103. int global_number; /* PCI domain number */
  104. resource_size_t dma_window_base_cur;
  105. resource_size_t dma_window_size;
  106. #ifdef CONFIG_PPC64
  107. unsigned long buid;
  108. struct pci_dn *pci_data;
  109. #endif /* CONFIG_PPC64 */
  110. void *private_data;
  111. struct npu *npu;
  112. };
  113. /* These are used for config access before all the PCI probing
  114. has been done. */
  115. extern int early_read_config_byte(struct pci_controller *hose, int bus,
  116. int dev_fn, int where, u8 *val);
  117. extern int early_read_config_word(struct pci_controller *hose, int bus,
  118. int dev_fn, int where, u16 *val);
  119. extern int early_read_config_dword(struct pci_controller *hose, int bus,
  120. int dev_fn, int where, u32 *val);
  121. extern int early_write_config_byte(struct pci_controller *hose, int bus,
  122. int dev_fn, int where, u8 val);
  123. extern int early_write_config_word(struct pci_controller *hose, int bus,
  124. int dev_fn, int where, u16 val);
  125. extern int early_write_config_dword(struct pci_controller *hose, int bus,
  126. int dev_fn, int where, u32 val);
  127. extern int early_find_capability(struct pci_controller *hose, int bus,
  128. int dev_fn, int cap);
  129. extern void setup_indirect_pci(struct pci_controller* hose,
  130. resource_size_t cfg_addr,
  131. resource_size_t cfg_data, u32 flags);
  132. extern int indirect_read_config(struct pci_bus *bus, unsigned int devfn,
  133. int offset, int len, u32 *val);
  134. extern int __indirect_read_config(struct pci_controller *hose,
  135. unsigned char bus_number, unsigned int devfn,
  136. int offset, int len, u32 *val);
  137. extern int indirect_write_config(struct pci_bus *bus, unsigned int devfn,
  138. int offset, int len, u32 val);
  139. static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
  140. {
  141. return bus->sysdata;
  142. }
  143. #ifndef CONFIG_PPC64
  144. extern int pci_device_from_OF_node(struct device_node *node,
  145. u8 *bus, u8 *devfn);
  146. extern void pci_create_OF_bus_map(void);
  147. #else /* CONFIG_PPC64 */
  148. /*
  149. * PCI stuff, for nodes representing PCI devices, pointed to
  150. * by device_node->data.
  151. */
  152. struct iommu_table;
  153. struct pci_dn {
  154. int flags;
  155. #define PCI_DN_FLAG_IOV_VF 0x01
  156. #define PCI_DN_FLAG_DEAD 0x02 /* Device has been hot-removed */
  157. int busno; /* pci bus number */
  158. int devfn; /* pci device and function number */
  159. int vendor_id; /* Vendor ID */
  160. int device_id; /* Device ID */
  161. int class_code; /* Device class code */
  162. struct pci_dn *parent;
  163. struct pci_controller *phb; /* for pci devices */
  164. struct iommu_table_group *table_group; /* for phb's or bridges */
  165. int pci_ext_config_space; /* for pci devices */
  166. #ifdef CONFIG_EEH
  167. struct eeh_dev *edev; /* eeh device */
  168. #endif
  169. #define IODA_INVALID_PE 0xFFFFFFFF
  170. unsigned int pe_number;
  171. #ifdef CONFIG_PCI_IOV
  172. int vf_index; /* VF index in the PF */
  173. u16 vfs_expanded; /* number of VFs IOV BAR expanded */
  174. u16 num_vfs; /* number of VFs enabled*/
  175. unsigned int *pe_num_map; /* PE# for the first VF PE or array */
  176. bool m64_single_mode; /* Use M64 BAR in Single Mode */
  177. #define IODA_INVALID_M64 (-1)
  178. int (*m64_map)[PCI_SRIOV_NUM_BARS]; /* Only used on powernv */
  179. int last_allow_rc; /* Only used on pseries */
  180. #endif /* CONFIG_PCI_IOV */
  181. int mps; /* Maximum Payload Size */
  182. struct list_head child_list;
  183. struct list_head list;
  184. struct resource holes[PCI_SRIOV_NUM_BARS];
  185. };
  186. /* Get the pointer to a device_node's pci_dn */
  187. #define PCI_DN(dn) ((struct pci_dn *) (dn)->data)
  188. extern struct pci_dn *pci_get_pdn_by_devfn(struct pci_bus *bus,
  189. int devfn);
  190. extern struct pci_dn *pci_get_pdn(struct pci_dev *pdev);
  191. extern struct pci_dn *pci_add_device_node_info(struct pci_controller *hose,
  192. struct device_node *dn);
  193. extern void pci_remove_device_node_info(struct device_node *dn);
  194. #ifdef CONFIG_PCI_IOV
  195. struct pci_dn *add_sriov_vf_pdns(struct pci_dev *pdev);
  196. void remove_sriov_vf_pdns(struct pci_dev *pdev);
  197. #endif
  198. static inline int pci_device_from_OF_node(struct device_node *np,
  199. u8 *bus, u8 *devfn)
  200. {
  201. if (!PCI_DN(np))
  202. return -ENODEV;
  203. *bus = PCI_DN(np)->busno;
  204. *devfn = PCI_DN(np)->devfn;
  205. return 0;
  206. }
  207. #if defined(CONFIG_EEH)
  208. static inline struct eeh_dev *pdn_to_eeh_dev(struct pci_dn *pdn)
  209. {
  210. return pdn ? pdn->edev : NULL;
  211. }
  212. #else
  213. #define pdn_to_eeh_dev(x) (NULL)
  214. #endif
  215. /** Find the bus corresponding to the indicated device node */
  216. extern struct pci_bus *pci_find_bus_by_node(struct device_node *dn);
  217. /** Remove all of the PCI devices under this bus */
  218. extern void pci_hp_remove_devices(struct pci_bus *bus);
  219. /** Discover new pci devices under this bus, and add them */
  220. extern void pci_hp_add_devices(struct pci_bus *bus);
  221. extern int pcibios_unmap_io_space(struct pci_bus *bus);
  222. extern int pcibios_map_io_space(struct pci_bus *bus);
  223. #ifdef CONFIG_NUMA
  224. #define PHB_SET_NODE(PHB, NODE) ((PHB)->node = (NODE))
  225. #else
  226. #define PHB_SET_NODE(PHB, NODE) ((PHB)->node = NUMA_NO_NODE)
  227. #endif
  228. #endif /* CONFIG_PPC64 */
  229. /* Get the PCI host controller for an OF device */
  230. extern struct pci_controller *pci_find_hose_for_OF_device(
  231. struct device_node* node);
  232. extern struct pci_controller *pci_find_controller_for_domain(int domain_nr);
  233. /* Fill up host controller resources from the OF node */
  234. extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
  235. struct device_node *dev, int primary);
  236. /* Allocate & free a PCI host bridge structure */
  237. extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev);
  238. extern void pcibios_free_controller(struct pci_controller *phb);
  239. extern void pcibios_free_controller_deferred(struct pci_host_bridge *bridge);
  240. #ifdef CONFIG_PCI
  241. extern int pcibios_vaddr_is_ioport(void __iomem *address);
  242. #else
  243. static inline int pcibios_vaddr_is_ioport(void __iomem *address)
  244. {
  245. return 0;
  246. }
  247. #endif /* CONFIG_PCI */
  248. #endif /* __KERNEL__ */
  249. #endif /* _ASM_POWERPC_PCI_BRIDGE_H */