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/arch/powerpc/include/asm/pci-bridge.h

http://github.com/mirrors/linux
C Header | 299 lines | 199 code | 50 blank | 50 comment | 1 complexity | b38aca5c77792399b3c806f0bff805ce MD5 | raw file
  1/* SPDX-License-Identifier: GPL-2.0-or-later */
  2#ifndef _ASM_POWERPC_PCI_BRIDGE_H
  3#define _ASM_POWERPC_PCI_BRIDGE_H
  4#ifdef __KERNEL__
  5/*
  6 */
  7#include <linux/pci.h>
  8#include <linux/list.h>
  9#include <linux/ioport.h>
 10#include <linux/numa.h>
 11
 12struct device_node;
 13
 14/*
 15 * PCI controller operations
 16 */
 17struct pci_controller_ops {
 18	void		(*dma_dev_setup)(struct pci_dev *pdev);
 19	void		(*dma_bus_setup)(struct pci_bus *bus);
 20	bool		(*iommu_bypass_supported)(struct pci_dev *pdev,
 21				u64 mask);
 22
 23	int		(*probe_mode)(struct pci_bus *bus);
 24
 25	/* Called when pci_enable_device() is called. Returns true to
 26	 * allow assignment/enabling of the device. */
 27	bool		(*enable_device_hook)(struct pci_dev *pdev);
 28
 29	void		(*disable_device)(struct pci_dev *pdev);
 30
 31	void		(*release_device)(struct pci_dev *pdev);
 32
 33	/* Called during PCI resource reassignment */
 34	resource_size_t (*window_alignment)(struct pci_bus *bus,
 35					    unsigned long type);
 36	void		(*setup_bridge)(struct pci_bus *bus,
 37					unsigned long type);
 38	void		(*reset_secondary_bus)(struct pci_dev *pdev);
 39
 40#ifdef CONFIG_PCI_MSI
 41	int		(*setup_msi_irqs)(struct pci_dev *pdev,
 42					  int nvec, int type);
 43	void		(*teardown_msi_irqs)(struct pci_dev *pdev);
 44#endif
 45
 46	void		(*shutdown)(struct pci_controller *hose);
 47};
 48
 49/*
 50 * Structure of a PCI controller (host bridge)
 51 */
 52struct pci_controller {
 53	struct pci_bus *bus;
 54	char is_dynamic;
 55#ifdef CONFIG_PPC64
 56	int node;
 57#endif
 58	struct device_node *dn;
 59	struct list_head list_node;
 60	struct device *parent;
 61
 62	int first_busno;
 63	int last_busno;
 64	int self_busno;
 65	struct resource busn;
 66
 67	void __iomem *io_base_virt;
 68#ifdef CONFIG_PPC64
 69	void *io_base_alloc;
 70#endif
 71	resource_size_t io_base_phys;
 72	resource_size_t pci_io_size;
 73
 74	/* Some machines have a special region to forward the ISA
 75	 * "memory" cycles such as VGA memory regions. Left to 0
 76	 * if unsupported
 77	 */
 78	resource_size_t	isa_mem_phys;
 79	resource_size_t	isa_mem_size;
 80
 81	struct pci_controller_ops controller_ops;
 82	struct pci_ops *ops;
 83	unsigned int __iomem *cfg_addr;
 84	void __iomem *cfg_data;
 85
 86	/*
 87	 * Used for variants of PCI indirect handling and possible quirks:
 88	 *  SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
 89	 *  EXT_REG - provides access to PCI-e extended registers
 90	 *  SURPRESS_PRIMARY_BUS - we suppress the setting of PCI_PRIMARY_BUS
 91	 *   on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
 92	 *   to determine which bus number to match on when generating type0
 93	 *   config cycles
 94	 *  NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
 95	 *   hanging if we don't have link and try to do config cycles to
 96	 *   anything but the PHB.  Only allow talking to the PHB if this is
 97	 *   set.
 98	 *  BIG_ENDIAN - cfg_addr is a big endian register
 99	 *  BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on
100	 *   the PLB4.  Effectively disable MRM commands by setting this.
101	 *  FSL_CFG_REG_LINK - Freescale controller version in which the PCIe
102	 *   link status is in a RC PCIe cfg register (vs being a SoC register)
103	 */
104#define PPC_INDIRECT_TYPE_SET_CFG_TYPE		0x00000001
105#define PPC_INDIRECT_TYPE_EXT_REG		0x00000002
106#define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS	0x00000004
107#define PPC_INDIRECT_TYPE_NO_PCIE_LINK		0x00000008
108#define PPC_INDIRECT_TYPE_BIG_ENDIAN		0x00000010
109#define PPC_INDIRECT_TYPE_BROKEN_MRM		0x00000020
110#define PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK	0x00000040
111	u32 indirect_type;
112	/* Currently, we limit ourselves to 1 IO range and 3 mem
113	 * ranges since the common pci_bus structure can't handle more
114	 */
115	struct resource	io_resource;
116	struct resource mem_resources[3];
117	resource_size_t mem_offset[3];
118	int global_number;		/* PCI domain number */
119
120	resource_size_t dma_window_base_cur;
121	resource_size_t dma_window_size;
122
123#ifdef CONFIG_PPC64
124	unsigned long buid;
125	struct pci_dn *pci_data;
126#endif	/* CONFIG_PPC64 */
127
128	void *private_data;
129	struct npu *npu;
130};
131
132/* These are used for config access before all the PCI probing
133   has been done. */
134extern int early_read_config_byte(struct pci_controller *hose, int bus,
135			int dev_fn, int where, u8 *val);
136extern int early_read_config_word(struct pci_controller *hose, int bus,
137			int dev_fn, int where, u16 *val);
138extern int early_read_config_dword(struct pci_controller *hose, int bus,
139			int dev_fn, int where, u32 *val);
140extern int early_write_config_byte(struct pci_controller *hose, int bus,
141			int dev_fn, int where, u8 val);
142extern int early_write_config_word(struct pci_controller *hose, int bus,
143			int dev_fn, int where, u16 val);
144extern int early_write_config_dword(struct pci_controller *hose, int bus,
145			int dev_fn, int where, u32 val);
146
147extern int early_find_capability(struct pci_controller *hose, int bus,
148				 int dev_fn, int cap);
149
150extern void setup_indirect_pci(struct pci_controller* hose,
151			       resource_size_t cfg_addr,
152			       resource_size_t cfg_data, u32 flags);
153
154extern int indirect_read_config(struct pci_bus *bus, unsigned int devfn,
155				int offset, int len, u32 *val);
156
157extern int __indirect_read_config(struct pci_controller *hose,
158				  unsigned char bus_number, unsigned int devfn,
159				  int offset, int len, u32 *val);
160
161extern int indirect_write_config(struct pci_bus *bus, unsigned int devfn,
162				 int offset, int len, u32 val);
163
164static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
165{
166	return bus->sysdata;
167}
168
169#ifndef CONFIG_PPC64
170
171extern int pci_device_from_OF_node(struct device_node *node,
172				   u8 *bus, u8 *devfn);
173extern void pci_create_OF_bus_map(void);
174
175#else	/* CONFIG_PPC64 */
176
177/*
178 * PCI stuff, for nodes representing PCI devices, pointed to
179 * by device_node->data.
180 */
181struct iommu_table;
182
183struct pci_dn {
184	int     flags;
185#define PCI_DN_FLAG_IOV_VF	0x01
186#define PCI_DN_FLAG_DEAD	0x02    /* Device has been hot-removed */
187
188	int	busno;			/* pci bus number */
189	int	devfn;			/* pci device and function number */
190	int	vendor_id;		/* Vendor ID */
191	int	device_id;		/* Device ID */
192	int	class_code;		/* Device class code */
193
194	struct  pci_dn *parent;
195	struct  pci_controller *phb;	/* for pci devices */
196	struct	iommu_table_group *table_group;	/* for phb's or bridges */
197
198	int	pci_ext_config_space;	/* for pci devices */
199#ifdef CONFIG_EEH
200	struct eeh_dev *edev;		/* eeh device */
201#endif
202#define IODA_INVALID_PE		0xFFFFFFFF
203	unsigned int pe_number;
204#ifdef CONFIG_PCI_IOV
205	int     vf_index;		/* VF index in the PF */
206	u16     vfs_expanded;		/* number of VFs IOV BAR expanded */
207	u16     num_vfs;		/* number of VFs enabled*/
208	unsigned int *pe_num_map;	/* PE# for the first VF PE or array */
209	bool    m64_single_mode;	/* Use M64 BAR in Single Mode */
210#define IODA_INVALID_M64        (-1)
211	int     (*m64_map)[PCI_SRIOV_NUM_BARS];	/* Only used on powernv */
212	int     last_allow_rc;			/* Only used on pseries */
213#endif /* CONFIG_PCI_IOV */
214	int	mps;			/* Maximum Payload Size */
215	struct list_head child_list;
216	struct list_head list;
217	struct resource holes[PCI_SRIOV_NUM_BARS];
218};
219
220/* Get the pointer to a device_node's pci_dn */
221#define PCI_DN(dn)	((struct pci_dn *) (dn)->data)
222
223extern struct pci_dn *pci_get_pdn_by_devfn(struct pci_bus *bus,
224					   int devfn);
225extern struct pci_dn *pci_get_pdn(struct pci_dev *pdev);
226extern struct pci_dn *pci_add_device_node_info(struct pci_controller *hose,
227					       struct device_node *dn);
228extern void pci_remove_device_node_info(struct device_node *dn);
229
230#ifdef CONFIG_PCI_IOV
231struct pci_dn *add_sriov_vf_pdns(struct pci_dev *pdev);
232void remove_sriov_vf_pdns(struct pci_dev *pdev);
233#endif
234
235static inline int pci_device_from_OF_node(struct device_node *np,
236					  u8 *bus, u8 *devfn)
237{
238	if (!PCI_DN(np))
239		return -ENODEV;
240	*bus = PCI_DN(np)->busno;
241	*devfn = PCI_DN(np)->devfn;
242	return 0;
243}
244
245#if defined(CONFIG_EEH)
246static inline struct eeh_dev *pdn_to_eeh_dev(struct pci_dn *pdn)
247{
248	return pdn ? pdn->edev : NULL;
249}
250#else
251#define pdn_to_eeh_dev(x)	(NULL)
252#endif
253
254/** Find the bus corresponding to the indicated device node */
255extern struct pci_bus *pci_find_bus_by_node(struct device_node *dn);
256
257/** Remove all of the PCI devices under this bus */
258extern void pci_hp_remove_devices(struct pci_bus *bus);
259
260/** Discover new pci devices under this bus, and add them */
261extern void pci_hp_add_devices(struct pci_bus *bus);
262
263extern int pcibios_unmap_io_space(struct pci_bus *bus);
264extern int pcibios_map_io_space(struct pci_bus *bus);
265
266#ifdef CONFIG_NUMA
267#define PHB_SET_NODE(PHB, NODE)		((PHB)->node = (NODE))
268#else
269#define PHB_SET_NODE(PHB, NODE)		((PHB)->node = NUMA_NO_NODE)
270#endif
271
272#endif	/* CONFIG_PPC64 */
273
274/* Get the PCI host controller for an OF device */
275extern struct pci_controller *pci_find_hose_for_OF_device(
276			struct device_node* node);
277
278extern struct pci_controller *pci_find_controller_for_domain(int domain_nr);
279
280/* Fill up host controller resources from the OF node */
281extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
282			struct device_node *dev, int primary);
283
284/* Allocate & free a PCI host bridge structure */
285extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev);
286extern void pcibios_free_controller(struct pci_controller *phb);
287extern void pcibios_free_controller_deferred(struct pci_host_bridge *bridge);
288
289#ifdef CONFIG_PCI
290extern int pcibios_vaddr_is_ioport(void __iomem *address);
291#else
292static inline int pcibios_vaddr_is_ioport(void __iomem *address)
293{
294	return 0;
295}
296#endif	/* CONFIG_PCI */
297
298#endif	/* __KERNEL__ */
299#endif	/* _ASM_POWERPC_PCI_BRIDGE_H */