/arch/powerpc/platforms/embedded6xx/hlwd-pic.c

http://github.com/mirrors/linux · C · 235 lines · 152 code · 43 blank · 40 comment · 9 complexity · b8598ad73ad6385260a4ee5132ef6f49 MD5 · raw file

  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * arch/powerpc/platforms/embedded6xx/hlwd-pic.c
  4. *
  5. * Nintendo Wii "Hollywood" interrupt controller support.
  6. * Copyright (C) 2009 The GameCube Linux Team
  7. * Copyright (C) 2009 Albert Herranz
  8. */
  9. #define DRV_MODULE_NAME "hlwd-pic"
  10. #define pr_fmt(fmt) DRV_MODULE_NAME ": " fmt
  11. #include <linux/kernel.h>
  12. #include <linux/irq.h>
  13. #include <linux/of.h>
  14. #include <linux/of_address.h>
  15. #include <linux/of_irq.h>
  16. #include <asm/io.h>
  17. #include "hlwd-pic.h"
  18. #define HLWD_NR_IRQS 32
  19. /*
  20. * Each interrupt has a corresponding bit in both
  21. * the Interrupt Cause (ICR) and Interrupt Mask (IMR) registers.
  22. *
  23. * Enabling/disabling an interrupt line involves asserting/clearing
  24. * the corresponding bit in IMR. ACK'ing a request simply involves
  25. * asserting the corresponding bit in ICR.
  26. */
  27. #define HW_BROADWAY_ICR 0x00
  28. #define HW_BROADWAY_IMR 0x04
  29. #define HW_STARLET_ICR 0x08
  30. #define HW_STARLET_IMR 0x0c
  31. /*
  32. * IRQ chip hooks.
  33. *
  34. */
  35. static void hlwd_pic_mask_and_ack(struct irq_data *d)
  36. {
  37. int irq = irqd_to_hwirq(d);
  38. void __iomem *io_base = irq_data_get_irq_chip_data(d);
  39. u32 mask = 1 << irq;
  40. clrbits32(io_base + HW_BROADWAY_IMR, mask);
  41. out_be32(io_base + HW_BROADWAY_ICR, mask);
  42. }
  43. static void hlwd_pic_ack(struct irq_data *d)
  44. {
  45. int irq = irqd_to_hwirq(d);
  46. void __iomem *io_base = irq_data_get_irq_chip_data(d);
  47. out_be32(io_base + HW_BROADWAY_ICR, 1 << irq);
  48. }
  49. static void hlwd_pic_mask(struct irq_data *d)
  50. {
  51. int irq = irqd_to_hwirq(d);
  52. void __iomem *io_base = irq_data_get_irq_chip_data(d);
  53. clrbits32(io_base + HW_BROADWAY_IMR, 1 << irq);
  54. }
  55. static void hlwd_pic_unmask(struct irq_data *d)
  56. {
  57. int irq = irqd_to_hwirq(d);
  58. void __iomem *io_base = irq_data_get_irq_chip_data(d);
  59. setbits32(io_base + HW_BROADWAY_IMR, 1 << irq);
  60. /* Make sure the ARM (aka. Starlet) doesn't handle this interrupt. */
  61. clrbits32(io_base + HW_STARLET_IMR, 1 << irq);
  62. }
  63. static struct irq_chip hlwd_pic = {
  64. .name = "hlwd-pic",
  65. .irq_ack = hlwd_pic_ack,
  66. .irq_mask_ack = hlwd_pic_mask_and_ack,
  67. .irq_mask = hlwd_pic_mask,
  68. .irq_unmask = hlwd_pic_unmask,
  69. };
  70. /*
  71. * IRQ host hooks.
  72. *
  73. */
  74. static struct irq_domain *hlwd_irq_host;
  75. static int hlwd_pic_map(struct irq_domain *h, unsigned int virq,
  76. irq_hw_number_t hwirq)
  77. {
  78. irq_set_chip_data(virq, h->host_data);
  79. irq_set_status_flags(virq, IRQ_LEVEL);
  80. irq_set_chip_and_handler(virq, &hlwd_pic, handle_level_irq);
  81. return 0;
  82. }
  83. static const struct irq_domain_ops hlwd_irq_domain_ops = {
  84. .map = hlwd_pic_map,
  85. };
  86. static unsigned int __hlwd_pic_get_irq(struct irq_domain *h)
  87. {
  88. void __iomem *io_base = h->host_data;
  89. int irq;
  90. u32 irq_status;
  91. irq_status = in_be32(io_base + HW_BROADWAY_ICR) &
  92. in_be32(io_base + HW_BROADWAY_IMR);
  93. if (irq_status == 0)
  94. return 0; /* no more IRQs pending */
  95. irq = __ffs(irq_status);
  96. return irq_linear_revmap(h, irq);
  97. }
  98. static void hlwd_pic_irq_cascade(struct irq_desc *desc)
  99. {
  100. struct irq_chip *chip = irq_desc_get_chip(desc);
  101. struct irq_domain *irq_domain = irq_desc_get_handler_data(desc);
  102. unsigned int virq;
  103. raw_spin_lock(&desc->lock);
  104. chip->irq_mask(&desc->irq_data); /* IRQ_LEVEL */
  105. raw_spin_unlock(&desc->lock);
  106. virq = __hlwd_pic_get_irq(irq_domain);
  107. if (virq)
  108. generic_handle_irq(virq);
  109. else
  110. pr_err("spurious interrupt!\n");
  111. raw_spin_lock(&desc->lock);
  112. chip->irq_ack(&desc->irq_data); /* IRQ_LEVEL */
  113. if (!irqd_irq_disabled(&desc->irq_data) && chip->irq_unmask)
  114. chip->irq_unmask(&desc->irq_data);
  115. raw_spin_unlock(&desc->lock);
  116. }
  117. /*
  118. * Platform hooks.
  119. *
  120. */
  121. static void __hlwd_quiesce(void __iomem *io_base)
  122. {
  123. /* mask and ack all IRQs */
  124. out_be32(io_base + HW_BROADWAY_IMR, 0);
  125. out_be32(io_base + HW_BROADWAY_ICR, 0xffffffff);
  126. }
  127. static struct irq_domain *hlwd_pic_init(struct device_node *np)
  128. {
  129. struct irq_domain *irq_domain;
  130. struct resource res;
  131. void __iomem *io_base;
  132. int retval;
  133. retval = of_address_to_resource(np, 0, &res);
  134. if (retval) {
  135. pr_err("no io memory range found\n");
  136. return NULL;
  137. }
  138. io_base = ioremap(res.start, resource_size(&res));
  139. if (!io_base) {
  140. pr_err("ioremap failed\n");
  141. return NULL;
  142. }
  143. pr_info("controller at 0x%08x mapped to 0x%p\n", res.start, io_base);
  144. __hlwd_quiesce(io_base);
  145. irq_domain = irq_domain_add_linear(np, HLWD_NR_IRQS,
  146. &hlwd_irq_domain_ops, io_base);
  147. if (!irq_domain) {
  148. pr_err("failed to allocate irq_domain\n");
  149. iounmap(io_base);
  150. return NULL;
  151. }
  152. return irq_domain;
  153. }
  154. unsigned int hlwd_pic_get_irq(void)
  155. {
  156. return __hlwd_pic_get_irq(hlwd_irq_host);
  157. }
  158. /*
  159. * Probe function.
  160. *
  161. */
  162. void hlwd_pic_probe(void)
  163. {
  164. struct irq_domain *host;
  165. struct device_node *np;
  166. const u32 *interrupts;
  167. int cascade_virq;
  168. for_each_compatible_node(np, NULL, "nintendo,hollywood-pic") {
  169. interrupts = of_get_property(np, "interrupts", NULL);
  170. if (interrupts) {
  171. host = hlwd_pic_init(np);
  172. BUG_ON(!host);
  173. cascade_virq = irq_of_parse_and_map(np, 0);
  174. irq_set_handler_data(cascade_virq, host);
  175. irq_set_chained_handler(cascade_virq,
  176. hlwd_pic_irq_cascade);
  177. hlwd_irq_host = host;
  178. break;
  179. }
  180. }
  181. }
  182. /**
  183. * hlwd_quiesce() - quiesce hollywood irq controller
  184. *
  185. * Mask and ack all interrupt sources.
  186. *
  187. */
  188. void hlwd_quiesce(void)
  189. {
  190. void __iomem *io_base = hlwd_irq_host->host_data;
  191. __hlwd_quiesce(io_base);
  192. }