/arch/powerpc/platforms/83xx/km83xx.c

http://github.com/mirrors/linux · C · 189 lines · 111 code · 23 blank · 55 comment · 16 complexity · 3c2f5a00db9709439dc387e10adb3692 MD5 · raw file

  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright 2008-2011 DENX Software Engineering GmbH
  4. * Author: Heiko Schocher <hs@denx.de>
  5. *
  6. * Description:
  7. * Keymile 83xx platform specific routines.
  8. */
  9. #include <linux/stddef.h>
  10. #include <linux/kernel.h>
  11. #include <linux/init.h>
  12. #include <linux/errno.h>
  13. #include <linux/reboot.h>
  14. #include <linux/pci.h>
  15. #include <linux/kdev_t.h>
  16. #include <linux/major.h>
  17. #include <linux/console.h>
  18. #include <linux/delay.h>
  19. #include <linux/seq_file.h>
  20. #include <linux/root_dev.h>
  21. #include <linux/initrd.h>
  22. #include <linux/of_platform.h>
  23. #include <linux/of_device.h>
  24. #include <linux/atomic.h>
  25. #include <linux/time.h>
  26. #include <linux/io.h>
  27. #include <asm/machdep.h>
  28. #include <asm/ipic.h>
  29. #include <asm/irq.h>
  30. #include <asm/prom.h>
  31. #include <asm/udbg.h>
  32. #include <sysdev/fsl_soc.h>
  33. #include <sysdev/fsl_pci.h>
  34. #include <soc/fsl/qe/qe.h>
  35. #include "mpc83xx.h"
  36. #define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revision field */
  37. static void quirk_mpc8360e_qe_enet10(void)
  38. {
  39. /*
  40. * handle mpc8360E Erratum QE_ENET10:
  41. * RGMII AC values do not meet the specification
  42. */
  43. uint svid = mfspr(SPRN_SVR);
  44. struct device_node *np_par;
  45. struct resource res;
  46. void __iomem *base;
  47. int ret;
  48. np_par = of_find_node_by_name(NULL, "par_io");
  49. if (np_par == NULL) {
  50. pr_warn("%s couldn't find par_io node\n", __func__);
  51. return;
  52. }
  53. /* Map Parallel I/O ports registers */
  54. ret = of_address_to_resource(np_par, 0, &res);
  55. if (ret) {
  56. pr_warn("%s couldn't map par_io registers\n", __func__);
  57. goto out;
  58. }
  59. base = ioremap(res.start, resource_size(&res));
  60. if (!base)
  61. goto out;
  62. /*
  63. * set output delay adjustments to default values according
  64. * table 5 in Errata Rev. 5, 9/2011:
  65. *
  66. * write 0b01 to UCC1 bits 18:19
  67. * write 0b01 to UCC2 option 1 bits 4:5
  68. * write 0b01 to UCC2 option 2 bits 16:17
  69. */
  70. clrsetbits_be32((base + 0xa8), 0x0c00f000, 0x04005000);
  71. /*
  72. * set output delay adjustments to default values according
  73. * table 3-13 in Reference Manual Rev.3 05/2010:
  74. *
  75. * write 0b01 to UCC2 option 2 bits 16:17
  76. * write 0b0101 to UCC1 bits 20:23
  77. * write 0b0101 to UCC2 option 1 bits 24:27
  78. */
  79. clrsetbits_be32((base + 0xac), 0x0000cff0, 0x00004550);
  80. if (SVR_REV(svid) == 0x0021) {
  81. /*
  82. * UCC2 option 1: write 0b1010 to bits 24:27
  83. * at address IMMRBAR+0x14AC
  84. */
  85. clrsetbits_be32((base + 0xac), 0x000000f0, 0x000000a0);
  86. } else if (SVR_REV(svid) == 0x0020) {
  87. /*
  88. * UCC1: write 0b11 to bits 18:19
  89. * at address IMMRBAR+0x14A8
  90. */
  91. setbits32((base + 0xa8), 0x00003000);
  92. /*
  93. * UCC2 option 1: write 0b11 to bits 4:5
  94. * at address IMMRBAR+0x14A8
  95. */
  96. setbits32((base + 0xa8), 0x0c000000);
  97. /*
  98. * UCC2 option 2: write 0b11 to bits 16:17
  99. * at address IMMRBAR+0x14AC
  100. */
  101. setbits32((base + 0xac), 0x0000c000);
  102. }
  103. iounmap(base);
  104. out:
  105. of_node_put(np_par);
  106. }
  107. /* ************************************************************************
  108. *
  109. * Setup the architecture
  110. *
  111. */
  112. static void __init mpc83xx_km_setup_arch(void)
  113. {
  114. #ifdef CONFIG_QUICC_ENGINE
  115. struct device_node *np;
  116. #endif
  117. mpc83xx_setup_arch();
  118. #ifdef CONFIG_QUICC_ENGINE
  119. np = of_find_node_by_name(NULL, "par_io");
  120. if (np != NULL) {
  121. par_io_init(np);
  122. of_node_put(np);
  123. for_each_node_by_name(np, "spi")
  124. par_io_of_config(np);
  125. for_each_node_by_name(np, "ucc")
  126. par_io_of_config(np);
  127. /* Only apply this quirk when par_io is available */
  128. np = of_find_compatible_node(NULL, "network", "ucc_geth");
  129. if (np != NULL) {
  130. quirk_mpc8360e_qe_enet10();
  131. of_node_put(np);
  132. }
  133. }
  134. #endif /* CONFIG_QUICC_ENGINE */
  135. }
  136. machine_device_initcall(mpc83xx_km, mpc83xx_declare_of_platform_devices);
  137. /* list of the supported boards */
  138. static char *board[] __initdata = {
  139. "Keymile,KMETER1",
  140. "Keymile,kmpbec8321",
  141. NULL
  142. };
  143. /*
  144. * Called very early, MMU is off, device-tree isn't unflattened
  145. */
  146. static int __init mpc83xx_km_probe(void)
  147. {
  148. int i = 0;
  149. while (board[i]) {
  150. if (of_machine_is_compatible(board[i]))
  151. break;
  152. i++;
  153. }
  154. return (board[i] != NULL);
  155. }
  156. define_machine(mpc83xx_km) {
  157. .name = "mpc83xx-km-platform",
  158. .probe = mpc83xx_km_probe,
  159. .setup_arch = mpc83xx_km_setup_arch,
  160. .init_IRQ = mpc83xx_ipic_init_IRQ,
  161. .get_irq = ipic_get_irq,
  162. .restart = mpc83xx_restart,
  163. .time_init = mpc83xx_time_init,
  164. .calibrate_decr = generic_calibrate_decr,
  165. .progress = udbg_progress,
  166. };