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/arch/powerpc/platforms/cell/celleb_scc_uhc.c

http://github.com/mirrors/linux
C | 95 lines | 56 code | 13 blank | 26 comment | 5 complexity | 9b2edabcdb6176c1c30a38d5b117daac MD5 | raw file
 1/*
 2 * SCC (Super Companion Chip) UHC setup
 3 *
 4 * (C) Copyright 2006-2007 TOSHIBA CORPORATION
 5 *
 6 * This program is free software; you can redistribute it and/or modify
 7 * it under the terms of the GNU General Public License as published by
 8 * the Free Software Foundation; either version 2 of the License, or
 9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#include <linux/kernel.h>
22#include <linux/pci.h>
23
24#include <asm/delay.h>
25#include <asm/io.h>
26#include <asm/machdep.h>
27
28#include "celleb_scc.h"
29
30#define UHC_RESET_WAIT_MAX 10000
31
32static inline int uhc_clkctrl_ready(u32 val)
33{
34	const u32 mask = SCC_UHC_USBCEN | SCC_UHC_USBCEN;
35	return((val & mask) == mask);
36}
37
38/*
39 * UHC(usb host controller) enable function.
40 * affect to both of OHCI and EHCI core module.
41 */
42static void enable_scc_uhc(struct pci_dev *dev)
43{
44	void __iomem *uhc_base;
45	u32 __iomem *uhc_clkctrl;
46	u32 __iomem *uhc_ecmode;
47	u32 val = 0;
48	int i;
49
50	if (!machine_is(celleb_beat) &&
51	    !machine_is(celleb_native))
52		return;
53
54	uhc_base = ioremap(pci_resource_start(dev, 0),
55			   pci_resource_len(dev, 0));
56	if (!uhc_base) {
57		printk(KERN_ERR "failed to map UHC register base.\n");
58		return;
59	}
60	uhc_clkctrl = uhc_base + SCC_UHC_CKRCTRL;
61	uhc_ecmode  = uhc_base + SCC_UHC_ECMODE;
62
63	/* setup for normal mode */
64	val |= SCC_UHC_F48MCKLEN;
65	out_be32(uhc_clkctrl, val);
66	val |= SCC_UHC_PHY_SUSPEND_SEL;
67	out_be32(uhc_clkctrl, val);
68	udelay(10);
69	val |= SCC_UHC_PHYEN;
70	out_be32(uhc_clkctrl, val);
71	udelay(50);
72
73	/* disable reset */
74	val |= SCC_UHC_HCLKEN;
75	out_be32(uhc_clkctrl, val);
76	val |= (SCC_UHC_USBCEN | SCC_UHC_USBEN);
77	out_be32(uhc_clkctrl, val);
78	i = 0;
79	while (!uhc_clkctrl_ready(in_be32(uhc_clkctrl))) {
80		udelay(10);
81		if (i++ > UHC_RESET_WAIT_MAX) {
82			printk(KERN_ERR "Failed to disable UHC reset %x\n",
83			       in_be32(uhc_clkctrl));
84			break;
85		}
86	}
87
88	/* Endian Conversion Mode for Master ALL area */
89	out_be32(uhc_ecmode, SCC_UHC_ECMODE_BY_BYTE);
90
91	iounmap(uhc_base);
92}
93
94DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
95		 PCI_DEVICE_ID_TOSHIBA_SCC_USB, enable_scc_uhc);