/arch/powerpc/platforms/85xx/mpc85xx_ads.c

http://github.com/mirrors/linux · C · 171 lines · 127 code · 25 blank · 19 comment · 3 complexity · 911cbe673794a0027f99747ab79afa9d MD5 · raw file

  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * MPC85xx setup and early boot code plus other random bits.
  4. *
  5. * Maintained by Kumar Gala (see MAINTAINERS for contact information)
  6. *
  7. * Copyright 2005 Freescale Semiconductor Inc.
  8. */
  9. #include <linux/stddef.h>
  10. #include <linux/kernel.h>
  11. #include <linux/pci.h>
  12. #include <linux/kdev_t.h>
  13. #include <linux/delay.h>
  14. #include <linux/seq_file.h>
  15. #include <linux/of_platform.h>
  16. #include <asm/time.h>
  17. #include <asm/machdep.h>
  18. #include <asm/pci-bridge.h>
  19. #include <asm/mpic.h>
  20. #include <mm/mmu_decl.h>
  21. #include <asm/udbg.h>
  22. #include <sysdev/fsl_soc.h>
  23. #include <sysdev/fsl_pci.h>
  24. #ifdef CONFIG_CPM2
  25. #include <asm/cpm2.h>
  26. #include <sysdev/cpm2_pic.h>
  27. #endif
  28. #include "mpc85xx.h"
  29. static void __init mpc85xx_ads_pic_init(void)
  30. {
  31. struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN,
  32. 0, 256, " OpenPIC ");
  33. BUG_ON(mpic == NULL);
  34. mpic_init(mpic);
  35. mpc85xx_cpm2_pic_init();
  36. }
  37. /*
  38. * Setup the architecture
  39. */
  40. #ifdef CONFIG_CPM2
  41. struct cpm_pin {
  42. int port, pin, flags;
  43. };
  44. static const struct cpm_pin mpc8560_ads_pins[] = {
  45. /* SCC1 */
  46. {3, 29, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  47. {3, 30, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
  48. {3, 31, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  49. /* SCC2 */
  50. {2, 12, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  51. {2, 13, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  52. {3, 26, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  53. {3, 27, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  54. {3, 28, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  55. /* FCC2 */
  56. {1, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  57. {1, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  58. {1, 20, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  59. {1, 21, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  60. {1, 22, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  61. {1, 23, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  62. {1, 24, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  63. {1, 25, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  64. {1, 26, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  65. {1, 27, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  66. {1, 28, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  67. {1, 29, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
  68. {1, 30, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  69. {1, 31, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  70. {2, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* CLK14 */
  71. {2, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* CLK13 */
  72. /* FCC3 */
  73. {1, 4, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  74. {1, 5, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  75. {1, 6, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  76. {1, 8, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  77. {1, 9, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  78. {1, 10, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  79. {1, 11, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  80. {1, 12, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  81. {1, 13, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  82. {1, 14, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  83. {1, 15, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  84. {1, 16, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  85. {1, 17, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  86. {2, 16, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* CLK16 */
  87. {2, 17, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* CLK15 */
  88. {2, 27, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  89. };
  90. static void __init init_ioports(void)
  91. {
  92. int i;
  93. for (i = 0; i < ARRAY_SIZE(mpc8560_ads_pins); i++) {
  94. const struct cpm_pin *pin = &mpc8560_ads_pins[i];
  95. cpm2_set_pin(pin->port, pin->pin, pin->flags);
  96. }
  97. cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_RX);
  98. cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_TX);
  99. cpm2_clk_setup(CPM_CLK_SCC2, CPM_BRG2, CPM_CLK_RX);
  100. cpm2_clk_setup(CPM_CLK_SCC2, CPM_BRG2, CPM_CLK_TX);
  101. cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK13, CPM_CLK_RX);
  102. cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK14, CPM_CLK_TX);
  103. cpm2_clk_setup(CPM_CLK_FCC3, CPM_CLK15, CPM_CLK_RX);
  104. cpm2_clk_setup(CPM_CLK_FCC3, CPM_CLK16, CPM_CLK_TX);
  105. }
  106. #endif
  107. static void __init mpc85xx_ads_setup_arch(void)
  108. {
  109. if (ppc_md.progress)
  110. ppc_md.progress("mpc85xx_ads_setup_arch()", 0);
  111. #ifdef CONFIG_CPM2
  112. cpm2_reset();
  113. init_ioports();
  114. #endif
  115. fsl_pci_assign_primary();
  116. }
  117. static void mpc85xx_ads_show_cpuinfo(struct seq_file *m)
  118. {
  119. uint pvid, svid, phid1;
  120. pvid = mfspr(SPRN_PVR);
  121. svid = mfspr(SPRN_SVR);
  122. seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
  123. seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
  124. seq_printf(m, "SVR\t\t: 0x%x\n", svid);
  125. /* Display cpu Pll setting */
  126. phid1 = mfspr(SPRN_HID1);
  127. seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
  128. }
  129. machine_arch_initcall(mpc85xx_ads, mpc85xx_common_publish_devices);
  130. /*
  131. * Called very early, device-tree isn't unflattened
  132. */
  133. static int __init mpc85xx_ads_probe(void)
  134. {
  135. return of_machine_is_compatible("MPC85xxADS");
  136. }
  137. define_machine(mpc85xx_ads) {
  138. .name = "MPC85xx ADS",
  139. .probe = mpc85xx_ads_probe,
  140. .setup_arch = mpc85xx_ads_setup_arch,
  141. .init_IRQ = mpc85xx_ads_pic_init,
  142. .show_cpuinfo = mpc85xx_ads_show_cpuinfo,
  143. .get_irq = mpic_get_irq,
  144. .calibrate_decr = generic_calibrate_decr,
  145. .progress = udbg_progress,
  146. };