/arch/powerpc/platforms/52xx/mpc52xx_gpt.c

http://github.com/mirrors/linux · C · 788 lines · 514 code · 128 blank · 146 comment · 44 complexity · 5107c436ec6bdae3f2a3d79157d7b599 MD5 · raw file

  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * MPC5200 General Purpose Timer device driver
  4. *
  5. * Copyright (c) 2009 Secret Lab Technologies Ltd.
  6. * Copyright (c) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
  7. *
  8. * This file is a driver for the the General Purpose Timer (gpt) devices
  9. * found on the MPC5200 SoC. Each timer has an IO pin which can be used
  10. * for GPIO or can be used to raise interrupts. The timer function can
  11. * be used independently from the IO pin, or it can be used to control
  12. * output signals or measure input signals.
  13. *
  14. * This driver supports the GPIO and IRQ controller functions of the GPT
  15. * device. Timer functions are not yet supported.
  16. *
  17. * The timer gpt0 can be used as watchdog (wdt). If the wdt mode is used,
  18. * this prevents the use of any gpt0 gpt function (i.e. they will fail with
  19. * -EBUSY). Thus, the safety wdt function always has precedence over the gpt
  20. * function. If the kernel has been compiled with CONFIG_WATCHDOG_NOWAYOUT,
  21. * this means that gpt0 is locked in wdt mode until the next reboot - this
  22. * may be a requirement in safety applications.
  23. *
  24. * To use the GPIO function, the following two properties must be added
  25. * to the device tree node for the gpt device (typically in the .dts file
  26. * for the board):
  27. * gpio-controller;
  28. * #gpio-cells = < 2 >;
  29. * This driver will register the GPIO pin if it finds the gpio-controller
  30. * property in the device tree.
  31. *
  32. * To use the IRQ controller function, the following two properties must
  33. * be added to the device tree node for the gpt device:
  34. * interrupt-controller;
  35. * #interrupt-cells = < 1 >;
  36. * The IRQ controller binding only uses one cell to specify the interrupt,
  37. * and the IRQ flags are encoded in the cell. A cell is not used to encode
  38. * the IRQ number because the GPT only has a single IRQ source. For flags,
  39. * a value of '1' means rising edge sensitive and '2' means falling edge.
  40. *
  41. * The GPIO and the IRQ controller functions can be used at the same time,
  42. * but in this use case the IO line will only work as an input. Trying to
  43. * use it as a GPIO output will not work.
  44. *
  45. * When using the GPIO line as an output, it can either be driven as normal
  46. * IO, or it can be an Open Collector (OC) output. At the moment it is the
  47. * responsibility of either the bootloader or the platform setup code to set
  48. * the output mode. This driver does not change the output mode setting.
  49. */
  50. #include <linux/device.h>
  51. #include <linux/irq.h>
  52. #include <linux/interrupt.h>
  53. #include <linux/io.h>
  54. #include <linux/list.h>
  55. #include <linux/mutex.h>
  56. #include <linux/of.h>
  57. #include <linux/of_platform.h>
  58. #include <linux/of_gpio.h>
  59. #include <linux/kernel.h>
  60. #include <linux/slab.h>
  61. #include <linux/fs.h>
  62. #include <linux/watchdog.h>
  63. #include <linux/miscdevice.h>
  64. #include <linux/uaccess.h>
  65. #include <linux/module.h>
  66. #include <asm/div64.h>
  67. #include <asm/mpc52xx.h>
  68. MODULE_DESCRIPTION("Freescale MPC52xx gpt driver");
  69. MODULE_AUTHOR("Sascha Hauer, Grant Likely, Albrecht Dreß");
  70. MODULE_LICENSE("GPL");
  71. /**
  72. * struct mpc52xx_gpt - Private data structure for MPC52xx GPT driver
  73. * @dev: pointer to device structure
  74. * @regs: virtual address of GPT registers
  75. * @lock: spinlock to coordinate between different functions.
  76. * @gc: gpio_chip instance structure; used when GPIO is enabled
  77. * @irqhost: Pointer to irq_domain instance; used when IRQ mode is supported
  78. * @wdt_mode: only relevant for gpt0: bit 0 (MPC52xx_GPT_CAN_WDT) indicates
  79. * if the gpt may be used as wdt, bit 1 (MPC52xx_GPT_IS_WDT) indicates
  80. * if the timer is actively used as wdt which blocks gpt functions
  81. */
  82. struct mpc52xx_gpt_priv {
  83. struct list_head list; /* List of all GPT devices */
  84. struct device *dev;
  85. struct mpc52xx_gpt __iomem *regs;
  86. raw_spinlock_t lock;
  87. struct irq_domain *irqhost;
  88. u32 ipb_freq;
  89. u8 wdt_mode;
  90. #if defined(CONFIG_GPIOLIB)
  91. struct gpio_chip gc;
  92. #endif
  93. };
  94. LIST_HEAD(mpc52xx_gpt_list);
  95. DEFINE_MUTEX(mpc52xx_gpt_list_mutex);
  96. #define MPC52xx_GPT_MODE_MS_MASK (0x07)
  97. #define MPC52xx_GPT_MODE_MS_IC (0x01)
  98. #define MPC52xx_GPT_MODE_MS_OC (0x02)
  99. #define MPC52xx_GPT_MODE_MS_PWM (0x03)
  100. #define MPC52xx_GPT_MODE_MS_GPIO (0x04)
  101. #define MPC52xx_GPT_MODE_GPIO_MASK (0x30)
  102. #define MPC52xx_GPT_MODE_GPIO_OUT_LOW (0x20)
  103. #define MPC52xx_GPT_MODE_GPIO_OUT_HIGH (0x30)
  104. #define MPC52xx_GPT_MODE_COUNTER_ENABLE (0x1000)
  105. #define MPC52xx_GPT_MODE_CONTINUOUS (0x0400)
  106. #define MPC52xx_GPT_MODE_OPEN_DRAIN (0x0200)
  107. #define MPC52xx_GPT_MODE_IRQ_EN (0x0100)
  108. #define MPC52xx_GPT_MODE_WDT_EN (0x8000)
  109. #define MPC52xx_GPT_MODE_ICT_MASK (0x030000)
  110. #define MPC52xx_GPT_MODE_ICT_RISING (0x010000)
  111. #define MPC52xx_GPT_MODE_ICT_FALLING (0x020000)
  112. #define MPC52xx_GPT_MODE_ICT_TOGGLE (0x030000)
  113. #define MPC52xx_GPT_MODE_WDT_PING (0xa5)
  114. #define MPC52xx_GPT_STATUS_IRQMASK (0x000f)
  115. #define MPC52xx_GPT_CAN_WDT (1 << 0)
  116. #define MPC52xx_GPT_IS_WDT (1 << 1)
  117. /* ---------------------------------------------------------------------
  118. * Cascaded interrupt controller hooks
  119. */
  120. static void mpc52xx_gpt_irq_unmask(struct irq_data *d)
  121. {
  122. struct mpc52xx_gpt_priv *gpt = irq_data_get_irq_chip_data(d);
  123. unsigned long flags;
  124. raw_spin_lock_irqsave(&gpt->lock, flags);
  125. setbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN);
  126. raw_spin_unlock_irqrestore(&gpt->lock, flags);
  127. }
  128. static void mpc52xx_gpt_irq_mask(struct irq_data *d)
  129. {
  130. struct mpc52xx_gpt_priv *gpt = irq_data_get_irq_chip_data(d);
  131. unsigned long flags;
  132. raw_spin_lock_irqsave(&gpt->lock, flags);
  133. clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN);
  134. raw_spin_unlock_irqrestore(&gpt->lock, flags);
  135. }
  136. static void mpc52xx_gpt_irq_ack(struct irq_data *d)
  137. {
  138. struct mpc52xx_gpt_priv *gpt = irq_data_get_irq_chip_data(d);
  139. out_be32(&gpt->regs->status, MPC52xx_GPT_STATUS_IRQMASK);
  140. }
  141. static int mpc52xx_gpt_irq_set_type(struct irq_data *d, unsigned int flow_type)
  142. {
  143. struct mpc52xx_gpt_priv *gpt = irq_data_get_irq_chip_data(d);
  144. unsigned long flags;
  145. u32 reg;
  146. dev_dbg(gpt->dev, "%s: virq=%i type=%x\n", __func__, d->irq, flow_type);
  147. raw_spin_lock_irqsave(&gpt->lock, flags);
  148. reg = in_be32(&gpt->regs->mode) & ~MPC52xx_GPT_MODE_ICT_MASK;
  149. if (flow_type & IRQF_TRIGGER_RISING)
  150. reg |= MPC52xx_GPT_MODE_ICT_RISING;
  151. if (flow_type & IRQF_TRIGGER_FALLING)
  152. reg |= MPC52xx_GPT_MODE_ICT_FALLING;
  153. out_be32(&gpt->regs->mode, reg);
  154. raw_spin_unlock_irqrestore(&gpt->lock, flags);
  155. return 0;
  156. }
  157. static struct irq_chip mpc52xx_gpt_irq_chip = {
  158. .name = "MPC52xx GPT",
  159. .irq_unmask = mpc52xx_gpt_irq_unmask,
  160. .irq_mask = mpc52xx_gpt_irq_mask,
  161. .irq_ack = mpc52xx_gpt_irq_ack,
  162. .irq_set_type = mpc52xx_gpt_irq_set_type,
  163. };
  164. static void mpc52xx_gpt_irq_cascade(struct irq_desc *desc)
  165. {
  166. struct mpc52xx_gpt_priv *gpt = irq_desc_get_handler_data(desc);
  167. int sub_virq;
  168. u32 status;
  169. status = in_be32(&gpt->regs->status) & MPC52xx_GPT_STATUS_IRQMASK;
  170. if (status) {
  171. sub_virq = irq_linear_revmap(gpt->irqhost, 0);
  172. generic_handle_irq(sub_virq);
  173. }
  174. }
  175. static int mpc52xx_gpt_irq_map(struct irq_domain *h, unsigned int virq,
  176. irq_hw_number_t hw)
  177. {
  178. struct mpc52xx_gpt_priv *gpt = h->host_data;
  179. dev_dbg(gpt->dev, "%s: h=%p, virq=%i\n", __func__, h, virq);
  180. irq_set_chip_data(virq, gpt);
  181. irq_set_chip_and_handler(virq, &mpc52xx_gpt_irq_chip, handle_edge_irq);
  182. return 0;
  183. }
  184. static int mpc52xx_gpt_irq_xlate(struct irq_domain *h, struct device_node *ct,
  185. const u32 *intspec, unsigned int intsize,
  186. irq_hw_number_t *out_hwirq,
  187. unsigned int *out_flags)
  188. {
  189. struct mpc52xx_gpt_priv *gpt = h->host_data;
  190. dev_dbg(gpt->dev, "%s: flags=%i\n", __func__, intspec[0]);
  191. if ((intsize < 1) || (intspec[0] > 3)) {
  192. dev_err(gpt->dev, "bad irq specifier in %pOF\n", ct);
  193. return -EINVAL;
  194. }
  195. *out_hwirq = 0; /* The GPT only has 1 IRQ line */
  196. *out_flags = intspec[0];
  197. return 0;
  198. }
  199. static const struct irq_domain_ops mpc52xx_gpt_irq_ops = {
  200. .map = mpc52xx_gpt_irq_map,
  201. .xlate = mpc52xx_gpt_irq_xlate,
  202. };
  203. static void
  204. mpc52xx_gpt_irq_setup(struct mpc52xx_gpt_priv *gpt, struct device_node *node)
  205. {
  206. int cascade_virq;
  207. unsigned long flags;
  208. u32 mode;
  209. cascade_virq = irq_of_parse_and_map(node, 0);
  210. if (!cascade_virq)
  211. return;
  212. gpt->irqhost = irq_domain_add_linear(node, 1, &mpc52xx_gpt_irq_ops, gpt);
  213. if (!gpt->irqhost) {
  214. dev_err(gpt->dev, "irq_domain_add_linear() failed\n");
  215. return;
  216. }
  217. irq_set_handler_data(cascade_virq, gpt);
  218. irq_set_chained_handler(cascade_virq, mpc52xx_gpt_irq_cascade);
  219. /* If the GPT is currently disabled, then change it to be in Input
  220. * Capture mode. If the mode is non-zero, then the pin could be
  221. * already in use for something. */
  222. raw_spin_lock_irqsave(&gpt->lock, flags);
  223. mode = in_be32(&gpt->regs->mode);
  224. if ((mode & MPC52xx_GPT_MODE_MS_MASK) == 0)
  225. out_be32(&gpt->regs->mode, mode | MPC52xx_GPT_MODE_MS_IC);
  226. raw_spin_unlock_irqrestore(&gpt->lock, flags);
  227. dev_dbg(gpt->dev, "%s() complete. virq=%i\n", __func__, cascade_virq);
  228. }
  229. /* ---------------------------------------------------------------------
  230. * GPIOLIB hooks
  231. */
  232. #if defined(CONFIG_GPIOLIB)
  233. static int mpc52xx_gpt_gpio_get(struct gpio_chip *gc, unsigned int gpio)
  234. {
  235. struct mpc52xx_gpt_priv *gpt = gpiochip_get_data(gc);
  236. return (in_be32(&gpt->regs->status) >> 8) & 1;
  237. }
  238. static void
  239. mpc52xx_gpt_gpio_set(struct gpio_chip *gc, unsigned int gpio, int v)
  240. {
  241. struct mpc52xx_gpt_priv *gpt = gpiochip_get_data(gc);
  242. unsigned long flags;
  243. u32 r;
  244. dev_dbg(gpt->dev, "%s: gpio:%d v:%d\n", __func__, gpio, v);
  245. r = v ? MPC52xx_GPT_MODE_GPIO_OUT_HIGH : MPC52xx_GPT_MODE_GPIO_OUT_LOW;
  246. raw_spin_lock_irqsave(&gpt->lock, flags);
  247. clrsetbits_be32(&gpt->regs->mode, MPC52xx_GPT_MODE_GPIO_MASK, r);
  248. raw_spin_unlock_irqrestore(&gpt->lock, flags);
  249. }
  250. static int mpc52xx_gpt_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
  251. {
  252. struct mpc52xx_gpt_priv *gpt = gpiochip_get_data(gc);
  253. unsigned long flags;
  254. dev_dbg(gpt->dev, "%s: gpio:%d\n", __func__, gpio);
  255. raw_spin_lock_irqsave(&gpt->lock, flags);
  256. clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_GPIO_MASK);
  257. raw_spin_unlock_irqrestore(&gpt->lock, flags);
  258. return 0;
  259. }
  260. static int
  261. mpc52xx_gpt_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
  262. {
  263. mpc52xx_gpt_gpio_set(gc, gpio, val);
  264. return 0;
  265. }
  266. static void
  267. mpc52xx_gpt_gpio_setup(struct mpc52xx_gpt_priv *gpt, struct device_node *node)
  268. {
  269. int rc;
  270. /* Only setup GPIO if the device tree claims the GPT is
  271. * a GPIO controller */
  272. if (!of_find_property(node, "gpio-controller", NULL))
  273. return;
  274. gpt->gc.label = kasprintf(GFP_KERNEL, "%pOF", node);
  275. if (!gpt->gc.label) {
  276. dev_err(gpt->dev, "out of memory\n");
  277. return;
  278. }
  279. gpt->gc.ngpio = 1;
  280. gpt->gc.direction_input = mpc52xx_gpt_gpio_dir_in;
  281. gpt->gc.direction_output = mpc52xx_gpt_gpio_dir_out;
  282. gpt->gc.get = mpc52xx_gpt_gpio_get;
  283. gpt->gc.set = mpc52xx_gpt_gpio_set;
  284. gpt->gc.base = -1;
  285. gpt->gc.of_node = node;
  286. /* Setup external pin in GPIO mode */
  287. clrsetbits_be32(&gpt->regs->mode, MPC52xx_GPT_MODE_MS_MASK,
  288. MPC52xx_GPT_MODE_MS_GPIO);
  289. rc = gpiochip_add_data(&gpt->gc, gpt);
  290. if (rc)
  291. dev_err(gpt->dev, "gpiochip_add_data() failed; rc=%i\n", rc);
  292. dev_dbg(gpt->dev, "%s() complete.\n", __func__);
  293. }
  294. #else /* defined(CONFIG_GPIOLIB) */
  295. static void
  296. mpc52xx_gpt_gpio_setup(struct mpc52xx_gpt_priv *p, struct device_node *np) { }
  297. #endif /* defined(CONFIG_GPIOLIB) */
  298. /***********************************************************************
  299. * Timer API
  300. */
  301. /**
  302. * mpc52xx_gpt_from_irq - Return the GPT device associated with an IRQ number
  303. * @irq: irq of timer.
  304. */
  305. struct mpc52xx_gpt_priv *mpc52xx_gpt_from_irq(int irq)
  306. {
  307. struct mpc52xx_gpt_priv *gpt;
  308. struct list_head *pos;
  309. /* Iterate over the list of timers looking for a matching device */
  310. mutex_lock(&mpc52xx_gpt_list_mutex);
  311. list_for_each(pos, &mpc52xx_gpt_list) {
  312. gpt = container_of(pos, struct mpc52xx_gpt_priv, list);
  313. if (gpt->irqhost && irq == irq_linear_revmap(gpt->irqhost, 0)) {
  314. mutex_unlock(&mpc52xx_gpt_list_mutex);
  315. return gpt;
  316. }
  317. }
  318. mutex_unlock(&mpc52xx_gpt_list_mutex);
  319. return NULL;
  320. }
  321. EXPORT_SYMBOL(mpc52xx_gpt_from_irq);
  322. static int mpc52xx_gpt_do_start(struct mpc52xx_gpt_priv *gpt, u64 period,
  323. int continuous, int as_wdt)
  324. {
  325. u32 clear, set;
  326. u64 clocks;
  327. u32 prescale;
  328. unsigned long flags;
  329. clear = MPC52xx_GPT_MODE_MS_MASK | MPC52xx_GPT_MODE_CONTINUOUS;
  330. set = MPC52xx_GPT_MODE_MS_GPIO | MPC52xx_GPT_MODE_COUNTER_ENABLE;
  331. if (as_wdt) {
  332. clear |= MPC52xx_GPT_MODE_IRQ_EN;
  333. set |= MPC52xx_GPT_MODE_WDT_EN;
  334. } else if (continuous)
  335. set |= MPC52xx_GPT_MODE_CONTINUOUS;
  336. /* Determine the number of clocks in the requested period. 64 bit
  337. * arithmatic is done here to preserve the precision until the value
  338. * is scaled back down into the u32 range. Period is in 'ns', bus
  339. * frequency is in Hz. */
  340. clocks = period * (u64)gpt->ipb_freq;
  341. do_div(clocks, 1000000000); /* Scale it down to ns range */
  342. /* This device cannot handle a clock count greater than 32 bits */
  343. if (clocks > 0xffffffff)
  344. return -EINVAL;
  345. /* Calculate the prescaler and count values from the clocks value.
  346. * 'clocks' is the number of clock ticks in the period. The timer
  347. * has 16 bit precision and a 16 bit prescaler. Prescaler is
  348. * calculated by integer dividing the clocks by 0x10000 (shifting
  349. * down 16 bits) to obtain the smallest possible divisor for clocks
  350. * to get a 16 bit count value.
  351. *
  352. * Note: the prescale register is '1' based, not '0' based. ie. a
  353. * value of '1' means divide the clock by one. 0xffff divides the
  354. * clock by 0xffff. '0x0000' does not divide by zero, but wraps
  355. * around and divides by 0x10000. That is why prescale must be
  356. * a u32 variable, not a u16, for this calculation. */
  357. prescale = (clocks >> 16) + 1;
  358. do_div(clocks, prescale);
  359. if (clocks > 0xffff) {
  360. pr_err("calculation error; prescale:%x clocks:%llx\n",
  361. prescale, clocks);
  362. return -EINVAL;
  363. }
  364. /* Set and enable the timer, reject an attempt to use a wdt as gpt */
  365. raw_spin_lock_irqsave(&gpt->lock, flags);
  366. if (as_wdt)
  367. gpt->wdt_mode |= MPC52xx_GPT_IS_WDT;
  368. else if ((gpt->wdt_mode & MPC52xx_GPT_IS_WDT) != 0) {
  369. raw_spin_unlock_irqrestore(&gpt->lock, flags);
  370. return -EBUSY;
  371. }
  372. out_be32(&gpt->regs->count, prescale << 16 | clocks);
  373. clrsetbits_be32(&gpt->regs->mode, clear, set);
  374. raw_spin_unlock_irqrestore(&gpt->lock, flags);
  375. return 0;
  376. }
  377. /**
  378. * mpc52xx_gpt_start_timer - Set and enable the GPT timer
  379. * @gpt: Pointer to gpt private data structure
  380. * @period: period of timer in ns; max. ~130s @ 33MHz IPB clock
  381. * @continuous: set to 1 to make timer continuous free running
  382. *
  383. * An interrupt will be generated every time the timer fires
  384. */
  385. int mpc52xx_gpt_start_timer(struct mpc52xx_gpt_priv *gpt, u64 period,
  386. int continuous)
  387. {
  388. return mpc52xx_gpt_do_start(gpt, period, continuous, 0);
  389. }
  390. EXPORT_SYMBOL(mpc52xx_gpt_start_timer);
  391. /**
  392. * mpc52xx_gpt_stop_timer - Stop a gpt
  393. * @gpt: Pointer to gpt private data structure
  394. *
  395. * Returns an error if attempting to stop a wdt
  396. */
  397. int mpc52xx_gpt_stop_timer(struct mpc52xx_gpt_priv *gpt)
  398. {
  399. unsigned long flags;
  400. /* reject the operation if the timer is used as watchdog (gpt 0 only) */
  401. raw_spin_lock_irqsave(&gpt->lock, flags);
  402. if ((gpt->wdt_mode & MPC52xx_GPT_IS_WDT) != 0) {
  403. raw_spin_unlock_irqrestore(&gpt->lock, flags);
  404. return -EBUSY;
  405. }
  406. clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_COUNTER_ENABLE);
  407. raw_spin_unlock_irqrestore(&gpt->lock, flags);
  408. return 0;
  409. }
  410. EXPORT_SYMBOL(mpc52xx_gpt_stop_timer);
  411. /**
  412. * mpc52xx_gpt_timer_period - Read the timer period
  413. * @gpt: Pointer to gpt private data structure
  414. *
  415. * Returns the timer period in ns
  416. */
  417. u64 mpc52xx_gpt_timer_period(struct mpc52xx_gpt_priv *gpt)
  418. {
  419. u64 period;
  420. u64 prescale;
  421. unsigned long flags;
  422. raw_spin_lock_irqsave(&gpt->lock, flags);
  423. period = in_be32(&gpt->regs->count);
  424. raw_spin_unlock_irqrestore(&gpt->lock, flags);
  425. prescale = period >> 16;
  426. period &= 0xffff;
  427. if (prescale == 0)
  428. prescale = 0x10000;
  429. period = period * prescale * 1000000000ULL;
  430. do_div(period, (u64)gpt->ipb_freq);
  431. return period;
  432. }
  433. EXPORT_SYMBOL(mpc52xx_gpt_timer_period);
  434. #if defined(CONFIG_MPC5200_WDT)
  435. /***********************************************************************
  436. * Watchdog API for gpt0
  437. */
  438. #define WDT_IDENTITY "mpc52xx watchdog on GPT0"
  439. /* wdt_is_active stores whether or not the /dev/watchdog device is opened */
  440. static unsigned long wdt_is_active;
  441. /* wdt-capable gpt */
  442. static struct mpc52xx_gpt_priv *mpc52xx_gpt_wdt;
  443. /* low-level wdt functions */
  444. static inline void mpc52xx_gpt_wdt_ping(struct mpc52xx_gpt_priv *gpt_wdt)
  445. {
  446. unsigned long flags;
  447. raw_spin_lock_irqsave(&gpt_wdt->lock, flags);
  448. out_8((u8 *) &gpt_wdt->regs->mode, MPC52xx_GPT_MODE_WDT_PING);
  449. raw_spin_unlock_irqrestore(&gpt_wdt->lock, flags);
  450. }
  451. /* wdt misc device api */
  452. static ssize_t mpc52xx_wdt_write(struct file *file, const char __user *data,
  453. size_t len, loff_t *ppos)
  454. {
  455. struct mpc52xx_gpt_priv *gpt_wdt = file->private_data;
  456. mpc52xx_gpt_wdt_ping(gpt_wdt);
  457. return 0;
  458. }
  459. static const struct watchdog_info mpc5200_wdt_info = {
  460. .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
  461. .identity = WDT_IDENTITY,
  462. };
  463. static long mpc52xx_wdt_ioctl(struct file *file, unsigned int cmd,
  464. unsigned long arg)
  465. {
  466. struct mpc52xx_gpt_priv *gpt_wdt = file->private_data;
  467. int __user *data = (int __user *)arg;
  468. int timeout;
  469. u64 real_timeout;
  470. int ret = 0;
  471. switch (cmd) {
  472. case WDIOC_GETSUPPORT:
  473. ret = copy_to_user(data, &mpc5200_wdt_info,
  474. sizeof(mpc5200_wdt_info));
  475. if (ret)
  476. ret = -EFAULT;
  477. break;
  478. case WDIOC_GETSTATUS:
  479. case WDIOC_GETBOOTSTATUS:
  480. ret = put_user(0, data);
  481. break;
  482. case WDIOC_KEEPALIVE:
  483. mpc52xx_gpt_wdt_ping(gpt_wdt);
  484. break;
  485. case WDIOC_SETTIMEOUT:
  486. ret = get_user(timeout, data);
  487. if (ret)
  488. break;
  489. real_timeout = (u64) timeout * 1000000000ULL;
  490. ret = mpc52xx_gpt_do_start(gpt_wdt, real_timeout, 0, 1);
  491. if (ret)
  492. break;
  493. /* fall through and return the timeout */
  494. case WDIOC_GETTIMEOUT:
  495. /* we need to round here as to avoid e.g. the following
  496. * situation:
  497. * - timeout requested is 1 second;
  498. * - real timeout @33MHz is 999997090ns
  499. * - the int divide by 10^9 will return 0.
  500. */
  501. real_timeout =
  502. mpc52xx_gpt_timer_period(gpt_wdt) + 500000000ULL;
  503. do_div(real_timeout, 1000000000ULL);
  504. timeout = (int) real_timeout;
  505. ret = put_user(timeout, data);
  506. break;
  507. default:
  508. ret = -ENOTTY;
  509. }
  510. return ret;
  511. }
  512. static int mpc52xx_wdt_open(struct inode *inode, struct file *file)
  513. {
  514. int ret;
  515. /* sanity check */
  516. if (!mpc52xx_gpt_wdt)
  517. return -ENODEV;
  518. /* /dev/watchdog can only be opened once */
  519. if (test_and_set_bit(0, &wdt_is_active))
  520. return -EBUSY;
  521. /* Set and activate the watchdog with 30 seconds timeout */
  522. ret = mpc52xx_gpt_do_start(mpc52xx_gpt_wdt, 30ULL * 1000000000ULL,
  523. 0, 1);
  524. if (ret) {
  525. clear_bit(0, &wdt_is_active);
  526. return ret;
  527. }
  528. file->private_data = mpc52xx_gpt_wdt;
  529. return stream_open(inode, file);
  530. }
  531. static int mpc52xx_wdt_release(struct inode *inode, struct file *file)
  532. {
  533. /* note: releasing the wdt in NOWAYOUT-mode does not stop it */
  534. #if !defined(CONFIG_WATCHDOG_NOWAYOUT)
  535. struct mpc52xx_gpt_priv *gpt_wdt = file->private_data;
  536. unsigned long flags;
  537. raw_spin_lock_irqsave(&gpt_wdt->lock, flags);
  538. clrbits32(&gpt_wdt->regs->mode,
  539. MPC52xx_GPT_MODE_COUNTER_ENABLE | MPC52xx_GPT_MODE_WDT_EN);
  540. gpt_wdt->wdt_mode &= ~MPC52xx_GPT_IS_WDT;
  541. raw_spin_unlock_irqrestore(&gpt_wdt->lock, flags);
  542. #endif
  543. clear_bit(0, &wdt_is_active);
  544. return 0;
  545. }
  546. static const struct file_operations mpc52xx_wdt_fops = {
  547. .owner = THIS_MODULE,
  548. .llseek = no_llseek,
  549. .write = mpc52xx_wdt_write,
  550. .unlocked_ioctl = mpc52xx_wdt_ioctl,
  551. .compat_ioctl = compat_ptr_ioctl,
  552. .open = mpc52xx_wdt_open,
  553. .release = mpc52xx_wdt_release,
  554. };
  555. static struct miscdevice mpc52xx_wdt_miscdev = {
  556. .minor = WATCHDOG_MINOR,
  557. .name = "watchdog",
  558. .fops = &mpc52xx_wdt_fops,
  559. };
  560. static int mpc52xx_gpt_wdt_init(void)
  561. {
  562. int err;
  563. /* try to register the watchdog misc device */
  564. err = misc_register(&mpc52xx_wdt_miscdev);
  565. if (err)
  566. pr_err("%s: cannot register watchdog device\n", WDT_IDENTITY);
  567. else
  568. pr_info("%s: watchdog device registered\n", WDT_IDENTITY);
  569. return err;
  570. }
  571. static int mpc52xx_gpt_wdt_setup(struct mpc52xx_gpt_priv *gpt,
  572. const u32 *period)
  573. {
  574. u64 real_timeout;
  575. /* remember the gpt for the wdt operation */
  576. mpc52xx_gpt_wdt = gpt;
  577. /* configure the wdt if the device tree contained a timeout */
  578. if (!period || *period == 0)
  579. return 0;
  580. real_timeout = (u64) *period * 1000000000ULL;
  581. if (mpc52xx_gpt_do_start(gpt, real_timeout, 0, 1))
  582. dev_warn(gpt->dev, "starting as wdt failed\n");
  583. else
  584. dev_info(gpt->dev, "watchdog set to %us timeout\n", *period);
  585. return 0;
  586. }
  587. #else
  588. static int mpc52xx_gpt_wdt_init(void)
  589. {
  590. return 0;
  591. }
  592. static inline int mpc52xx_gpt_wdt_setup(struct mpc52xx_gpt_priv *gpt,
  593. const u32 *period)
  594. {
  595. return 0;
  596. }
  597. #endif /* CONFIG_MPC5200_WDT */
  598. /* ---------------------------------------------------------------------
  599. * of_platform bus binding code
  600. */
  601. static int mpc52xx_gpt_probe(struct platform_device *ofdev)
  602. {
  603. struct mpc52xx_gpt_priv *gpt;
  604. gpt = devm_kzalloc(&ofdev->dev, sizeof *gpt, GFP_KERNEL);
  605. if (!gpt)
  606. return -ENOMEM;
  607. raw_spin_lock_init(&gpt->lock);
  608. gpt->dev = &ofdev->dev;
  609. gpt->ipb_freq = mpc5xxx_get_bus_frequency(ofdev->dev.of_node);
  610. gpt->regs = of_iomap(ofdev->dev.of_node, 0);
  611. if (!gpt->regs)
  612. return -ENOMEM;
  613. dev_set_drvdata(&ofdev->dev, gpt);
  614. mpc52xx_gpt_gpio_setup(gpt, ofdev->dev.of_node);
  615. mpc52xx_gpt_irq_setup(gpt, ofdev->dev.of_node);
  616. mutex_lock(&mpc52xx_gpt_list_mutex);
  617. list_add(&gpt->list, &mpc52xx_gpt_list);
  618. mutex_unlock(&mpc52xx_gpt_list_mutex);
  619. /* check if this device could be a watchdog */
  620. if (of_get_property(ofdev->dev.of_node, "fsl,has-wdt", NULL) ||
  621. of_get_property(ofdev->dev.of_node, "has-wdt", NULL)) {
  622. const u32 *on_boot_wdt;
  623. gpt->wdt_mode = MPC52xx_GPT_CAN_WDT;
  624. on_boot_wdt = of_get_property(ofdev->dev.of_node,
  625. "fsl,wdt-on-boot", NULL);
  626. if (on_boot_wdt) {
  627. dev_info(gpt->dev, "used as watchdog\n");
  628. gpt->wdt_mode |= MPC52xx_GPT_IS_WDT;
  629. } else
  630. dev_info(gpt->dev, "can function as watchdog\n");
  631. mpc52xx_gpt_wdt_setup(gpt, on_boot_wdt);
  632. }
  633. return 0;
  634. }
  635. static int mpc52xx_gpt_remove(struct platform_device *ofdev)
  636. {
  637. return -EBUSY;
  638. }
  639. static const struct of_device_id mpc52xx_gpt_match[] = {
  640. { .compatible = "fsl,mpc5200-gpt", },
  641. /* Depreciated compatible values; don't use for new dts files */
  642. { .compatible = "fsl,mpc5200-gpt-gpio", },
  643. { .compatible = "mpc5200-gpt", },
  644. {}
  645. };
  646. static struct platform_driver mpc52xx_gpt_driver = {
  647. .driver = {
  648. .name = "mpc52xx-gpt",
  649. .of_match_table = mpc52xx_gpt_match,
  650. },
  651. .probe = mpc52xx_gpt_probe,
  652. .remove = mpc52xx_gpt_remove,
  653. };
  654. static int __init mpc52xx_gpt_init(void)
  655. {
  656. return platform_driver_register(&mpc52xx_gpt_driver);
  657. }
  658. /* Make sure GPIOs and IRQs get set up before anyone tries to use them */
  659. subsys_initcall(mpc52xx_gpt_init);
  660. device_initcall(mpc52xx_gpt_wdt_init);