/arch/powerpc/platforms/52xx/media5200.c

http://github.com/mirrors/linux · C · 252 lines · 167 code · 44 blank · 41 comment · 10 complexity · 17fea9553f446a14b3b504034bd11c7d MD5 · raw file

  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Support for 'media5200-platform' compatible boards.
  4. *
  5. * Copyright (C) 2008 Secret Lab Technologies Ltd.
  6. *
  7. * Description:
  8. * This code implements support for the Freescape Media5200 platform
  9. * (built around the MPC5200 SoC).
  10. *
  11. * Notable characteristic of the Media5200 is the presence of an FPGA
  12. * that has all external IRQ lines routed through it. This file implements
  13. * a cascaded interrupt controller driver which attaches itself to the
  14. * Virtual IRQ subsystem after the primary mpc5200 interrupt controller
  15. * is initialized.
  16. */
  17. #undef DEBUG
  18. #include <linux/irq.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/io.h>
  21. #include <asm/time.h>
  22. #include <asm/prom.h>
  23. #include <asm/machdep.h>
  24. #include <asm/mpc52xx.h>
  25. static const struct of_device_id mpc5200_gpio_ids[] __initconst = {
  26. { .compatible = "fsl,mpc5200-gpio", },
  27. { .compatible = "mpc5200-gpio", },
  28. {}
  29. };
  30. /* FPGA register set */
  31. #define MEDIA5200_IRQ_ENABLE (0x40c)
  32. #define MEDIA5200_IRQ_STATUS (0x410)
  33. #define MEDIA5200_NUM_IRQS (6)
  34. #define MEDIA5200_IRQ_SHIFT (32 - MEDIA5200_NUM_IRQS)
  35. struct media5200_irq {
  36. void __iomem *regs;
  37. spinlock_t lock;
  38. struct irq_domain *irqhost;
  39. };
  40. struct media5200_irq media5200_irq;
  41. static void media5200_irq_unmask(struct irq_data *d)
  42. {
  43. unsigned long flags;
  44. u32 val;
  45. spin_lock_irqsave(&media5200_irq.lock, flags);
  46. val = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE);
  47. val |= 1 << (MEDIA5200_IRQ_SHIFT + irqd_to_hwirq(d));
  48. out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, val);
  49. spin_unlock_irqrestore(&media5200_irq.lock, flags);
  50. }
  51. static void media5200_irq_mask(struct irq_data *d)
  52. {
  53. unsigned long flags;
  54. u32 val;
  55. spin_lock_irqsave(&media5200_irq.lock, flags);
  56. val = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE);
  57. val &= ~(1 << (MEDIA5200_IRQ_SHIFT + irqd_to_hwirq(d)));
  58. out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, val);
  59. spin_unlock_irqrestore(&media5200_irq.lock, flags);
  60. }
  61. static struct irq_chip media5200_irq_chip = {
  62. .name = "Media5200 FPGA",
  63. .irq_unmask = media5200_irq_unmask,
  64. .irq_mask = media5200_irq_mask,
  65. .irq_mask_ack = media5200_irq_mask,
  66. };
  67. static void media5200_irq_cascade(struct irq_desc *desc)
  68. {
  69. struct irq_chip *chip = irq_desc_get_chip(desc);
  70. int sub_virq, val;
  71. u32 status, enable;
  72. /* Mask off the cascaded IRQ */
  73. raw_spin_lock(&desc->lock);
  74. chip->irq_mask(&desc->irq_data);
  75. raw_spin_unlock(&desc->lock);
  76. /* Ask the FPGA for IRQ status. If 'val' is 0, then no irqs
  77. * are pending. 'ffs()' is 1 based */
  78. status = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE);
  79. enable = in_be32(media5200_irq.regs + MEDIA5200_IRQ_STATUS);
  80. val = ffs((status & enable) >> MEDIA5200_IRQ_SHIFT);
  81. if (val) {
  82. sub_virq = irq_linear_revmap(media5200_irq.irqhost, val - 1);
  83. /* pr_debug("%s: virq=%i s=%.8x e=%.8x hwirq=%i subvirq=%i\n",
  84. * __func__, virq, status, enable, val - 1, sub_virq);
  85. */
  86. generic_handle_irq(sub_virq);
  87. }
  88. /* Processing done; can reenable the cascade now */
  89. raw_spin_lock(&desc->lock);
  90. chip->irq_ack(&desc->irq_data);
  91. if (!irqd_irq_disabled(&desc->irq_data))
  92. chip->irq_unmask(&desc->irq_data);
  93. raw_spin_unlock(&desc->lock);
  94. }
  95. static int media5200_irq_map(struct irq_domain *h, unsigned int virq,
  96. irq_hw_number_t hw)
  97. {
  98. pr_debug("%s: h=%p, virq=%i, hwirq=%i\n", __func__, h, virq, (int)hw);
  99. irq_set_chip_data(virq, &media5200_irq);
  100. irq_set_chip_and_handler(virq, &media5200_irq_chip, handle_level_irq);
  101. irq_set_status_flags(virq, IRQ_LEVEL);
  102. return 0;
  103. }
  104. static int media5200_irq_xlate(struct irq_domain *h, struct device_node *ct,
  105. const u32 *intspec, unsigned int intsize,
  106. irq_hw_number_t *out_hwirq,
  107. unsigned int *out_flags)
  108. {
  109. if (intsize != 2)
  110. return -1;
  111. pr_debug("%s: bank=%i, number=%i\n", __func__, intspec[0], intspec[1]);
  112. *out_hwirq = intspec[1];
  113. *out_flags = IRQ_TYPE_NONE;
  114. return 0;
  115. }
  116. static const struct irq_domain_ops media5200_irq_ops = {
  117. .map = media5200_irq_map,
  118. .xlate = media5200_irq_xlate,
  119. };
  120. /*
  121. * Setup Media5200 IRQ mapping
  122. */
  123. static void __init media5200_init_irq(void)
  124. {
  125. struct device_node *fpga_np;
  126. int cascade_virq;
  127. /* First setup the regular MPC5200 interrupt controller */
  128. mpc52xx_init_irq();
  129. /* Now find the FPGA IRQ */
  130. fpga_np = of_find_compatible_node(NULL, NULL, "fsl,media5200-fpga");
  131. if (!fpga_np)
  132. goto out;
  133. pr_debug("%s: found fpga node: %pOF\n", __func__, fpga_np);
  134. media5200_irq.regs = of_iomap(fpga_np, 0);
  135. if (!media5200_irq.regs)
  136. goto out;
  137. pr_debug("%s: mapped to %p\n", __func__, media5200_irq.regs);
  138. cascade_virq = irq_of_parse_and_map(fpga_np, 0);
  139. if (!cascade_virq)
  140. goto out;
  141. pr_debug("%s: cascaded on virq=%i\n", __func__, cascade_virq);
  142. /* Disable all FPGA IRQs */
  143. out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, 0);
  144. spin_lock_init(&media5200_irq.lock);
  145. media5200_irq.irqhost = irq_domain_add_linear(fpga_np,
  146. MEDIA5200_NUM_IRQS, &media5200_irq_ops, &media5200_irq);
  147. if (!media5200_irq.irqhost)
  148. goto out;
  149. pr_debug("%s: allocated irqhost\n", __func__);
  150. irq_set_handler_data(cascade_virq, &media5200_irq);
  151. irq_set_chained_handler(cascade_virq, media5200_irq_cascade);
  152. return;
  153. out:
  154. pr_err("Could not find Media5200 FPGA; PCI interrupts will not work\n");
  155. }
  156. /*
  157. * Setup the architecture
  158. */
  159. static void __init media5200_setup_arch(void)
  160. {
  161. struct device_node *np;
  162. struct mpc52xx_gpio __iomem *gpio;
  163. u32 port_config;
  164. if (ppc_md.progress)
  165. ppc_md.progress("media5200_setup_arch()", 0);
  166. /* Map important registers from the internal memory map */
  167. mpc52xx_map_common_devices();
  168. /* Some mpc5200 & mpc5200b related configuration */
  169. mpc5200_setup_xlb_arbiter();
  170. mpc52xx_setup_pci();
  171. np = of_find_matching_node(NULL, mpc5200_gpio_ids);
  172. gpio = of_iomap(np, 0);
  173. of_node_put(np);
  174. if (!gpio) {
  175. printk(KERN_ERR "%s() failed. expect abnormal behavior\n",
  176. __func__);
  177. return;
  178. }
  179. /* Set port config */
  180. port_config = in_be32(&gpio->port_config);
  181. port_config &= ~0x03000000; /* ATA CS is on csb_4/5 */
  182. port_config |= 0x01000000;
  183. out_be32(&gpio->port_config, port_config);
  184. /* Unmap zone */
  185. iounmap(gpio);
  186. }
  187. /* list of the supported boards */
  188. static const char * const board[] __initconst = {
  189. "fsl,media5200",
  190. NULL
  191. };
  192. /*
  193. * Called very early, MMU is off, device-tree isn't unflattened
  194. */
  195. static int __init media5200_probe(void)
  196. {
  197. return of_device_compatible_match(of_root, board);
  198. }
  199. define_machine(media5200_platform) {
  200. .name = "media5200-platform",
  201. .probe = media5200_probe,
  202. .setup_arch = media5200_setup_arch,
  203. .init = mpc52xx_declare_of_platform_devices,
  204. .init_IRQ = media5200_init_irq,
  205. .get_irq = mpc52xx_get_irq,
  206. .restart = mpc52xx_restart,
  207. .calibrate_decr = generic_calibrate_decr,
  208. };