/arch/powerpc/oprofile/op_model_7450.c

http://github.com/mirrors/linux · C · 207 lines · 125 code · 40 blank · 42 comment · 12 complexity · 759992517a2cf114eacb2d053d83e711 MD5 · raw file

  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * arch/powerpc/oprofile/op_model_7450.c
  4. *
  5. * Freescale 745x/744x oprofile support, based on fsl_booke support
  6. * Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM
  7. *
  8. * Copyright (c) 2004 Freescale Semiconductor, Inc
  9. *
  10. * Author: Andy Fleming
  11. * Maintainer: Kumar Gala <galak@kernel.crashing.org>
  12. */
  13. #include <linux/oprofile.h>
  14. #include <linux/smp.h>
  15. #include <asm/ptrace.h>
  16. #include <asm/processor.h>
  17. #include <asm/cputable.h>
  18. #include <asm/page.h>
  19. #include <asm/pmc.h>
  20. #include <asm/oprofile_impl.h>
  21. static unsigned long reset_value[OP_MAX_COUNTER];
  22. static int oprofile_running;
  23. static u32 mmcr0_val, mmcr1_val, mmcr2_val, num_pmcs;
  24. #define MMCR0_PMC1_SHIFT 6
  25. #define MMCR0_PMC2_SHIFT 0
  26. #define MMCR1_PMC3_SHIFT 27
  27. #define MMCR1_PMC4_SHIFT 22
  28. #define MMCR1_PMC5_SHIFT 17
  29. #define MMCR1_PMC6_SHIFT 11
  30. #define mmcr0_event1(event) \
  31. ((event << MMCR0_PMC1_SHIFT) & MMCR0_PMC1SEL)
  32. #define mmcr0_event2(event) \
  33. ((event << MMCR0_PMC2_SHIFT) & MMCR0_PMC2SEL)
  34. #define mmcr1_event3(event) \
  35. ((event << MMCR1_PMC3_SHIFT) & MMCR1_PMC3SEL)
  36. #define mmcr1_event4(event) \
  37. ((event << MMCR1_PMC4_SHIFT) & MMCR1_PMC4SEL)
  38. #define mmcr1_event5(event) \
  39. ((event << MMCR1_PMC5_SHIFT) & MMCR1_PMC5SEL)
  40. #define mmcr1_event6(event) \
  41. ((event << MMCR1_PMC6_SHIFT) & MMCR1_PMC6SEL)
  42. #define MMCR0_INIT (MMCR0_FC | MMCR0_FCS | MMCR0_FCP | MMCR0_FCM1 | MMCR0_FCM0)
  43. /* Unfreezes the counters on this CPU, enables the interrupt,
  44. * enables the counters to trigger the interrupt, and sets the
  45. * counters to only count when the mark bit is not set.
  46. */
  47. static void pmc_start_ctrs(void)
  48. {
  49. u32 mmcr0 = mfspr(SPRN_MMCR0);
  50. mmcr0 &= ~(MMCR0_FC | MMCR0_FCM0);
  51. mmcr0 |= (MMCR0_FCECE | MMCR0_PMC1CE | MMCR0_PMCnCE | MMCR0_PMXE);
  52. mtspr(SPRN_MMCR0, mmcr0);
  53. }
  54. /* Disables the counters on this CPU, and freezes them */
  55. static void pmc_stop_ctrs(void)
  56. {
  57. u32 mmcr0 = mfspr(SPRN_MMCR0);
  58. mmcr0 |= MMCR0_FC;
  59. mmcr0 &= ~(MMCR0_FCECE | MMCR0_PMC1CE | MMCR0_PMCnCE | MMCR0_PMXE);
  60. mtspr(SPRN_MMCR0, mmcr0);
  61. }
  62. /* Configures the counters on this CPU based on the global
  63. * settings */
  64. static int fsl7450_cpu_setup(struct op_counter_config *ctr)
  65. {
  66. /* freeze all counters */
  67. pmc_stop_ctrs();
  68. mtspr(SPRN_MMCR0, mmcr0_val);
  69. mtspr(SPRN_MMCR1, mmcr1_val);
  70. if (num_pmcs > 4)
  71. mtspr(SPRN_MMCR2, mmcr2_val);
  72. return 0;
  73. }
  74. /* Configures the global settings for the countes on all CPUs. */
  75. static int fsl7450_reg_setup(struct op_counter_config *ctr,
  76. struct op_system_config *sys,
  77. int num_ctrs)
  78. {
  79. int i;
  80. num_pmcs = num_ctrs;
  81. /* Our counters count up, and "count" refers to
  82. * how much before the next interrupt, and we interrupt
  83. * on overflow. So we calculate the starting value
  84. * which will give us "count" until overflow.
  85. * Then we set the events on the enabled counters */
  86. for (i = 0; i < num_ctrs; ++i)
  87. reset_value[i] = 0x80000000UL - ctr[i].count;
  88. /* Set events for Counters 1 & 2 */
  89. mmcr0_val = MMCR0_INIT | mmcr0_event1(ctr[0].event)
  90. | mmcr0_event2(ctr[1].event);
  91. /* Setup user/kernel bits */
  92. if (sys->enable_kernel)
  93. mmcr0_val &= ~(MMCR0_FCS);
  94. if (sys->enable_user)
  95. mmcr0_val &= ~(MMCR0_FCP);
  96. /* Set events for Counters 3-6 */
  97. mmcr1_val = mmcr1_event3(ctr[2].event)
  98. | mmcr1_event4(ctr[3].event);
  99. if (num_ctrs > 4)
  100. mmcr1_val |= mmcr1_event5(ctr[4].event)
  101. | mmcr1_event6(ctr[5].event);
  102. mmcr2_val = 0;
  103. return 0;
  104. }
  105. /* Sets the counters on this CPU to the chosen values, and starts them */
  106. static int fsl7450_start(struct op_counter_config *ctr)
  107. {
  108. int i;
  109. mtmsr(mfmsr() | MSR_PMM);
  110. for (i = 0; i < num_pmcs; ++i) {
  111. if (ctr[i].enabled)
  112. classic_ctr_write(i, reset_value[i]);
  113. else
  114. classic_ctr_write(i, 0);
  115. }
  116. /* Clear the freeze bit, and enable the interrupt.
  117. * The counters won't actually start until the rfi clears
  118. * the PMM bit */
  119. pmc_start_ctrs();
  120. oprofile_running = 1;
  121. return 0;
  122. }
  123. /* Stop the counters on this CPU */
  124. static void fsl7450_stop(void)
  125. {
  126. /* freeze counters */
  127. pmc_stop_ctrs();
  128. oprofile_running = 0;
  129. mb();
  130. }
  131. /* Handle the interrupt on this CPU, and log a sample for each
  132. * event that triggered the interrupt */
  133. static void fsl7450_handle_interrupt(struct pt_regs *regs,
  134. struct op_counter_config *ctr)
  135. {
  136. unsigned long pc;
  137. int is_kernel;
  138. int val;
  139. int i;
  140. /* set the PMM bit (see comment below) */
  141. mtmsr(mfmsr() | MSR_PMM);
  142. pc = mfspr(SPRN_SIAR);
  143. is_kernel = is_kernel_addr(pc);
  144. for (i = 0; i < num_pmcs; ++i) {
  145. val = classic_ctr_read(i);
  146. if (val < 0) {
  147. if (oprofile_running && ctr[i].enabled) {
  148. oprofile_add_ext_sample(pc, regs, i, is_kernel);
  149. classic_ctr_write(i, reset_value[i]);
  150. } else {
  151. classic_ctr_write(i, 0);
  152. }
  153. }
  154. }
  155. /* The freeze bit was set by the interrupt. */
  156. /* Clear the freeze bit, and reenable the interrupt.
  157. * The counters won't actually start until the rfi clears
  158. * the PM/M bit */
  159. pmc_start_ctrs();
  160. }
  161. struct op_powerpc_model op_model_7450= {
  162. .reg_setup = fsl7450_reg_setup,
  163. .cpu_setup = fsl7450_cpu_setup,
  164. .start = fsl7450_start,
  165. .stop = fsl7450_stop,
  166. .handle_interrupt = fsl7450_handle_interrupt,
  167. };