/arch/unicore32/kernel/head.S

http://github.com/mirrors/linux · Assembly · 249 lines · 135 code · 26 blank · 88 comment · 1 complexity · 774938cdec20be68e8e5276edb0aef76 MD5 · raw file

  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * linux/arch/unicore32/kernel/head.S
  4. *
  5. * Code specific to PKUnity SoC and UniCore ISA
  6. *
  7. * Copyright (C) 2001-2010 GUAN Xue-tao
  8. */
  9. #include <linux/linkage.h>
  10. #include <linux/init.h>
  11. #include <asm/assembler.h>
  12. #include <asm/ptrace.h>
  13. #include <generated/asm-offsets.h>
  14. #include <asm/memory.h>
  15. #include <asm/thread_info.h>
  16. #include <asm/hwdef-copro.h>
  17. #include <asm/pgtable-hwdef.h>
  18. #if (PHYS_OFFSET & 0x003fffff)
  19. #error "PHYS_OFFSET must be at an even 4MiB boundary!"
  20. #endif
  21. #define KERNEL_RAM_VADDR (PAGE_OFFSET + KERNEL_IMAGE_START)
  22. #define KERNEL_RAM_PADDR (PHYS_OFFSET + KERNEL_IMAGE_START)
  23. #define KERNEL_PGD_PADDR (KERNEL_RAM_PADDR - 0x1000)
  24. #define KERNEL_PGD_VADDR (KERNEL_RAM_VADDR - 0x1000)
  25. #define KERNEL_START KERNEL_RAM_VADDR
  26. #define KERNEL_END _end
  27. /*
  28. * swapper_pg_dir is the virtual address of the initial page table.
  29. * We place the page tables 4K below KERNEL_RAM_VADDR. Therefore, we must
  30. * make sure that KERNEL_RAM_VADDR is correctly set. Currently, we expect
  31. * the least significant 16 bits to be 0x8000, but we could probably
  32. * relax this restriction to KERNEL_RAM_VADDR >= PAGE_OFFSET + 0x1000.
  33. */
  34. #if (KERNEL_RAM_VADDR & 0xffff) != 0x8000
  35. #error KERNEL_RAM_VADDR must start at 0xXXXX8000
  36. #endif
  37. .globl swapper_pg_dir
  38. .equ swapper_pg_dir, KERNEL_RAM_VADDR - 0x1000
  39. /*
  40. * Kernel startup entry point.
  41. * ---------------------------
  42. *
  43. * This is normally called from the decompressor code. The requirements
  44. * are: MMU = off, D-cache = off, I-cache = dont care
  45. *
  46. * This code is mostly position independent, so if you link the kernel at
  47. * 0xc0008000, you call this at __pa(0xc0008000).
  48. */
  49. __HEAD
  50. ENTRY(stext)
  51. @ set asr
  52. mov r0, #PRIV_MODE @ ensure priv mode
  53. or r0, #PSR_R_BIT | PSR_I_BIT @ disable irqs
  54. mov.a asr, r0
  55. @ process identify
  56. movc r0, p0.c0, #0 @ cpuid
  57. movl r1, 0xff00ffff @ mask
  58. movl r2, 0x4d000863 @ value
  59. and r0, r1, r0
  60. cxor.a r0, r2
  61. bne __error_p @ invalid processor id
  62. /*
  63. * Clear the 4K level 1 swapper page table
  64. */
  65. movl r0, #KERNEL_PGD_PADDR @ page table address
  66. mov r1, #0
  67. add r2, r0, #0x1000
  68. 101: stw.w r1, [r0]+, #4
  69. stw.w r1, [r0]+, #4
  70. stw.w r1, [r0]+, #4
  71. stw.w r1, [r0]+, #4
  72. cxor.a r0, r2
  73. bne 101b
  74. movl r4, #KERNEL_PGD_PADDR @ page table address
  75. mov r7, #PMD_TYPE_SECT | PMD_PRESENT @ page size: section
  76. or r7, r7, #PMD_SECT_CACHEABLE @ cacheable
  77. or r7, r7, #PMD_SECT_READ | PMD_SECT_WRITE | PMD_SECT_EXEC
  78. /*
  79. * Create identity mapping for first 4MB of kernel to
  80. * cater for the MMU enable. This identity mapping
  81. * will be removed by paging_init(). We use our current program
  82. * counter to determine corresponding section base address.
  83. */
  84. mov r6, pc
  85. mov r6, r6 >> #22 @ start of kernel section
  86. or r1, r7, r6 << #22 @ flags + kernel base
  87. stw r1, [r4+], r6 << #2 @ identity mapping
  88. /*
  89. * Now setup the pagetables for our kernel direct
  90. * mapped region.
  91. */
  92. add r0, r4, #(KERNEL_START & 0xff000000) >> 20
  93. stw.w r1, [r0+], #(KERNEL_START & 0x00c00000) >> 20
  94. movl r6, #(KERNEL_END - 1)
  95. add r0, r0, #4
  96. add r6, r4, r6 >> #20
  97. 102: csub.a r0, r6
  98. add r1, r1, #1 << 22
  99. bua 103f
  100. stw.w r1, [r0]+, #4
  101. b 102b
  102. 103:
  103. /*
  104. * Then map first 4MB of ram in case it contains our boot params.
  105. */
  106. add r0, r4, #PAGE_OFFSET >> 20
  107. or r6, r7, #(PHYS_OFFSET & 0xffc00000)
  108. stw r6, [r0]
  109. ldw r15, __switch_data @ address to jump to after
  110. /*
  111. * Initialise TLB, Caches, and MMU state ready to switch the MMU
  112. * on.
  113. */
  114. mov r0, #0
  115. movc p0.c5, r0, #28 @ cache invalidate all
  116. nop8
  117. movc p0.c6, r0, #6 @ TLB invalidate all
  118. nop8
  119. /*
  120. * ..V. .... ..TB IDAM
  121. * ..1. .... ..01 1111
  122. */
  123. movl r0, #0x201f @ control register setting
  124. /*
  125. * Setup common bits before finally enabling the MMU. Essentially
  126. * this is just loading the page table pointer and domain access
  127. * registers.
  128. */
  129. #ifndef CONFIG_ALIGNMENT_TRAP
  130. andn r0, r0, #CR_A
  131. #endif
  132. #ifdef CONFIG_CPU_DCACHE_DISABLE
  133. andn r0, r0, #CR_D
  134. #endif
  135. #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
  136. andn r0, r0, #CR_B
  137. #endif
  138. #ifdef CONFIG_CPU_ICACHE_DISABLE
  139. andn r0, r0, #CR_I
  140. #endif
  141. movc p0.c2, r4, #0 @ set pgd
  142. b __turn_mmu_on
  143. ENDPROC(stext)
  144. /*
  145. * Enable the MMU. This completely changes the structure of the visible
  146. * memory space. You will not be able to trace execution through this.
  147. *
  148. * r0 = cp#0 control register
  149. * r15 = *virtual* address to jump to upon completion
  150. */
  151. .align 5
  152. __turn_mmu_on:
  153. mov r0, r0
  154. movc p0.c1, r0, #0 @ write control reg
  155. nop @ fetch inst by phys addr
  156. mov pc, r15
  157. nop8 @ fetch inst by phys addr
  158. ENDPROC(__turn_mmu_on)
  159. /*
  160. * Setup the initial page tables. We only setup the barest
  161. * amount which are required to get the kernel running, which
  162. * generally means mapping in the kernel code.
  163. *
  164. * r9 = cpuid
  165. * r10 = procinfo
  166. *
  167. * Returns:
  168. * r0, r3, r6, r7 corrupted
  169. * r4 = physical page table address
  170. */
  171. .ltorg
  172. .align 2
  173. .type __switch_data, %object
  174. __switch_data:
  175. .long __mmap_switched
  176. .long __bss_start @ r6
  177. .long _end @ r7
  178. .long cr_alignment @ r8
  179. .long init_thread_union + THREAD_START_SP @ sp
  180. /*
  181. * The following fragment of code is executed with the MMU on in MMU mode,
  182. * and uses absolute addresses; this is not position independent.
  183. *
  184. * r0 = cp#0 control register
  185. */
  186. __mmap_switched:
  187. adr r3, __switch_data + 4
  188. ldm.w (r6, r7, r8), [r3]+
  189. ldw sp, [r3]
  190. mov fp, #0 @ Clear BSS (and zero fp)
  191. 203: csub.a r6, r7
  192. bea 204f
  193. stw.w fp, [r6]+,#4
  194. b 203b
  195. 204:
  196. andn r1, r0, #CR_A @ Clear 'A' bit
  197. stm (r0, r1), [r8]+ @ Save control register values
  198. b start_kernel
  199. ENDPROC(__mmap_switched)
  200. /*
  201. * Exception handling. Something went wrong and we can't proceed. We
  202. * ought to tell the user, but since we don't have any guarantee that
  203. * we're even running on the right architecture, we do virtually nothing.
  204. *
  205. * If CONFIG_DEBUG_LL is set we try to print out something about the error
  206. * and hope for the best (useful if bootloader fails to pass a proper
  207. * machine ID for example).
  208. */
  209. __error_p:
  210. #ifdef CONFIG_DEBUG_LL
  211. adr r0, str_p1
  212. b.l printascii
  213. mov r0, r9
  214. b.l printhex8
  215. adr r0, str_p2
  216. b.l printascii
  217. 901: nop8
  218. b 901b
  219. str_p1: .asciz "\nError: unrecognized processor variant (0x"
  220. str_p2: .asciz ").\n"
  221. .align
  222. #endif
  223. ENDPROC(__error_p)