/arch/unicore32/mm/cache-ucv2.S

http://github.com/mirrors/linux · Assembly · 209 lines · 121 code · 30 blank · 58 comment · 0 complexity · 46a7d455a88bcf4105cd96dc02a88f76 MD5 · raw file

  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * linux/arch/unicore32/mm/cache-ucv2.S
  4. *
  5. * Code specific to PKUnity SoC and UniCore ISA
  6. *
  7. * Copyright (C) 2001-2010 GUAN Xue-tao
  8. *
  9. * This is the "shell" of the UniCore-v2 processor support.
  10. */
  11. #include <linux/linkage.h>
  12. #include <linux/init.h>
  13. #include <asm/assembler.h>
  14. #include <asm/page.h>
  15. #include "proc-macros.S"
  16. /*
  17. * __cpuc_flush_icache_all()
  18. * __cpuc_flush_kern_all()
  19. * __cpuc_flush_user_all()
  20. *
  21. * Flush the entire cache.
  22. */
  23. ENTRY(__cpuc_flush_icache_all)
  24. /*FALLTHROUGH*/
  25. ENTRY(__cpuc_flush_kern_all)
  26. /*FALLTHROUGH*/
  27. ENTRY(__cpuc_flush_user_all)
  28. mov r0, #0
  29. movc p0.c5, r0, #14 @ Dcache flush all
  30. nop8
  31. mov r0, #0
  32. movc p0.c5, r0, #20 @ Icache invalidate all
  33. nop8
  34. mov pc, lr
  35. /*
  36. * __cpuc_flush_user_range(start, end, flags)
  37. *
  38. * Flush a range of TLB entries in the specified address space.
  39. *
  40. * - start - start address (may not be aligned)
  41. * - end - end address (exclusive, may not be aligned)
  42. * - flags - vm_area_struct flags describing address space
  43. */
  44. ENTRY(__cpuc_flush_user_range)
  45. cxor.a r2, #0
  46. beq __cpuc_dma_flush_range
  47. #ifndef CONFIG_CPU_DCACHE_LINE_DISABLE
  48. andn r0, r0, #CACHE_LINESIZE - 1 @ Safety check
  49. sub r1, r1, r0
  50. csub.a r1, #MAX_AREA_SIZE
  51. bsg 2f
  52. andn r1, r1, #CACHE_LINESIZE - 1
  53. add r1, r1, #CACHE_LINESIZE
  54. 101: dcacheline_flush r0, r11, r12
  55. add r0, r0, #CACHE_LINESIZE
  56. sub.a r1, r1, #CACHE_LINESIZE
  57. bns 101b
  58. b 3f
  59. #endif
  60. 2: mov ip, #0
  61. movc p0.c5, ip, #14 @ Dcache flush all
  62. nop8
  63. 3: mov ip, #0
  64. movc p0.c5, ip, #20 @ Icache invalidate all
  65. nop8
  66. mov pc, lr
  67. /*
  68. * __cpuc_coherent_kern_range(start,end)
  69. * __cpuc_coherent_user_range(start,end)
  70. *
  71. * Ensure that the I and D caches are coherent within specified
  72. * region. This is typically used when code has been written to
  73. * a memory region, and will be executed.
  74. *
  75. * - start - virtual start address of region
  76. * - end - virtual end address of region
  77. */
  78. ENTRY(__cpuc_coherent_kern_range)
  79. /* FALLTHROUGH */
  80. ENTRY(__cpuc_coherent_user_range)
  81. #ifndef CONFIG_CPU_DCACHE_LINE_DISABLE
  82. andn r0, r0, #CACHE_LINESIZE - 1 @ Safety check
  83. sub r1, r1, r0
  84. csub.a r1, #MAX_AREA_SIZE
  85. bsg 2f
  86. andn r1, r1, #CACHE_LINESIZE - 1
  87. add r1, r1, #CACHE_LINESIZE
  88. @ r0 va2pa r10
  89. mov r9, #PAGE_SZ
  90. sub r9, r9, #1 @ PAGE_MASK
  91. 101: va2pa r0, r10, r11, r12, r13, 2f @ r10 is PA
  92. b 103f
  93. 102: cand.a r0, r9
  94. beq 101b
  95. 103: movc p0.c5, r10, #11 @ Dcache clean line of R10
  96. nop8
  97. add r0, r0, #CACHE_LINESIZE
  98. add r10, r10, #CACHE_LINESIZE
  99. sub.a r1, r1, #CACHE_LINESIZE
  100. bns 102b
  101. b 3f
  102. #endif
  103. 2: mov ip, #0
  104. movc p0.c5, ip, #10 @ Dcache clean all
  105. nop8
  106. 3: mov ip, #0
  107. movc p0.c5, ip, #20 @ Icache invalidate all
  108. nop8
  109. mov pc, lr
  110. /*
  111. * __cpuc_flush_kern_dcache_area(void *addr, size_t size)
  112. *
  113. * - addr - kernel address
  114. * - size - region size
  115. */
  116. ENTRY(__cpuc_flush_kern_dcache_area)
  117. mov ip, #0
  118. movc p0.c5, ip, #14 @ Dcache flush all
  119. nop8
  120. mov pc, lr
  121. /*
  122. * __cpuc_dma_clean_range(start,end)
  123. * - start - virtual start address of region
  124. * - end - virtual end address of region
  125. */
  126. ENTRY(__cpuc_dma_clean_range)
  127. #ifndef CONFIG_CPU_DCACHE_LINE_DISABLE
  128. andn r0, r0, #CACHE_LINESIZE - 1
  129. sub r1, r1, r0
  130. andn r1, r1, #CACHE_LINESIZE - 1
  131. add r1, r1, #CACHE_LINESIZE
  132. csub.a r1, #MAX_AREA_SIZE
  133. bsg 2f
  134. @ r0 va2pa r10
  135. mov r9, #PAGE_SZ
  136. sub r9, r9, #1 @ PAGE_MASK
  137. 101: va2pa r0, r10, r11, r12, r13, 2f @ r10 is PA
  138. b 1f
  139. 102: cand.a r0, r9
  140. beq 101b
  141. 1: movc p0.c5, r10, #11 @ Dcache clean line of R10
  142. nop8
  143. add r0, r0, #CACHE_LINESIZE
  144. add r10, r10, #CACHE_LINESIZE
  145. sub.a r1, r1, #CACHE_LINESIZE
  146. bns 102b
  147. mov pc, lr
  148. #endif
  149. 2: mov ip, #0
  150. movc p0.c5, ip, #10 @ Dcache clean all
  151. nop8
  152. mov pc, lr
  153. /*
  154. * __cpuc_dma_inv_range(start,end)
  155. * __cpuc_dma_flush_range(start,end)
  156. * - start - virtual start address of region
  157. * - end - virtual end address of region
  158. */
  159. __cpuc_dma_inv_range:
  160. /* FALLTHROUGH */
  161. ENTRY(__cpuc_dma_flush_range)
  162. #ifndef CONFIG_CPU_DCACHE_LINE_DISABLE
  163. andn r0, r0, #CACHE_LINESIZE - 1
  164. sub r1, r1, r0
  165. andn r1, r1, #CACHE_LINESIZE - 1
  166. add r1, r1, #CACHE_LINESIZE
  167. csub.a r1, #MAX_AREA_SIZE
  168. bsg 2f
  169. @ r0 va2pa r10
  170. 101: dcacheline_flush r0, r11, r12
  171. add r0, r0, #CACHE_LINESIZE
  172. sub.a r1, r1, #CACHE_LINESIZE
  173. bns 101b
  174. mov pc, lr
  175. #endif
  176. 2: mov ip, #0
  177. movc p0.c5, ip, #14 @ Dcache flush all
  178. nop8
  179. mov pc, lr