/arch/unicore32/include/mach/regs-ost.h

http://github.com/mirrors/linux · C Header · 91 lines · 21 code · 6 blank · 64 comment · 0 complexity · 626b6408b8779808b17c39b79d125c90 MD5 · raw file 

    

  1. /* SPDX-License-Identifier: GPL-2.0 */
    2. 

  2. /*
    3. 

  3.  * PKUnity Operating System Timer (OST) Registers
    4. 

  4.  */
    5. 

  5. /*
    6. 

  6.  * Match Reg 0 OST_OSMR0
    7. 

  7.  */
    8. 

  8. #define OST_OSMR0	(PKUNITY_OST_BASE + 0x0000)
    9. 

  9. /*
    10. 

  10.  * Match Reg 1 OST_OSMR1
    11. 

  11.  */
    12. 

  12. #define OST_OSMR1	(PKUNITY_OST_BASE + 0x0004)
    13. 

  13. /*
    14. 

  14.  * Match Reg 2 OST_OSMR2
    15. 

  15.  */
    16. 

  16. #define OST_OSMR2	(PKUNITY_OST_BASE + 0x0008)
    17. 

  17. /*
    18. 

  18.  * Match Reg 3 OST_OSMR3
    19. 

  19.  */
    20. 

  20. #define OST_OSMR3	(PKUNITY_OST_BASE + 0x000C)
    21. 

  21. /*
    22. 

  22.  * Counter Reg OST_OSCR
    23. 

  23.  */
    24. 

  24. #define OST_OSCR	(PKUNITY_OST_BASE + 0x0010)
    25. 

  25. /*
    26. 

  26.  * Status Reg OST_OSSR
    27. 

  27.  */
    28. 

  28. #define OST_OSSR	(PKUNITY_OST_BASE + 0x0014)
    29. 

  29. /*
    30. 

  30.  * Watchdog Enable Reg OST_OWER
    31. 

  31.  */
    32. 

  32. #define OST_OWER	(PKUNITY_OST_BASE + 0x0018)
    33. 

  33. /*
    34. 

  34.  * Interrupt Enable Reg OST_OIER
    35. 

  35.  */
    36. 

  36. #define OST_OIER	(PKUNITY_OST_BASE + 0x001C)
    37. 

  37. 

  38. /*
    39. 

  39.  * PWM Registers: IO base address: PKUNITY_OST_BASE + 0x80
    40. 

  40.  *      PWCR: Pulse Width Control Reg
    41. 

  41.  *      DCCR: Duty Cycle Control Reg
    42. 

  42.  *      PCR: Period Control Reg
    43. 

  43.  */
    44. 

  44. #define OST_PWM_PWCR	(0x00)
    45. 

  45. #define OST_PWM_DCCR	(0x04)
    46. 

  46. #define OST_PWM_PCR 	(0x08)
    47. 

  47. 

  48. /*
    49. 

  49.  * Match detected 0 OST_OSSR_M0
    50. 

  50.  */
    51. 

  51. #define OST_OSSR_M0		FIELD(1, 1, 0)
    52. 

  52. /*
    53. 

  53.  * Match detected 1 OST_OSSR_M1
    54. 

  54.  */
    55. 

  55. #define OST_OSSR_M1		FIELD(1, 1, 1)
    56. 

  56. /*
    57. 

  57.  * Match detected 2 OST_OSSR_M2
    58. 

  58.  */
    59. 

  59. #define OST_OSSR_M2		FIELD(1, 1, 2)
    60. 

  60. /*
    61. 

  61.  * Match detected 3 OST_OSSR_M3
    62. 

  62.  */
    63. 

  63. #define OST_OSSR_M3		FIELD(1, 1, 3)
    64. 

  64. 

  65. /*
    66. 

  66.  * Interrupt enable 0 OST_OIER_E0
    67. 

  67.  */
    68. 

  68. #define OST_OIER_E0		FIELD(1, 1, 0)
    69. 

  69. /*
    70. 

  70.  * Interrupt enable 1 OST_OIER_E1
    71. 

  71.  */
    72. 

  72. #define OST_OIER_E1		FIELD(1, 1, 1)
    73. 

  73. /*
    74. 

  74.  * Interrupt enable 2 OST_OIER_E2
    75. 

  75.  */
    76. 

  76. #define OST_OIER_E2		FIELD(1, 1, 2)
    77. 

  77. /*
    78. 

  78.  * Interrupt enable 3 OST_OIER_E3
    79. 

  79.  */
    80. 

  80. #define OST_OIER_E3		FIELD(1, 1, 3)
    81. 

  81. 

  82. /*
    83. 

  83.  * Watchdog Match Enable OST_OWER_WME
    84. 

  84.  */
    85. 

  85. #define OST_OWER_WME		FIELD(1, 1, 0)
    86. 

  86. 

  87. /*
    88. 

  88.  * PWM Full Duty Cycle OST_PWMDCCR_FDCYCLE
    89. 

  89.  */
    90. 

  90. #define OST_PWMDCCR_FDCYCLE	FIELD(1, 1, 10)
    91.