/arch/xtensa/kernel/pci-dma.c

http://github.com/mirrors/linux · C · 99 lines · 70 code · 12 blank · 17 comment · 5 complexity · ed2f5dfdf7573e67b26ebe784a930b58 MD5 · raw file

  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * DMA coherent memory allocation.
  4. *
  5. * Copyright (C) 2002 - 2005 Tensilica Inc.
  6. * Copyright (C) 2015 Cadence Design Systems Inc.
  7. *
  8. * Based on version for i386.
  9. *
  10. * Chris Zankel <chris@zankel.net>
  11. * Joe Taylor <joe@tensilica.com, joetylr@yahoo.com>
  12. */
  13. #include <linux/dma-contiguous.h>
  14. #include <linux/dma-noncoherent.h>
  15. #include <linux/dma-direct.h>
  16. #include <linux/gfp.h>
  17. #include <linux/highmem.h>
  18. #include <linux/mm.h>
  19. #include <linux/types.h>
  20. #include <asm/cacheflush.h>
  21. #include <asm/io.h>
  22. #include <asm/platform.h>
  23. static void do_cache_op(phys_addr_t paddr, size_t size,
  24. void (*fn)(unsigned long, unsigned long))
  25. {
  26. unsigned long off = paddr & (PAGE_SIZE - 1);
  27. unsigned long pfn = PFN_DOWN(paddr);
  28. struct page *page = pfn_to_page(pfn);
  29. if (!PageHighMem(page))
  30. fn((unsigned long)phys_to_virt(paddr), size);
  31. else
  32. while (size > 0) {
  33. size_t sz = min_t(size_t, size, PAGE_SIZE - off);
  34. void *vaddr = kmap_atomic(page);
  35. fn((unsigned long)vaddr + off, sz);
  36. kunmap_atomic(vaddr);
  37. off = 0;
  38. ++page;
  39. size -= sz;
  40. }
  41. }
  42. void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
  43. enum dma_data_direction dir)
  44. {
  45. switch (dir) {
  46. case DMA_BIDIRECTIONAL:
  47. case DMA_FROM_DEVICE:
  48. do_cache_op(paddr, size, __invalidate_dcache_range);
  49. break;
  50. case DMA_NONE:
  51. BUG();
  52. break;
  53. default:
  54. break;
  55. }
  56. }
  57. void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
  58. enum dma_data_direction dir)
  59. {
  60. switch (dir) {
  61. case DMA_BIDIRECTIONAL:
  62. case DMA_TO_DEVICE:
  63. if (XCHAL_DCACHE_IS_WRITEBACK)
  64. do_cache_op(paddr, size, __flush_dcache_range);
  65. break;
  66. case DMA_NONE:
  67. BUG();
  68. break;
  69. default:
  70. break;
  71. }
  72. }
  73. void arch_dma_prep_coherent(struct page *page, size_t size)
  74. {
  75. __invalidate_dcache_range((unsigned long)page_address(page), size);
  76. }
  77. /*
  78. * Memory caching is platform-dependent in noMMU xtensa configurations.
  79. * This function should be implemented in platform code in order to enable
  80. * coherent DMA memory operations when CONFIG_MMU is not enabled.
  81. */
  82. #ifdef CONFIG_MMU
  83. void *arch_dma_set_uncached(void *p, size_t size)
  84. {
  85. return p + XCHAL_KSEG_BYPASS_VADDR - XCHAL_KSEG_CACHED_VADDR;
  86. }
  87. #endif /* CONFIG_MMU */