/arch/xtensa/kernel/pci-dma.c

http://github.com/mirrors/linux · C · 99 lines · 70 code · 12 blank · 17 comment · 5 complexity · ed2f5dfdf7573e67b26ebe784a930b58 MD5 · raw file 

    

  1. // SPDX-License-Identifier: GPL-2.0-or-later
    2. 

  2. /*
    3. 

  3.  * DMA coherent memory allocation.
    4. 

  4.  *
    5. 

  5.  * Copyright (C) 2002 - 2005 Tensilica Inc.
    6. 

  6.  * Copyright (C) 2015 Cadence Design Systems Inc.
    7. 

  7.  *
    8. 

  8.  * Based on version for i386.
    9. 

  9.  *
    10. 

  10.  * Chris Zankel <chris@zankel.net>
    11. 

  11.  * Joe Taylor <joe@tensilica.com, joetylr@yahoo.com>
    12. 

  12.  */
    13. 

  13. 

  14. #include <linux/dma-contiguous.h>
    15. 

  15. #include <linux/dma-noncoherent.h>
    16. 

  16. #include <linux/dma-direct.h>
    17. 

  17. #include <linux/gfp.h>
    18. 

  18. #include <linux/highmem.h>
    19. 

  19. #include <linux/mm.h>
    20. 

  20. #include <linux/types.h>
    21. 

  21. #include <asm/cacheflush.h>
    22. 

  22. #include <asm/io.h>
    23. 

  23. #include <asm/platform.h>
    24. 

  24. 

  25. static void do_cache_op(phys_addr_t paddr, size_t size,
    26. 

  26. 			void (*fn)(unsigned long, unsigned long))
    27. 

  27. {
    28. 

  28. 	unsigned long off = paddr & (PAGE_SIZE - 1);
    29. 

  29. 	unsigned long pfn = PFN_DOWN(paddr);
    30. 

  30. 	struct page *page = pfn_to_page(pfn);
    31. 

  31. 

  32. 	if (!PageHighMem(page))
    33. 

  33. 		fn((unsigned long)phys_to_virt(paddr), size);
    34. 

  34. 	else
    35. 

  35. 		while (size > 0) {
    36. 

  36. 			size_t sz = min_t(size_t, size, PAGE_SIZE - off);
    37. 

  37. 			void *vaddr = kmap_atomic(page);
    38. 

  38. 

  39. 			fn((unsigned long)vaddr + off, sz);
    40. 

  40. 			kunmap_atomic(vaddr);
    41. 

  41. 			off = 0;
    42. 

  42. 			++page;
    43. 

  43. 			size -= sz;
    44. 

  44. 		}
    45. 

  45. }
    46. 

  46. 

  47. void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
    48. 

  48. 		enum dma_data_direction dir)
    49. 

  49. {
    50. 

  50. 	switch (dir) {
    51. 

  51. 	case DMA_BIDIRECTIONAL:
    52. 

  52. 	case DMA_FROM_DEVICE:
    53. 

  53. 		do_cache_op(paddr, size, __invalidate_dcache_range);
    54. 

  54. 		break;
    55. 

  55. 

  56. 	case DMA_NONE:
    57. 

  57. 		BUG();
    58. 

  58. 		break;
    59. 

  59. 

  60. 	default:
    61. 

  61. 		break;
    62. 

  62. 	}
    63. 

  63. }
    64. 

  64. 

  65. void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
    66. 

  66. 		enum dma_data_direction dir)
    67. 

  67. {
    68. 

  68. 	switch (dir) {
    69. 

  69. 	case DMA_BIDIRECTIONAL:
    70. 

  70. 	case DMA_TO_DEVICE:
    71. 

  71. 		if (XCHAL_DCACHE_IS_WRITEBACK)
    72. 

  72. 			do_cache_op(paddr, size, __flush_dcache_range);
    73. 

  73. 		break;
    74. 

  74. 

  75. 	case DMA_NONE:
    76. 

  76. 		BUG();
    77. 

  77. 		break;
    78. 

  78. 

  79. 	default:
    80. 

  80. 		break;
    81. 

  81. 	}
    82. 

  82. }
    83. 

  83. 

  84. void arch_dma_prep_coherent(struct page *page, size_t size)
    85. 

  85. {
    86. 

  86. 	__invalidate_dcache_range((unsigned long)page_address(page), size);
    87. 

  87. }
    88. 

  88. 

  89. /*
    90. 

  90.  * Memory caching is platform-dependent in noMMU xtensa configurations.
    91. 

  91.  * This function should be implemented in platform code in order to enable
    92. 

  92.  * coherent DMA memory operations when CONFIG_MMU is not enabled.
    93. 

  93.  */
    94. 

  94. #ifdef CONFIG_MMU
    95. 

  95. void *arch_dma_set_uncached(void *p, size_t size)
    96. 

  96. {
    97. 

  97. 	return p + XCHAL_KSEG_BYPASS_VADDR - XCHAL_KSEG_CACHED_VADDR;
    98. 

  98. }
    99. 

  99. #endif /* CONFIG_MMU */
    100.