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/arch/xtensa/include/asm/elf.h

http://github.com/mirrors/linux
C Header | 180 lines | 99 code | 30 blank | 51 comment | 4 complexity | 63b4dadaaedaf48eb14dd531cadf4c45 MD5 | raw file
  1/*
  2 * include/asm-xtensa/elf.h
  3 *
  4 * ELF register definitions
  5 *
  6 * This file is subject to the terms and conditions of the GNU General Public
  7 * License.  See the file "COPYING" in the main directory of this archive
  8 * for more details.
  9 *
 10 * Copyright (C) 2001 - 2005 Tensilica Inc.
 11 */
 12
 13#ifndef _XTENSA_ELF_H
 14#define _XTENSA_ELF_H
 15
 16#include <asm/ptrace.h>
 17#include <asm/coprocessor.h>
 18#include <linux/elf-em.h>
 19
 20/* Xtensa processor ELF architecture-magic number */
 21
 22#define EM_XTENSA_OLD	0xABC7
 23
 24/* Xtensa relocations defined by the ABIs */
 25
 26#define R_XTENSA_NONE           0
 27#define R_XTENSA_32             1
 28#define R_XTENSA_RTLD           2
 29#define R_XTENSA_GLOB_DAT       3
 30#define R_XTENSA_JMP_SLOT       4
 31#define R_XTENSA_RELATIVE       5
 32#define R_XTENSA_PLT            6
 33#define R_XTENSA_OP0            8
 34#define R_XTENSA_OP1            9
 35#define R_XTENSA_OP2            10
 36#define R_XTENSA_ASM_EXPAND	11
 37#define R_XTENSA_ASM_SIMPLIFY	12
 38#define R_XTENSA_GNU_VTINHERIT	15
 39#define R_XTENSA_GNU_VTENTRY	16
 40#define R_XTENSA_DIFF8		17
 41#define R_XTENSA_DIFF16		18
 42#define R_XTENSA_DIFF32		19
 43#define R_XTENSA_SLOT0_OP	20
 44#define R_XTENSA_SLOT1_OP	21
 45#define R_XTENSA_SLOT2_OP	22
 46#define R_XTENSA_SLOT3_OP	23
 47#define R_XTENSA_SLOT4_OP	24
 48#define R_XTENSA_SLOT5_OP	25
 49#define R_XTENSA_SLOT6_OP	26
 50#define R_XTENSA_SLOT7_OP	27
 51#define R_XTENSA_SLOT8_OP	28
 52#define R_XTENSA_SLOT9_OP	29
 53#define R_XTENSA_SLOT10_OP	30
 54#define R_XTENSA_SLOT11_OP	31
 55#define R_XTENSA_SLOT12_OP	32
 56#define R_XTENSA_SLOT13_OP	33
 57#define R_XTENSA_SLOT14_OP	34
 58#define R_XTENSA_SLOT0_ALT	35
 59#define R_XTENSA_SLOT1_ALT	36
 60#define R_XTENSA_SLOT2_ALT	37
 61#define R_XTENSA_SLOT3_ALT	38
 62#define R_XTENSA_SLOT4_ALT	39
 63#define R_XTENSA_SLOT5_ALT	40
 64#define R_XTENSA_SLOT6_ALT	41
 65#define R_XTENSA_SLOT7_ALT	42
 66#define R_XTENSA_SLOT8_ALT	43
 67#define R_XTENSA_SLOT9_ALT	44
 68#define R_XTENSA_SLOT10_ALT	45
 69#define R_XTENSA_SLOT11_ALT	46
 70#define R_XTENSA_SLOT12_ALT	47
 71#define R_XTENSA_SLOT13_ALT	48
 72#define R_XTENSA_SLOT14_ALT	49
 73
 74/* ELF register definitions. This is needed for core dump support.  */
 75
 76typedef unsigned long elf_greg_t;
 77
 78typedef struct user_pt_regs xtensa_gregset_t;
 79
 80#define ELF_NGREG	(sizeof(xtensa_gregset_t) / sizeof(elf_greg_t))
 81
 82typedef elf_greg_t elf_gregset_t[ELF_NGREG];
 83
 84#define ELF_NFPREG	18
 85
 86typedef unsigned int elf_fpreg_t;
 87typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
 88
 89/*
 90 * This is used to ensure we don't load something for the wrong architecture.
 91 */
 92
 93#define elf_check_arch(x) ( ( (x)->e_machine == EM_XTENSA )  || \
 94			    ( (x)->e_machine == EM_XTENSA_OLD ) )
 95
 96/*
 97 * These are used to set parameters in the core dumps.
 98 */
 99
100#ifdef __XTENSA_EL__
101# define ELF_DATA	ELFDATA2LSB
102#elif defined(__XTENSA_EB__)
103# define ELF_DATA	ELFDATA2MSB
104#else
105# error processor byte order undefined!
106#endif
107
108#define ELF_CLASS	ELFCLASS32
109#define ELF_ARCH	EM_XTENSA
110
111#define ELF_EXEC_PAGESIZE	PAGE_SIZE
112#define CORE_DUMP_USE_REGSET
113
114/*
115 * This is the location that an ET_DYN program is loaded if exec'ed.  Typical
116 * use of this is to invoke "./ld.so someprog" to test out a new version of
117 * the loader.  We need to make sure that it is out of the way of the program
118 * that it will "exec", and that there is sufficient room for the brk.
119 */
120
121#define ELF_ET_DYN_BASE         (2 * TASK_SIZE / 3)
122
123/*
124 * This yields a mask that user programs can use to figure out what
125 * instruction set this CPU supports.  This could be done in user space,
126 * but it's not easy, and we've already done it here.
127 */
128
129#define ELF_HWCAP	(0)
130
131/*
132 * This yields a string that ld.so will use to load implementation
133 * specific libraries for optimization.  This is more specific in
134 * intent than poking at uname or /proc/cpuinfo.
135 * For the moment, we have only optimizations for the Intel generations,
136 * but that could change...
137 */
138
139#define ELF_PLATFORM  (NULL)
140
141/*
142 * The Xtensa processor ABI says that when the program starts, a2
143 * contains a pointer to a function which might be registered using
144 * `atexit'.  This provides a mean for the dynamic linker to call
145 * DT_FINI functions for shared libraries that have been loaded before
146 * the code runs.
147 *
148 * A value of 0 tells we have no such handler.
149 *
150 * We might as well make sure everything else is cleared too (except
151 * for the stack pointer in a1), just to make things more
152 * deterministic.  Also, clearing a0 terminates debugger backtraces.
153 */
154
155#define ELF_PLAT_INIT(_r, load_addr) \
156	do { _r->areg[0]=0; /*_r->areg[1]=0;*/ _r->areg[2]=0;  _r->areg[3]=0;  \
157	     _r->areg[4]=0;  _r->areg[5]=0;    _r->areg[6]=0;  _r->areg[7]=0;  \
158	     _r->areg[8]=0;  _r->areg[9]=0;    _r->areg[10]=0; _r->areg[11]=0; \
159	     _r->areg[12]=0; _r->areg[13]=0;   _r->areg[14]=0; _r->areg[15]=0; \
160	} while (0)
161
162typedef struct {
163	xtregs_opt_t	opt;
164	xtregs_user_t	user;
165#if XTENSA_HAVE_COPROCESSORS
166	xtregs_cp0_t	cp0;
167	xtregs_cp1_t	cp1;
168	xtregs_cp2_t	cp2;
169	xtregs_cp3_t	cp3;
170	xtregs_cp4_t	cp4;
171	xtregs_cp5_t	cp5;
172	xtregs_cp6_t	cp6;
173	xtregs_cp7_t	cp7;
174#endif
175} elf_xtregs_t;
176
177#define SET_PERSONALITY(ex) \
178	set_personality(PER_LINUX_32BIT | (current->personality & (~PER_MASK)))
179
180#endif	/* _XTENSA_ELF_H */