/drivers/mfd/twl4030-irq.c

http://github.com/mirrors/linux · C · 777 lines · 516 code · 112 blank · 149 comment · 46 complexity · 075f25dc2e47d54a33719b01d7a88492 MD5 · raw file

  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * twl4030-irq.c - TWL4030/TPS659x0 irq support
  4. *
  5. * Copyright (C) 2005-2006 Texas Instruments, Inc.
  6. *
  7. * Modifications to defer interrupt handling to a kernel thread:
  8. * Copyright (C) 2006 MontaVista Software, Inc.
  9. *
  10. * Based on tlv320aic23.c:
  11. * Copyright (c) by Kai Svahn <kai.svahn@nokia.com>
  12. *
  13. * Code cleanup and modifications to IRQ handler.
  14. * by syed khasim <x0khasim@ti.com>
  15. */
  16. #include <linux/export.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/irq.h>
  19. #include <linux/slab.h>
  20. #include <linux/of.h>
  21. #include <linux/irqdomain.h>
  22. #include <linux/mfd/twl.h>
  23. #include "twl-core.h"
  24. /*
  25. * TWL4030 IRQ handling has two stages in hardware, and thus in software.
  26. * The Primary Interrupt Handler (PIH) stage exposes status bits saying
  27. * which Secondary Interrupt Handler (SIH) stage is raising an interrupt.
  28. * SIH modules are more traditional IRQ components, which support per-IRQ
  29. * enable/disable and trigger controls; they do most of the work.
  30. *
  31. * These chips are designed to support IRQ handling from two different
  32. * I2C masters. Each has a dedicated IRQ line, and dedicated IRQ status
  33. * and mask registers in the PIH and SIH modules.
  34. *
  35. * We set up IRQs starting at a platform-specified base, always starting
  36. * with PIH and the SIH for PWR_INT and then usually adding GPIO:
  37. * base + 0 .. base + 7 PIH
  38. * base + 8 .. base + 15 SIH for PWR_INT
  39. * base + 16 .. base + 33 SIH for GPIO
  40. */
  41. #define TWL4030_CORE_NR_IRQS 8
  42. #define TWL4030_PWR_NR_IRQS 8
  43. /* PIH register offsets */
  44. #define REG_PIH_ISR_P1 0x01
  45. #define REG_PIH_ISR_P2 0x02
  46. #define REG_PIH_SIR 0x03 /* for testing */
  47. /* Linux could (eventually) use either IRQ line */
  48. static int irq_line;
  49. struct sih {
  50. char name[8];
  51. u8 module; /* module id */
  52. u8 control_offset; /* for SIH_CTRL */
  53. bool set_cor;
  54. u8 bits; /* valid in isr/imr */
  55. u8 bytes_ixr; /* bytelen of ISR/IMR/SIR */
  56. u8 edr_offset;
  57. u8 bytes_edr; /* bytelen of EDR */
  58. u8 irq_lines; /* number of supported irq lines */
  59. /* SIR ignored -- set interrupt, for testing only */
  60. struct sih_irq_data {
  61. u8 isr_offset;
  62. u8 imr_offset;
  63. } mask[2];
  64. /* + 2 bytes padding */
  65. };
  66. static const struct sih *sih_modules;
  67. static int nr_sih_modules;
  68. #define SIH_INITIALIZER(modname, nbits) \
  69. .module = TWL4030_MODULE_ ## modname, \
  70. .control_offset = TWL4030_ ## modname ## _SIH_CTRL, \
  71. .bits = nbits, \
  72. .bytes_ixr = DIV_ROUND_UP(nbits, 8), \
  73. .edr_offset = TWL4030_ ## modname ## _EDR, \
  74. .bytes_edr = DIV_ROUND_UP((2*(nbits)), 8), \
  75. .irq_lines = 2, \
  76. .mask = { { \
  77. .isr_offset = TWL4030_ ## modname ## _ISR1, \
  78. .imr_offset = TWL4030_ ## modname ## _IMR1, \
  79. }, \
  80. { \
  81. .isr_offset = TWL4030_ ## modname ## _ISR2, \
  82. .imr_offset = TWL4030_ ## modname ## _IMR2, \
  83. }, },
  84. /* register naming policies are inconsistent ... */
  85. #define TWL4030_INT_PWR_EDR TWL4030_INT_PWR_EDR1
  86. #define TWL4030_MODULE_KEYPAD_KEYP TWL4030_MODULE_KEYPAD
  87. #define TWL4030_MODULE_INT_PWR TWL4030_MODULE_INT
  88. /*
  89. * Order in this table matches order in PIH_ISR. That is,
  90. * BIT(n) in PIH_ISR is sih_modules[n].
  91. */
  92. /* sih_modules_twl4030 is used both in twl4030 and twl5030 */
  93. static const struct sih sih_modules_twl4030[6] = {
  94. [0] = {
  95. .name = "gpio",
  96. .module = TWL4030_MODULE_GPIO,
  97. .control_offset = REG_GPIO_SIH_CTRL,
  98. .set_cor = true,
  99. .bits = TWL4030_GPIO_MAX,
  100. .bytes_ixr = 3,
  101. /* Note: *all* of these IRQs default to no-trigger */
  102. .edr_offset = REG_GPIO_EDR1,
  103. .bytes_edr = 5,
  104. .irq_lines = 2,
  105. .mask = { {
  106. .isr_offset = REG_GPIO_ISR1A,
  107. .imr_offset = REG_GPIO_IMR1A,
  108. }, {
  109. .isr_offset = REG_GPIO_ISR1B,
  110. .imr_offset = REG_GPIO_IMR1B,
  111. }, },
  112. },
  113. [1] = {
  114. .name = "keypad",
  115. .set_cor = true,
  116. SIH_INITIALIZER(KEYPAD_KEYP, 4)
  117. },
  118. [2] = {
  119. .name = "bci",
  120. .module = TWL4030_MODULE_INTERRUPTS,
  121. .control_offset = TWL4030_INTERRUPTS_BCISIHCTRL,
  122. .set_cor = true,
  123. .bits = 12,
  124. .bytes_ixr = 2,
  125. .edr_offset = TWL4030_INTERRUPTS_BCIEDR1,
  126. /* Note: most of these IRQs default to no-trigger */
  127. .bytes_edr = 3,
  128. .irq_lines = 2,
  129. .mask = { {
  130. .isr_offset = TWL4030_INTERRUPTS_BCIISR1A,
  131. .imr_offset = TWL4030_INTERRUPTS_BCIIMR1A,
  132. }, {
  133. .isr_offset = TWL4030_INTERRUPTS_BCIISR1B,
  134. .imr_offset = TWL4030_INTERRUPTS_BCIIMR1B,
  135. }, },
  136. },
  137. [3] = {
  138. .name = "madc",
  139. SIH_INITIALIZER(MADC, 4)
  140. },
  141. [4] = {
  142. /* USB doesn't use the same SIH organization */
  143. .name = "usb",
  144. },
  145. [5] = {
  146. .name = "power",
  147. .set_cor = true,
  148. SIH_INITIALIZER(INT_PWR, 8)
  149. },
  150. /* there are no SIH modules #6 or #7 ... */
  151. };
  152. static const struct sih sih_modules_twl5031[8] = {
  153. [0] = {
  154. .name = "gpio",
  155. .module = TWL4030_MODULE_GPIO,
  156. .control_offset = REG_GPIO_SIH_CTRL,
  157. .set_cor = true,
  158. .bits = TWL4030_GPIO_MAX,
  159. .bytes_ixr = 3,
  160. /* Note: *all* of these IRQs default to no-trigger */
  161. .edr_offset = REG_GPIO_EDR1,
  162. .bytes_edr = 5,
  163. .irq_lines = 2,
  164. .mask = { {
  165. .isr_offset = REG_GPIO_ISR1A,
  166. .imr_offset = REG_GPIO_IMR1A,
  167. }, {
  168. .isr_offset = REG_GPIO_ISR1B,
  169. .imr_offset = REG_GPIO_IMR1B,
  170. }, },
  171. },
  172. [1] = {
  173. .name = "keypad",
  174. .set_cor = true,
  175. SIH_INITIALIZER(KEYPAD_KEYP, 4)
  176. },
  177. [2] = {
  178. .name = "bci",
  179. .module = TWL5031_MODULE_INTERRUPTS,
  180. .control_offset = TWL5031_INTERRUPTS_BCISIHCTRL,
  181. .bits = 7,
  182. .bytes_ixr = 1,
  183. .edr_offset = TWL5031_INTERRUPTS_BCIEDR1,
  184. /* Note: most of these IRQs default to no-trigger */
  185. .bytes_edr = 2,
  186. .irq_lines = 2,
  187. .mask = { {
  188. .isr_offset = TWL5031_INTERRUPTS_BCIISR1,
  189. .imr_offset = TWL5031_INTERRUPTS_BCIIMR1,
  190. }, {
  191. .isr_offset = TWL5031_INTERRUPTS_BCIISR2,
  192. .imr_offset = TWL5031_INTERRUPTS_BCIIMR2,
  193. }, },
  194. },
  195. [3] = {
  196. .name = "madc",
  197. SIH_INITIALIZER(MADC, 4)
  198. },
  199. [4] = {
  200. /* USB doesn't use the same SIH organization */
  201. .name = "usb",
  202. },
  203. [5] = {
  204. .name = "power",
  205. .set_cor = true,
  206. SIH_INITIALIZER(INT_PWR, 8)
  207. },
  208. [6] = {
  209. /*
  210. * ECI/DBI doesn't use the same SIH organization.
  211. * For example, it supports only one interrupt output line.
  212. * That is, the interrupts are seen on both INT1 and INT2 lines.
  213. */
  214. .name = "eci_dbi",
  215. .module = TWL5031_MODULE_ACCESSORY,
  216. .bits = 9,
  217. .bytes_ixr = 2,
  218. .irq_lines = 1,
  219. .mask = { {
  220. .isr_offset = TWL5031_ACIIDR_LSB,
  221. .imr_offset = TWL5031_ACIIMR_LSB,
  222. }, },
  223. },
  224. [7] = {
  225. /* Audio accessory */
  226. .name = "audio",
  227. .module = TWL5031_MODULE_ACCESSORY,
  228. .control_offset = TWL5031_ACCSIHCTRL,
  229. .bits = 2,
  230. .bytes_ixr = 1,
  231. .edr_offset = TWL5031_ACCEDR1,
  232. /* Note: most of these IRQs default to no-trigger */
  233. .bytes_edr = 1,
  234. .irq_lines = 2,
  235. .mask = { {
  236. .isr_offset = TWL5031_ACCISR1,
  237. .imr_offset = TWL5031_ACCIMR1,
  238. }, {
  239. .isr_offset = TWL5031_ACCISR2,
  240. .imr_offset = TWL5031_ACCIMR2,
  241. }, },
  242. },
  243. };
  244. #undef TWL4030_MODULE_KEYPAD_KEYP
  245. #undef TWL4030_MODULE_INT_PWR
  246. #undef TWL4030_INT_PWR_EDR
  247. /*----------------------------------------------------------------------*/
  248. static unsigned twl4030_irq_base;
  249. /*
  250. * handle_twl4030_pih() is the desc->handle method for the twl4030 interrupt.
  251. * This is a chained interrupt, so there is no desc->action method for it.
  252. * Now we need to query the interrupt controller in the twl4030 to determine
  253. * which module is generating the interrupt request. However, we can't do i2c
  254. * transactions in interrupt context, so we must defer that work to a kernel
  255. * thread. All we do here is acknowledge and mask the interrupt and wakeup
  256. * the kernel thread.
  257. */
  258. static irqreturn_t handle_twl4030_pih(int irq, void *devid)
  259. {
  260. irqreturn_t ret;
  261. u8 pih_isr;
  262. ret = twl_i2c_read_u8(TWL_MODULE_PIH, &pih_isr,
  263. REG_PIH_ISR_P1);
  264. if (ret) {
  265. pr_warn("twl4030: I2C error %d reading PIH ISR\n", ret);
  266. return IRQ_NONE;
  267. }
  268. while (pih_isr) {
  269. unsigned long pending = __ffs(pih_isr);
  270. unsigned int irq;
  271. pih_isr &= ~BIT(pending);
  272. irq = pending + twl4030_irq_base;
  273. handle_nested_irq(irq);
  274. }
  275. return IRQ_HANDLED;
  276. }
  277. /*----------------------------------------------------------------------*/
  278. /*
  279. * twl4030_init_sih_modules() ... start from a known state where no
  280. * IRQs will be coming in, and where we can quickly enable them then
  281. * handle them as they arrive. Mask all IRQs: maybe init SIH_CTRL.
  282. *
  283. * NOTE: we don't touch EDR registers here; they stay with hardware
  284. * defaults or whatever the last value was. Note that when both EDR
  285. * bits for an IRQ are clear, that's as if its IMR bit is set...
  286. */
  287. static int twl4030_init_sih_modules(unsigned line)
  288. {
  289. const struct sih *sih;
  290. u8 buf[4];
  291. int i;
  292. int status;
  293. /* line 0 == int1_n signal; line 1 == int2_n signal */
  294. if (line > 1)
  295. return -EINVAL;
  296. irq_line = line;
  297. /* disable all interrupts on our line */
  298. memset(buf, 0xff, sizeof(buf));
  299. sih = sih_modules;
  300. for (i = 0; i < nr_sih_modules; i++, sih++) {
  301. /* skip USB -- it's funky */
  302. if (!sih->bytes_ixr)
  303. continue;
  304. /* Not all the SIH modules support multiple interrupt lines */
  305. if (sih->irq_lines <= line)
  306. continue;
  307. status = twl_i2c_write(sih->module, buf,
  308. sih->mask[line].imr_offset, sih->bytes_ixr);
  309. if (status < 0)
  310. pr_err("twl4030: err %d initializing %s %s\n",
  311. status, sih->name, "IMR");
  312. /*
  313. * Maybe disable "exclusive" mode; buffer second pending irq;
  314. * set Clear-On-Read (COR) bit.
  315. *
  316. * NOTE that sometimes COR polarity is documented as being
  317. * inverted: for MADC, COR=1 means "clear on write".
  318. * And for PWR_INT it's not documented...
  319. */
  320. if (sih->set_cor) {
  321. status = twl_i2c_write_u8(sih->module,
  322. TWL4030_SIH_CTRL_COR_MASK,
  323. sih->control_offset);
  324. if (status < 0)
  325. pr_err("twl4030: err %d initializing %s %s\n",
  326. status, sih->name, "SIH_CTRL");
  327. }
  328. }
  329. sih = sih_modules;
  330. for (i = 0; i < nr_sih_modules; i++, sih++) {
  331. u8 rxbuf[4];
  332. int j;
  333. /* skip USB */
  334. if (!sih->bytes_ixr)
  335. continue;
  336. /* Not all the SIH modules support multiple interrupt lines */
  337. if (sih->irq_lines <= line)
  338. continue;
  339. /*
  340. * Clear pending interrupt status. Either the read was
  341. * enough, or we need to write those bits. Repeat, in
  342. * case an IRQ is pending (PENDDIS=0) ... that's not
  343. * uncommon with PWR_INT.PWRON.
  344. */
  345. for (j = 0; j < 2; j++) {
  346. status = twl_i2c_read(sih->module, rxbuf,
  347. sih->mask[line].isr_offset, sih->bytes_ixr);
  348. if (status < 0)
  349. pr_warn("twl4030: err %d initializing %s %s\n",
  350. status, sih->name, "ISR");
  351. if (!sih->set_cor) {
  352. status = twl_i2c_write(sih->module, buf,
  353. sih->mask[line].isr_offset,
  354. sih->bytes_ixr);
  355. if (status < 0)
  356. pr_warn("twl4030: write failed: %d\n",
  357. status);
  358. }
  359. /*
  360. * else COR=1 means read sufficed.
  361. * (for most SIH modules...)
  362. */
  363. }
  364. }
  365. return 0;
  366. }
  367. static inline void activate_irq(int irq)
  368. {
  369. irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
  370. }
  371. /*----------------------------------------------------------------------*/
  372. struct sih_agent {
  373. int irq_base;
  374. const struct sih *sih;
  375. u32 imr;
  376. bool imr_change_pending;
  377. u32 edge_change;
  378. struct mutex irq_lock;
  379. char *irq_name;
  380. };
  381. /*----------------------------------------------------------------------*/
  382. /*
  383. * All irq_chip methods get issued from code holding irq_desc[irq].lock,
  384. * which can't perform the underlying I2C operations (because they sleep).
  385. * So we must hand them off to a thread (workqueue) and cope with asynch
  386. * completion, potentially including some re-ordering, of these requests.
  387. */
  388. static void twl4030_sih_mask(struct irq_data *data)
  389. {
  390. struct sih_agent *agent = irq_data_get_irq_chip_data(data);
  391. agent->imr |= BIT(data->irq - agent->irq_base);
  392. agent->imr_change_pending = true;
  393. }
  394. static void twl4030_sih_unmask(struct irq_data *data)
  395. {
  396. struct sih_agent *agent = irq_data_get_irq_chip_data(data);
  397. agent->imr &= ~BIT(data->irq - agent->irq_base);
  398. agent->imr_change_pending = true;
  399. }
  400. static int twl4030_sih_set_type(struct irq_data *data, unsigned trigger)
  401. {
  402. struct sih_agent *agent = irq_data_get_irq_chip_data(data);
  403. if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
  404. return -EINVAL;
  405. if (irqd_get_trigger_type(data) != trigger)
  406. agent->edge_change |= BIT(data->irq - agent->irq_base);
  407. return 0;
  408. }
  409. static void twl4030_sih_bus_lock(struct irq_data *data)
  410. {
  411. struct sih_agent *agent = irq_data_get_irq_chip_data(data);
  412. mutex_lock(&agent->irq_lock);
  413. }
  414. static void twl4030_sih_bus_sync_unlock(struct irq_data *data)
  415. {
  416. struct sih_agent *agent = irq_data_get_irq_chip_data(data);
  417. const struct sih *sih = agent->sih;
  418. int status;
  419. if (agent->imr_change_pending) {
  420. union {
  421. u32 word;
  422. u8 bytes[4];
  423. } imr;
  424. /* byte[0] gets overwritten as we write ... */
  425. imr.word = cpu_to_le32(agent->imr);
  426. agent->imr_change_pending = false;
  427. /* write the whole mask ... simpler than subsetting it */
  428. status = twl_i2c_write(sih->module, imr.bytes,
  429. sih->mask[irq_line].imr_offset,
  430. sih->bytes_ixr);
  431. if (status)
  432. pr_err("twl4030: %s, %s --> %d\n", __func__,
  433. "write", status);
  434. }
  435. if (agent->edge_change) {
  436. u32 edge_change;
  437. u8 bytes[6];
  438. edge_change = agent->edge_change;
  439. agent->edge_change = 0;
  440. /*
  441. * Read, reserving first byte for write scratch. Yes, this
  442. * could be cached for some speedup ... but be careful about
  443. * any processor on the other IRQ line, EDR registers are
  444. * shared.
  445. */
  446. status = twl_i2c_read(sih->module, bytes,
  447. sih->edr_offset, sih->bytes_edr);
  448. if (status) {
  449. pr_err("twl4030: %s, %s --> %d\n", __func__,
  450. "read", status);
  451. return;
  452. }
  453. /* Modify only the bits we know must change */
  454. while (edge_change) {
  455. int i = fls(edge_change) - 1;
  456. int byte = i >> 2;
  457. int off = (i & 0x3) * 2;
  458. unsigned int type;
  459. bytes[byte] &= ~(0x03 << off);
  460. type = irq_get_trigger_type(i + agent->irq_base);
  461. if (type & IRQ_TYPE_EDGE_RISING)
  462. bytes[byte] |= BIT(off + 1);
  463. if (type & IRQ_TYPE_EDGE_FALLING)
  464. bytes[byte] |= BIT(off + 0);
  465. edge_change &= ~BIT(i);
  466. }
  467. /* Write */
  468. status = twl_i2c_write(sih->module, bytes,
  469. sih->edr_offset, sih->bytes_edr);
  470. if (status)
  471. pr_err("twl4030: %s, %s --> %d\n", __func__,
  472. "write", status);
  473. }
  474. mutex_unlock(&agent->irq_lock);
  475. }
  476. static struct irq_chip twl4030_sih_irq_chip = {
  477. .name = "twl4030",
  478. .irq_mask = twl4030_sih_mask,
  479. .irq_unmask = twl4030_sih_unmask,
  480. .irq_set_type = twl4030_sih_set_type,
  481. .irq_bus_lock = twl4030_sih_bus_lock,
  482. .irq_bus_sync_unlock = twl4030_sih_bus_sync_unlock,
  483. .flags = IRQCHIP_SKIP_SET_WAKE,
  484. };
  485. /*----------------------------------------------------------------------*/
  486. static inline int sih_read_isr(const struct sih *sih)
  487. {
  488. int status;
  489. union {
  490. u8 bytes[4];
  491. u32 word;
  492. } isr;
  493. /* FIXME need retry-on-error ... */
  494. isr.word = 0;
  495. status = twl_i2c_read(sih->module, isr.bytes,
  496. sih->mask[irq_line].isr_offset, sih->bytes_ixr);
  497. return (status < 0) ? status : le32_to_cpu(isr.word);
  498. }
  499. /*
  500. * Generic handler for SIH interrupts ... we "know" this is called
  501. * in task context, with IRQs enabled.
  502. */
  503. static irqreturn_t handle_twl4030_sih(int irq, void *data)
  504. {
  505. struct sih_agent *agent = irq_get_handler_data(irq);
  506. const struct sih *sih = agent->sih;
  507. int isr;
  508. /* reading ISR acks the IRQs, using clear-on-read mode */
  509. isr = sih_read_isr(sih);
  510. if (isr < 0) {
  511. pr_err("twl4030: %s SIH, read ISR error %d\n",
  512. sih->name, isr);
  513. /* REVISIT: recover; eventually mask it all, etc */
  514. return IRQ_HANDLED;
  515. }
  516. while (isr) {
  517. irq = fls(isr);
  518. irq--;
  519. isr &= ~BIT(irq);
  520. if (irq < sih->bits)
  521. handle_nested_irq(agent->irq_base + irq);
  522. else
  523. pr_err("twl4030: %s SIH, invalid ISR bit %d\n",
  524. sih->name, irq);
  525. }
  526. return IRQ_HANDLED;
  527. }
  528. /* returns the first IRQ used by this SIH bank, or negative errno */
  529. int twl4030_sih_setup(struct device *dev, int module, int irq_base)
  530. {
  531. int sih_mod;
  532. const struct sih *sih = NULL;
  533. struct sih_agent *agent;
  534. int i, irq;
  535. int status = -EINVAL;
  536. /* only support modules with standard clear-on-read for now */
  537. for (sih_mod = 0, sih = sih_modules; sih_mod < nr_sih_modules;
  538. sih_mod++, sih++) {
  539. if (sih->module == module && sih->set_cor) {
  540. status = 0;
  541. break;
  542. }
  543. }
  544. if (status < 0) {
  545. dev_err(dev, "module to setup SIH for not found\n");
  546. return status;
  547. }
  548. agent = kzalloc(sizeof(*agent), GFP_KERNEL);
  549. if (!agent)
  550. return -ENOMEM;
  551. agent->irq_base = irq_base;
  552. agent->sih = sih;
  553. agent->imr = ~0;
  554. mutex_init(&agent->irq_lock);
  555. for (i = 0; i < sih->bits; i++) {
  556. irq = irq_base + i;
  557. irq_set_chip_data(irq, agent);
  558. irq_set_chip_and_handler(irq, &twl4030_sih_irq_chip,
  559. handle_edge_irq);
  560. irq_set_nested_thread(irq, 1);
  561. activate_irq(irq);
  562. }
  563. /* replace generic PIH handler (handle_simple_irq) */
  564. irq = sih_mod + twl4030_irq_base;
  565. irq_set_handler_data(irq, agent);
  566. agent->irq_name = kasprintf(GFP_KERNEL, "twl4030_%s", sih->name);
  567. status = request_threaded_irq(irq, NULL, handle_twl4030_sih,
  568. IRQF_EARLY_RESUME | IRQF_ONESHOT,
  569. agent->irq_name ?: sih->name, NULL);
  570. dev_info(dev, "%s (irq %d) chaining IRQs %d..%d\n", sih->name,
  571. irq, irq_base, irq_base + i - 1);
  572. return status < 0 ? status : irq_base;
  573. }
  574. /* FIXME need a call to reverse twl4030_sih_setup() ... */
  575. /*----------------------------------------------------------------------*/
  576. /* FIXME pass in which interrupt line we'll use ... */
  577. #define twl_irq_line 0
  578. int twl4030_init_irq(struct device *dev, int irq_num)
  579. {
  580. static struct irq_chip twl4030_irq_chip;
  581. int status, i;
  582. int irq_base, irq_end, nr_irqs;
  583. struct device_node *node = dev->of_node;
  584. /*
  585. * TWL core and pwr interrupts must be contiguous because
  586. * the hwirqs numbers are defined contiguously from 1 to 15.
  587. * Create only one domain for both.
  588. */
  589. nr_irqs = TWL4030_PWR_NR_IRQS + TWL4030_CORE_NR_IRQS;
  590. irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
  591. if (irq_base < 0) {
  592. dev_err(dev, "Fail to allocate IRQ descs\n");
  593. return irq_base;
  594. }
  595. irq_domain_add_legacy(node, nr_irqs, irq_base, 0,
  596. &irq_domain_simple_ops, NULL);
  597. irq_end = irq_base + TWL4030_CORE_NR_IRQS;
  598. /*
  599. * Mask and clear all TWL4030 interrupts since initially we do
  600. * not have any TWL4030 module interrupt handlers present
  601. */
  602. status = twl4030_init_sih_modules(twl_irq_line);
  603. if (status < 0)
  604. return status;
  605. twl4030_irq_base = irq_base;
  606. /*
  607. * Install an irq handler for each of the SIH modules;
  608. * clone dummy irq_chip since PIH can't *do* anything
  609. */
  610. twl4030_irq_chip = dummy_irq_chip;
  611. twl4030_irq_chip.name = "twl4030";
  612. twl4030_sih_irq_chip.irq_ack = dummy_irq_chip.irq_ack;
  613. for (i = irq_base; i < irq_end; i++) {
  614. irq_set_chip_and_handler(i, &twl4030_irq_chip,
  615. handle_simple_irq);
  616. irq_set_nested_thread(i, 1);
  617. activate_irq(i);
  618. }
  619. dev_info(dev, "%s (irq %d) chaining IRQs %d..%d\n", "PIH",
  620. irq_num, irq_base, irq_end);
  621. /* ... and the PWR_INT module ... */
  622. status = twl4030_sih_setup(dev, TWL4030_MODULE_INT, irq_end);
  623. if (status < 0) {
  624. dev_err(dev, "sih_setup PWR INT --> %d\n", status);
  625. goto fail;
  626. }
  627. /* install an irq handler to demultiplex the TWL4030 interrupt */
  628. status = request_threaded_irq(irq_num, NULL, handle_twl4030_pih,
  629. IRQF_ONESHOT,
  630. "TWL4030-PIH", NULL);
  631. if (status < 0) {
  632. dev_err(dev, "could not claim irq%d: %d\n", irq_num, status);
  633. goto fail_rqirq;
  634. }
  635. enable_irq_wake(irq_num);
  636. return irq_base;
  637. fail_rqirq:
  638. /* clean up twl4030_sih_setup */
  639. fail:
  640. for (i = irq_base; i < irq_end; i++) {
  641. irq_set_nested_thread(i, 0);
  642. irq_set_chip_and_handler(i, NULL, NULL);
  643. }
  644. return status;
  645. }
  646. int twl4030_exit_irq(void)
  647. {
  648. /* FIXME undo twl_init_irq() */
  649. if (twl4030_irq_base) {
  650. pr_err("twl4030: can't yet clean up IRQs?\n");
  651. return -ENOSYS;
  652. }
  653. return 0;
  654. }
  655. int twl4030_init_chip_irq(const char *chip)
  656. {
  657. if (!strcmp(chip, "twl5031")) {
  658. sih_modules = sih_modules_twl5031;
  659. nr_sih_modules = ARRAY_SIZE(sih_modules_twl5031);
  660. } else {
  661. sih_modules = sih_modules_twl4030;
  662. nr_sih_modules = ARRAY_SIZE(sih_modules_twl4030);
  663. }
  664. return 0;
  665. }