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/drivers/gpio/gpio-ep93xx.c

http://github.com/mirrors/linux
C | 445 lines | 323 code | 72 blank | 50 comment | 27 complexity | a8afa4e372c2afa2dfbabf1d03727252 MD5 | raw file
  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Generic EP93xx GPIO handling
  4 *
  5 * Copyright (c) 2008 Ryan Mallon
  6 * Copyright (c) 2011 H Hartley Sweeten <hsweeten@visionengravers.com>
  7 *
  8 * Based on code originally from:
  9 *  linux/arch/arm/mach-ep93xx/core.c
 10 */
 11
 12#include <linux/init.h>
 13#include <linux/module.h>
 14#include <linux/platform_device.h>
 15#include <linux/io.h>
 16#include <linux/irq.h>
 17#include <linux/slab.h>
 18#include <linux/gpio/driver.h>
 19#include <linux/bitops.h>
 20
 21#define EP93XX_GPIO_F_INT_STATUS 0x5c
 22#define EP93XX_GPIO_A_INT_STATUS 0xa0
 23#define EP93XX_GPIO_B_INT_STATUS 0xbc
 24
 25/* Maximum value for gpio line identifiers */
 26#define EP93XX_GPIO_LINE_MAX 63
 27
 28/* Maximum value for irq capable line identifiers */
 29#define EP93XX_GPIO_LINE_MAX_IRQ 23
 30
 31/*
 32 * Static mapping of GPIO bank F IRQS:
 33 * F0..F7 (16..24) to irq 80..87.
 34 */
 35#define EP93XX_GPIO_F_IRQ_BASE 80
 36
 37struct ep93xx_gpio {
 38	void __iomem		*base;
 39	struct gpio_chip	gc[8];
 40};
 41
 42/*************************************************************************
 43 * Interrupt handling for EP93xx on-chip GPIOs
 44 *************************************************************************/
 45static unsigned char gpio_int_unmasked[3];
 46static unsigned char gpio_int_enabled[3];
 47static unsigned char gpio_int_type1[3];
 48static unsigned char gpio_int_type2[3];
 49static unsigned char gpio_int_debounce[3];
 50
 51/* Port ordering is: A B F */
 52static const u8 int_type1_register_offset[3]	= { 0x90, 0xac, 0x4c };
 53static const u8 int_type2_register_offset[3]	= { 0x94, 0xb0, 0x50 };
 54static const u8 eoi_register_offset[3]		= { 0x98, 0xb4, 0x54 };
 55static const u8 int_en_register_offset[3]	= { 0x9c, 0xb8, 0x58 };
 56static const u8 int_debounce_register_offset[3]	= { 0xa8, 0xc4, 0x64 };
 57
 58static void ep93xx_gpio_update_int_params(struct ep93xx_gpio *epg, unsigned port)
 59{
 60	BUG_ON(port > 2);
 61
 62	writeb_relaxed(0, epg->base + int_en_register_offset[port]);
 63
 64	writeb_relaxed(gpio_int_type2[port],
 65		       epg->base + int_type2_register_offset[port]);
 66
 67	writeb_relaxed(gpio_int_type1[port],
 68		       epg->base + int_type1_register_offset[port]);
 69
 70	writeb(gpio_int_unmasked[port] & gpio_int_enabled[port],
 71	       epg->base + int_en_register_offset[port]);
 72}
 73
 74static int ep93xx_gpio_port(struct gpio_chip *gc)
 75{
 76	struct ep93xx_gpio *epg = gpiochip_get_data(gc);
 77	int port = 0;
 78
 79	while (port < ARRAY_SIZE(epg->gc) && gc != &epg->gc[port])
 80		port++;
 81
 82	/* This should not happen but is there as a last safeguard */
 83	if (port == ARRAY_SIZE(epg->gc)) {
 84		pr_crit("can't find the GPIO port\n");
 85		return 0;
 86	}
 87
 88	return port;
 89}
 90
 91static void ep93xx_gpio_int_debounce(struct gpio_chip *gc,
 92				     unsigned int offset, bool enable)
 93{
 94	struct ep93xx_gpio *epg = gpiochip_get_data(gc);
 95	int port = ep93xx_gpio_port(gc);
 96	int port_mask = BIT(offset);
 97
 98	if (enable)
 99		gpio_int_debounce[port] |= port_mask;
100	else
101		gpio_int_debounce[port] &= ~port_mask;
102
103	writeb(gpio_int_debounce[port],
104	       epg->base + int_debounce_register_offset[port]);
105}
106
107static void ep93xx_gpio_ab_irq_handler(struct irq_desc *desc)
108{
109	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
110	struct ep93xx_gpio *epg = gpiochip_get_data(gc);
111	struct irq_chip *irqchip = irq_desc_get_chip(desc);
112	unsigned long stat;
113	int offset;
114
115	chained_irq_enter(irqchip, desc);
116
117	/*
118	 * Dispatch the IRQs to the irqdomain of each A and B
119	 * gpiochip irqdomains depending on what has fired.
120	 * The tricky part is that the IRQ line is shared
121	 * between bank A and B and each has their own gpiochip.
122	 */
123	stat = readb(epg->base + EP93XX_GPIO_A_INT_STATUS);
124	for_each_set_bit(offset, &stat, 8)
125		generic_handle_irq(irq_find_mapping(epg->gc[0].irq.domain,
126						    offset));
127
128	stat = readb(epg->base + EP93XX_GPIO_B_INT_STATUS);
129	for_each_set_bit(offset, &stat, 8)
130		generic_handle_irq(irq_find_mapping(epg->gc[1].irq.domain,
131						    offset));
132
133	chained_irq_exit(irqchip, desc);
134}
135
136static void ep93xx_gpio_f_irq_handler(struct irq_desc *desc)
137{
138	/*
139	 * map discontiguous hw irq range to continuous sw irq range:
140	 *
141	 *  IRQ_EP93XX_GPIO{0..7}MUX -> EP93XX_GPIO_LINE_F{0..7}
142	 */
143	struct irq_chip *irqchip = irq_desc_get_chip(desc);
144	unsigned int irq = irq_desc_get_irq(desc);
145	int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */
146	int gpio_irq = EP93XX_GPIO_F_IRQ_BASE + port_f_idx;
147
148	chained_irq_enter(irqchip, desc);
149	generic_handle_irq(gpio_irq);
150	chained_irq_exit(irqchip, desc);
151}
152
153static void ep93xx_gpio_irq_ack(struct irq_data *d)
154{
155	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
156	struct ep93xx_gpio *epg = gpiochip_get_data(gc);
157	int port = ep93xx_gpio_port(gc);
158	int port_mask = BIT(d->irq & 7);
159
160	if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
161		gpio_int_type2[port] ^= port_mask; /* switch edge direction */
162		ep93xx_gpio_update_int_params(epg, port);
163	}
164
165	writeb(port_mask, epg->base + eoi_register_offset[port]);
166}
167
168static void ep93xx_gpio_irq_mask_ack(struct irq_data *d)
169{
170	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
171	struct ep93xx_gpio *epg = gpiochip_get_data(gc);
172	int port = ep93xx_gpio_port(gc);
173	int port_mask = BIT(d->irq & 7);
174
175	if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH)
176		gpio_int_type2[port] ^= port_mask; /* switch edge direction */
177
178	gpio_int_unmasked[port] &= ~port_mask;
179	ep93xx_gpio_update_int_params(epg, port);
180
181	writeb(port_mask, epg->base + eoi_register_offset[port]);
182}
183
184static void ep93xx_gpio_irq_mask(struct irq_data *d)
185{
186	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
187	struct ep93xx_gpio *epg = gpiochip_get_data(gc);
188	int port = ep93xx_gpio_port(gc);
189
190	gpio_int_unmasked[port] &= ~BIT(d->irq & 7);
191	ep93xx_gpio_update_int_params(epg, port);
192}
193
194static void ep93xx_gpio_irq_unmask(struct irq_data *d)
195{
196	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
197	struct ep93xx_gpio *epg = gpiochip_get_data(gc);
198	int port = ep93xx_gpio_port(gc);
199
200	gpio_int_unmasked[port] |= BIT(d->irq & 7);
201	ep93xx_gpio_update_int_params(epg, port);
202}
203
204/*
205 * gpio_int_type1 controls whether the interrupt is level (0) or
206 * edge (1) triggered, while gpio_int_type2 controls whether it
207 * triggers on low/falling (0) or high/rising (1).
208 */
209static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type)
210{
211	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
212	struct ep93xx_gpio *epg = gpiochip_get_data(gc);
213	int port = ep93xx_gpio_port(gc);
214	int offset = d->irq & 7;
215	int port_mask = BIT(offset);
216	irq_flow_handler_t handler;
217
218	gc->direction_input(gc, offset);
219
220	switch (type) {
221	case IRQ_TYPE_EDGE_RISING:
222		gpio_int_type1[port] |= port_mask;
223		gpio_int_type2[port] |= port_mask;
224		handler = handle_edge_irq;
225		break;
226	case IRQ_TYPE_EDGE_FALLING:
227		gpio_int_type1[port] |= port_mask;
228		gpio_int_type2[port] &= ~port_mask;
229		handler = handle_edge_irq;
230		break;
231	case IRQ_TYPE_LEVEL_HIGH:
232		gpio_int_type1[port] &= ~port_mask;
233		gpio_int_type2[port] |= port_mask;
234		handler = handle_level_irq;
235		break;
236	case IRQ_TYPE_LEVEL_LOW:
237		gpio_int_type1[port] &= ~port_mask;
238		gpio_int_type2[port] &= ~port_mask;
239		handler = handle_level_irq;
240		break;
241	case IRQ_TYPE_EDGE_BOTH:
242		gpio_int_type1[port] |= port_mask;
243		/* set initial polarity based on current input level */
244		if (gc->get(gc, offset))
245			gpio_int_type2[port] &= ~port_mask; /* falling */
246		else
247			gpio_int_type2[port] |= port_mask; /* rising */
248		handler = handle_edge_irq;
249		break;
250	default:
251		return -EINVAL;
252	}
253
254	irq_set_handler_locked(d, handler);
255
256	gpio_int_enabled[port] |= port_mask;
257
258	ep93xx_gpio_update_int_params(epg, port);
259
260	return 0;
261}
262
263static struct irq_chip ep93xx_gpio_irq_chip = {
264	.name		= "GPIO",
265	.irq_ack	= ep93xx_gpio_irq_ack,
266	.irq_mask_ack	= ep93xx_gpio_irq_mask_ack,
267	.irq_mask	= ep93xx_gpio_irq_mask,
268	.irq_unmask	= ep93xx_gpio_irq_unmask,
269	.irq_set_type	= ep93xx_gpio_irq_type,
270};
271
272/*************************************************************************
273 * gpiolib interface for EP93xx on-chip GPIOs
274 *************************************************************************/
275struct ep93xx_gpio_bank {
276	const char	*label;
277	int		data;
278	int		dir;
279	int		base;
280	bool		has_irq;
281	bool		has_hierarchical_irq;
282	unsigned int	irq_base;
283};
284
285#define EP93XX_GPIO_BANK(_label, _data, _dir, _base, _has_irq, _has_hier, _irq_base) \
286	{							\
287		.label		= _label,			\
288		.data		= _data,			\
289		.dir		= _dir,				\
290		.base		= _base,			\
291		.has_irq	= _has_irq,			\
292		.has_hierarchical_irq = _has_hier,		\
293		.irq_base	= _irq_base,			\
294	}
295
296static struct ep93xx_gpio_bank ep93xx_gpio_banks[] = {
297	/* Bank A has 8 IRQs */
298	EP93XX_GPIO_BANK("A", 0x00, 0x10, 0, true, false, 64),
299	/* Bank B has 8 IRQs */
300	EP93XX_GPIO_BANK("B", 0x04, 0x14, 8, true, false, 72),
301	EP93XX_GPIO_BANK("C", 0x08, 0x18, 40, false, false, 0),
302	EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 24, false, false, 0),
303	EP93XX_GPIO_BANK("E", 0x20, 0x24, 32, false, false, 0),
304	/* Bank F has 8 IRQs */
305	EP93XX_GPIO_BANK("F", 0x30, 0x34, 16, false, true, 0),
306	EP93XX_GPIO_BANK("G", 0x38, 0x3c, 48, false, false, 0),
307	EP93XX_GPIO_BANK("H", 0x40, 0x44, 56, false, false, 0),
308};
309
310static int ep93xx_gpio_set_config(struct gpio_chip *gc, unsigned offset,
311				  unsigned long config)
312{
313	u32 debounce;
314
315	if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
316		return -ENOTSUPP;
317
318	debounce = pinconf_to_config_argument(config);
319	ep93xx_gpio_int_debounce(gc, offset, debounce ? true : false);
320
321	return 0;
322}
323
324static int ep93xx_gpio_f_to_irq(struct gpio_chip *gc, unsigned offset)
325{
326	return EP93XX_GPIO_F_IRQ_BASE + offset;
327}
328
329static int ep93xx_gpio_add_bank(struct gpio_chip *gc,
330				struct platform_device *pdev,
331				struct ep93xx_gpio *epg,
332				struct ep93xx_gpio_bank *bank)
333{
334	void __iomem *data = epg->base + bank->data;
335	void __iomem *dir = epg->base + bank->dir;
336	struct device *dev = &pdev->dev;
337	struct gpio_irq_chip *girq;
338	int err;
339
340	err = bgpio_init(gc, dev, 1, data, NULL, NULL, dir, NULL, 0);
341	if (err)
342		return err;
343
344	gc->label = bank->label;
345	gc->base = bank->base;
346
347	girq = &gc->irq;
348	if (bank->has_irq || bank->has_hierarchical_irq) {
349		gc->set_config = ep93xx_gpio_set_config;
350		girq->chip = &ep93xx_gpio_irq_chip;
351	}
352
353	if (bank->has_irq) {
354		int ab_parent_irq = platform_get_irq(pdev, 0);
355
356		girq->parent_handler = ep93xx_gpio_ab_irq_handler;
357		girq->num_parents = 1;
358		girq->parents = devm_kcalloc(dev, 1,
359					     sizeof(*girq->parents),
360					     GFP_KERNEL);
361		if (!girq->parents)
362			return -ENOMEM;
363		girq->default_type = IRQ_TYPE_NONE;
364		girq->handler = handle_level_irq;
365		girq->parents[0] = ab_parent_irq;
366		girq->first = bank->irq_base;
367	}
368
369	/* Only bank F has especially funky IRQ handling */
370	if (bank->has_hierarchical_irq) {
371		int gpio_irq;
372		int i;
373
374		/*
375		 * FIXME: convert this to use hierarchical IRQ support!
376		 * this requires fixing the root irqchip to be hierarchial.
377		 */
378		girq->parent_handler = ep93xx_gpio_f_irq_handler;
379		girq->num_parents = 8;
380		girq->parents = devm_kcalloc(dev, 8,
381					     sizeof(*girq->parents),
382					     GFP_KERNEL);
383		if (!girq->parents)
384			return -ENOMEM;
385		/* Pick resources 1..8 for these IRQs */
386		for (i = 1; i <= 8; i++)
387			girq->parents[i - 1] = platform_get_irq(pdev, i);
388		for (i = 0; i < 8; i++) {
389			gpio_irq = EP93XX_GPIO_F_IRQ_BASE + i;
390			irq_set_chip_data(gpio_irq, &epg->gc[5]);
391			irq_set_chip_and_handler(gpio_irq,
392						 &ep93xx_gpio_irq_chip,
393						 handle_level_irq);
394			irq_clear_status_flags(gpio_irq, IRQ_NOREQUEST);
395		}
396		girq->default_type = IRQ_TYPE_NONE;
397		girq->handler = handle_level_irq;
398		gc->to_irq = ep93xx_gpio_f_to_irq;
399	}
400
401	return devm_gpiochip_add_data(dev, gc, epg);
402}
403
404static int ep93xx_gpio_probe(struct platform_device *pdev)
405{
406	struct ep93xx_gpio *epg;
407	int i;
408
409	epg = devm_kzalloc(&pdev->dev, sizeof(*epg), GFP_KERNEL);
410	if (!epg)
411		return -ENOMEM;
412
413	epg->base = devm_platform_ioremap_resource(pdev, 0);
414	if (IS_ERR(epg->base))
415		return PTR_ERR(epg->base);
416
417	for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) {
418		struct gpio_chip *gc = &epg->gc[i];
419		struct ep93xx_gpio_bank *bank = &ep93xx_gpio_banks[i];
420
421		if (ep93xx_gpio_add_bank(gc, pdev, epg, bank))
422			dev_warn(&pdev->dev, "Unable to add gpio bank %s\n",
423				 bank->label);
424	}
425
426	return 0;
427}
428
429static struct platform_driver ep93xx_gpio_driver = {
430	.driver		= {
431		.name	= "gpio-ep93xx",
432	},
433	.probe		= ep93xx_gpio_probe,
434};
435
436static int __init ep93xx_gpio_init(void)
437{
438	return platform_driver_register(&ep93xx_gpio_driver);
439}
440postcore_initcall(ep93xx_gpio_init);
441
442MODULE_AUTHOR("Ryan Mallon <ryan@bluewatersys.com> "
443		"H Hartley Sweeten <hsweeten@visionengravers.com>");
444MODULE_DESCRIPTION("EP93XX GPIO driver");
445MODULE_LICENSE("GPL");