/drivers/gpio/gpio-sx150x.c

http://github.com/mirrors/linux · C · 794 lines · 614 code · 95 blank · 85 comment · 64 complexity · 65f922d02b6ba21d4027a70a73cc90ef MD5 · raw file

  1. /* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
  2. *
  3. * Driver for Semtech SX150X I2C GPIO Expanders
  4. *
  5. * Author: Gregory Bean <gbean@codeaurora.org>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 and
  9. * only version 2 as published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  19. * 02110-1301, USA.
  20. */
  21. #include <linux/gpio.h>
  22. #include <linux/i2c.h>
  23. #include <linux/init.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/irq.h>
  26. #include <linux/mutex.h>
  27. #include <linux/slab.h>
  28. #include <linux/of.h>
  29. #include <linux/of_address.h>
  30. #include <linux/of_irq.h>
  31. #include <linux/of_gpio.h>
  32. #include <linux/of_device.h>
  33. #define NO_UPDATE_PENDING -1
  34. /* The chip models of sx150x */
  35. #define SX150X_123 0
  36. #define SX150X_456 1
  37. #define SX150X_789 2
  38. struct sx150x_123_pri {
  39. u8 reg_pld_mode;
  40. u8 reg_pld_table0;
  41. u8 reg_pld_table1;
  42. u8 reg_pld_table2;
  43. u8 reg_pld_table3;
  44. u8 reg_pld_table4;
  45. u8 reg_advance;
  46. };
  47. struct sx150x_456_pri {
  48. u8 reg_pld_mode;
  49. u8 reg_pld_table0;
  50. u8 reg_pld_table1;
  51. u8 reg_pld_table2;
  52. u8 reg_pld_table3;
  53. u8 reg_pld_table4;
  54. u8 reg_advance;
  55. };
  56. struct sx150x_789_pri {
  57. u8 reg_drain;
  58. u8 reg_polarity;
  59. u8 reg_clock;
  60. u8 reg_misc;
  61. u8 reg_reset;
  62. u8 ngpios;
  63. };
  64. struct sx150x_device_data {
  65. u8 model;
  66. u8 reg_pullup;
  67. u8 reg_pulldn;
  68. u8 reg_dir;
  69. u8 reg_data;
  70. u8 reg_irq_mask;
  71. u8 reg_irq_src;
  72. u8 reg_sense;
  73. u8 ngpios;
  74. union {
  75. struct sx150x_123_pri x123;
  76. struct sx150x_456_pri x456;
  77. struct sx150x_789_pri x789;
  78. } pri;
  79. };
  80. /**
  81. * struct sx150x_platform_data - config data for SX150x driver
  82. * @gpio_base: The index number of the first GPIO assigned to this
  83. * GPIO expander. The expander will create a block of
  84. * consecutively numbered gpios beginning at the given base,
  85. * with the size of the block depending on the model of the
  86. * expander chip.
  87. * @oscio_is_gpo: If set to true, the driver will configure OSCIO as a GPO
  88. * instead of as an oscillator, increasing the size of the
  89. * GP(I)O pool created by this expander by one. The
  90. * output-only GPO pin will be added at the end of the block.
  91. * @io_pullup_ena: A bit-mask which enables or disables the pull-up resistor
  92. * for each IO line in the expander. Setting the bit at
  93. * position n will enable the pull-up for the IO at
  94. * the corresponding offset. For chips with fewer than
  95. * 16 IO pins, high-end bits are ignored.
  96. * @io_pulldn_ena: A bit-mask which enables-or disables the pull-down
  97. * resistor for each IO line in the expander. Setting the
  98. * bit at position n will enable the pull-down for the IO at
  99. * the corresponding offset. For chips with fewer than
  100. * 16 IO pins, high-end bits are ignored.
  101. * @io_polarity: A bit-mask which enables polarity inversion for each IO line
  102. * in the expander. Setting the bit at position n inverts
  103. * the polarity of that IO line, while clearing it results
  104. * in normal polarity. For chips with fewer than 16 IO pins,
  105. * high-end bits are ignored.
  106. * @irq_summary: The 'summary IRQ' line to which the GPIO expander's INT line
  107. * is connected, via which it reports interrupt events
  108. * across all GPIO lines. This must be a real,
  109. * pre-existing IRQ line.
  110. * Setting this value < 0 disables the irq_chip functionality
  111. * of the driver.
  112. * @irq_base: The first 'virtual IRQ' line at which our block of GPIO-based
  113. * IRQ lines will appear. Similarly to gpio_base, the expander
  114. * will create a block of irqs beginning at this number.
  115. * This value is ignored if irq_summary is < 0.
  116. * @reset_during_probe: If set to true, the driver will trigger a full
  117. * reset of the chip at the beginning of the probe
  118. * in order to place it in a known state.
  119. */
  120. struct sx150x_platform_data {
  121. unsigned gpio_base;
  122. bool oscio_is_gpo;
  123. u16 io_pullup_ena;
  124. u16 io_pulldn_ena;
  125. u16 io_polarity;
  126. int irq_summary;
  127. unsigned irq_base;
  128. bool reset_during_probe;
  129. };
  130. struct sx150x_chip {
  131. struct gpio_chip gpio_chip;
  132. struct i2c_client *client;
  133. const struct sx150x_device_data *dev_cfg;
  134. int irq_summary;
  135. int irq_base;
  136. int irq_update;
  137. u32 irq_sense;
  138. u32 irq_masked;
  139. u32 dev_sense;
  140. u32 dev_masked;
  141. struct irq_chip irq_chip;
  142. struct mutex lock;
  143. };
  144. static const struct sx150x_device_data sx150x_devices[] = {
  145. [0] = { /* sx1508q */
  146. .model = SX150X_789,
  147. .reg_pullup = 0x03,
  148. .reg_pulldn = 0x04,
  149. .reg_dir = 0x07,
  150. .reg_data = 0x08,
  151. .reg_irq_mask = 0x09,
  152. .reg_irq_src = 0x0c,
  153. .reg_sense = 0x0b,
  154. .pri.x789 = {
  155. .reg_drain = 0x05,
  156. .reg_polarity = 0x06,
  157. .reg_clock = 0x0f,
  158. .reg_misc = 0x10,
  159. .reg_reset = 0x7d,
  160. },
  161. .ngpios = 8,
  162. },
  163. [1] = { /* sx1509q */
  164. .model = SX150X_789,
  165. .reg_pullup = 0x07,
  166. .reg_pulldn = 0x09,
  167. .reg_dir = 0x0f,
  168. .reg_data = 0x11,
  169. .reg_irq_mask = 0x13,
  170. .reg_irq_src = 0x19,
  171. .reg_sense = 0x17,
  172. .pri.x789 = {
  173. .reg_drain = 0x0b,
  174. .reg_polarity = 0x0d,
  175. .reg_clock = 0x1e,
  176. .reg_misc = 0x1f,
  177. .reg_reset = 0x7d,
  178. },
  179. .ngpios = 16
  180. },
  181. [2] = { /* sx1506q */
  182. .model = SX150X_456,
  183. .reg_pullup = 0x05,
  184. .reg_pulldn = 0x07,
  185. .reg_dir = 0x03,
  186. .reg_data = 0x01,
  187. .reg_irq_mask = 0x09,
  188. .reg_irq_src = 0x0f,
  189. .reg_sense = 0x0d,
  190. .pri.x456 = {
  191. .reg_pld_mode = 0x21,
  192. .reg_pld_table0 = 0x23,
  193. .reg_pld_table1 = 0x25,
  194. .reg_pld_table2 = 0x27,
  195. .reg_pld_table3 = 0x29,
  196. .reg_pld_table4 = 0x2b,
  197. .reg_advance = 0xad,
  198. },
  199. .ngpios = 16
  200. },
  201. [3] = { /* sx1502q */
  202. .model = SX150X_123,
  203. .reg_pullup = 0x02,
  204. .reg_pulldn = 0x03,
  205. .reg_dir = 0x01,
  206. .reg_data = 0x00,
  207. .reg_irq_mask = 0x05,
  208. .reg_irq_src = 0x08,
  209. .reg_sense = 0x07,
  210. .pri.x123 = {
  211. .reg_pld_mode = 0x10,
  212. .reg_pld_table0 = 0x11,
  213. .reg_pld_table1 = 0x12,
  214. .reg_pld_table2 = 0x13,
  215. .reg_pld_table3 = 0x14,
  216. .reg_pld_table4 = 0x15,
  217. .reg_advance = 0xad,
  218. },
  219. .ngpios = 8,
  220. },
  221. };
  222. static const struct i2c_device_id sx150x_id[] = {
  223. {"sx1508q", 0},
  224. {"sx1509q", 1},
  225. {"sx1506q", 2},
  226. {"sx1502q", 3},
  227. {}
  228. };
  229. MODULE_DEVICE_TABLE(i2c, sx150x_id);
  230. static const struct of_device_id sx150x_of_match[] = {
  231. { .compatible = "semtech,sx1508q" },
  232. { .compatible = "semtech,sx1509q" },
  233. { .compatible = "semtech,sx1506q" },
  234. { .compatible = "semtech,sx1502q" },
  235. {},
  236. };
  237. MODULE_DEVICE_TABLE(of, sx150x_of_match);
  238. static s32 sx150x_i2c_write(struct i2c_client *client, u8 reg, u8 val)
  239. {
  240. s32 err = i2c_smbus_write_byte_data(client, reg, val);
  241. if (err < 0)
  242. dev_warn(&client->dev,
  243. "i2c write fail: can't write %02x to %02x: %d\n",
  244. val, reg, err);
  245. return err;
  246. }
  247. static s32 sx150x_i2c_read(struct i2c_client *client, u8 reg, u8 *val)
  248. {
  249. s32 err = i2c_smbus_read_byte_data(client, reg);
  250. if (err >= 0)
  251. *val = err;
  252. else
  253. dev_warn(&client->dev,
  254. "i2c read fail: can't read from %02x: %d\n",
  255. reg, err);
  256. return err;
  257. }
  258. static inline bool offset_is_oscio(struct sx150x_chip *chip, unsigned offset)
  259. {
  260. return (chip->dev_cfg->ngpios == offset);
  261. }
  262. /*
  263. * These utility functions solve the common problem of locating and setting
  264. * configuration bits. Configuration bits are grouped into registers
  265. * whose indexes increase downwards. For example, with eight-bit registers,
  266. * sixteen gpios would have their config bits grouped in the following order:
  267. * REGISTER N-1 [ f e d c b a 9 8 ]
  268. * N [ 7 6 5 4 3 2 1 0 ]
  269. *
  270. * For multi-bit configurations, the pattern gets wider:
  271. * REGISTER N-3 [ f f e e d d c c ]
  272. * N-2 [ b b a a 9 9 8 8 ]
  273. * N-1 [ 7 7 6 6 5 5 4 4 ]
  274. * N [ 3 3 2 2 1 1 0 0 ]
  275. *
  276. * Given the address of the starting register 'N', the index of the gpio
  277. * whose configuration we seek to change, and the width in bits of that
  278. * configuration, these functions allow us to locate the correct
  279. * register and mask the correct bits.
  280. */
  281. static inline void sx150x_find_cfg(u8 offset, u8 width,
  282. u8 *reg, u8 *mask, u8 *shift)
  283. {
  284. *reg -= offset * width / 8;
  285. *mask = (1 << width) - 1;
  286. *shift = (offset * width) % 8;
  287. *mask <<= *shift;
  288. }
  289. static s32 sx150x_write_cfg(struct sx150x_chip *chip,
  290. u8 offset, u8 width, u8 reg, u8 val)
  291. {
  292. u8 mask;
  293. u8 data;
  294. u8 shift;
  295. s32 err;
  296. sx150x_find_cfg(offset, width, &reg, &mask, &shift);
  297. err = sx150x_i2c_read(chip->client, reg, &data);
  298. if (err < 0)
  299. return err;
  300. data &= ~mask;
  301. data |= (val << shift) & mask;
  302. return sx150x_i2c_write(chip->client, reg, data);
  303. }
  304. static int sx150x_get_io(struct sx150x_chip *chip, unsigned offset)
  305. {
  306. u8 reg = chip->dev_cfg->reg_data;
  307. u8 mask;
  308. u8 data;
  309. u8 shift;
  310. s32 err;
  311. sx150x_find_cfg(offset, 1, &reg, &mask, &shift);
  312. err = sx150x_i2c_read(chip->client, reg, &data);
  313. if (err >= 0)
  314. err = (data & mask) != 0 ? 1 : 0;
  315. return err;
  316. }
  317. static void sx150x_set_oscio(struct sx150x_chip *chip, int val)
  318. {
  319. sx150x_i2c_write(chip->client,
  320. chip->dev_cfg->pri.x789.reg_clock,
  321. (val ? 0x1f : 0x10));
  322. }
  323. static void sx150x_set_io(struct sx150x_chip *chip, unsigned offset, int val)
  324. {
  325. sx150x_write_cfg(chip,
  326. offset,
  327. 1,
  328. chip->dev_cfg->reg_data,
  329. (val ? 1 : 0));
  330. }
  331. static int sx150x_io_input(struct sx150x_chip *chip, unsigned offset)
  332. {
  333. return sx150x_write_cfg(chip,
  334. offset,
  335. 1,
  336. chip->dev_cfg->reg_dir,
  337. 1);
  338. }
  339. static int sx150x_io_output(struct sx150x_chip *chip, unsigned offset, int val)
  340. {
  341. int err;
  342. err = sx150x_write_cfg(chip,
  343. offset,
  344. 1,
  345. chip->dev_cfg->reg_data,
  346. (val ? 1 : 0));
  347. if (err >= 0)
  348. err = sx150x_write_cfg(chip,
  349. offset,
  350. 1,
  351. chip->dev_cfg->reg_dir,
  352. 0);
  353. return err;
  354. }
  355. static int sx150x_gpio_get(struct gpio_chip *gc, unsigned offset)
  356. {
  357. struct sx150x_chip *chip = gpiochip_get_data(gc);
  358. int status = -EINVAL;
  359. if (!offset_is_oscio(chip, offset)) {
  360. mutex_lock(&chip->lock);
  361. status = sx150x_get_io(chip, offset);
  362. mutex_unlock(&chip->lock);
  363. }
  364. return (status < 0) ? status : !!status;
  365. }
  366. static void sx150x_gpio_set(struct gpio_chip *gc, unsigned offset, int val)
  367. {
  368. struct sx150x_chip *chip = gpiochip_get_data(gc);
  369. mutex_lock(&chip->lock);
  370. if (offset_is_oscio(chip, offset))
  371. sx150x_set_oscio(chip, val);
  372. else
  373. sx150x_set_io(chip, offset, val);
  374. mutex_unlock(&chip->lock);
  375. }
  376. static int sx150x_gpio_set_single_ended(struct gpio_chip *gc,
  377. unsigned offset,
  378. enum single_ended_mode mode)
  379. {
  380. struct sx150x_chip *chip = gpiochip_get_data(gc);
  381. /* On the SX160X 789 we can set open drain */
  382. if (chip->dev_cfg->model != SX150X_789)
  383. return -ENOTSUPP;
  384. if (mode == LINE_MODE_PUSH_PULL)
  385. return sx150x_write_cfg(chip,
  386. offset,
  387. 1,
  388. chip->dev_cfg->pri.x789.reg_drain,
  389. 0);
  390. if (mode == LINE_MODE_OPEN_DRAIN)
  391. return sx150x_write_cfg(chip,
  392. offset,
  393. 1,
  394. chip->dev_cfg->pri.x789.reg_drain,
  395. 1);
  396. return -ENOTSUPP;
  397. }
  398. static int sx150x_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
  399. {
  400. struct sx150x_chip *chip = gpiochip_get_data(gc);
  401. int status = -EINVAL;
  402. if (!offset_is_oscio(chip, offset)) {
  403. mutex_lock(&chip->lock);
  404. status = sx150x_io_input(chip, offset);
  405. mutex_unlock(&chip->lock);
  406. }
  407. return status;
  408. }
  409. static int sx150x_gpio_direction_output(struct gpio_chip *gc,
  410. unsigned offset,
  411. int val)
  412. {
  413. struct sx150x_chip *chip = gpiochip_get_data(gc);
  414. int status = 0;
  415. if (!offset_is_oscio(chip, offset)) {
  416. mutex_lock(&chip->lock);
  417. status = sx150x_io_output(chip, offset, val);
  418. mutex_unlock(&chip->lock);
  419. }
  420. return status;
  421. }
  422. static void sx150x_irq_mask(struct irq_data *d)
  423. {
  424. struct sx150x_chip *chip = gpiochip_get_data(irq_data_get_irq_chip_data(d));
  425. unsigned n = d->hwirq;
  426. chip->irq_masked |= (1 << n);
  427. chip->irq_update = n;
  428. }
  429. static void sx150x_irq_unmask(struct irq_data *d)
  430. {
  431. struct sx150x_chip *chip = gpiochip_get_data(irq_data_get_irq_chip_data(d));
  432. unsigned n = d->hwirq;
  433. chip->irq_masked &= ~(1 << n);
  434. chip->irq_update = n;
  435. }
  436. static int sx150x_irq_set_type(struct irq_data *d, unsigned int flow_type)
  437. {
  438. struct sx150x_chip *chip = gpiochip_get_data(irq_data_get_irq_chip_data(d));
  439. unsigned n, val = 0;
  440. if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
  441. return -EINVAL;
  442. n = d->hwirq;
  443. if (flow_type & IRQ_TYPE_EDGE_RISING)
  444. val |= 0x1;
  445. if (flow_type & IRQ_TYPE_EDGE_FALLING)
  446. val |= 0x2;
  447. chip->irq_sense &= ~(3UL << (n * 2));
  448. chip->irq_sense |= val << (n * 2);
  449. chip->irq_update = n;
  450. return 0;
  451. }
  452. static irqreturn_t sx150x_irq_thread_fn(int irq, void *dev_id)
  453. {
  454. struct sx150x_chip *chip = (struct sx150x_chip *)dev_id;
  455. unsigned nhandled = 0;
  456. unsigned sub_irq;
  457. unsigned n;
  458. s32 err;
  459. u8 val;
  460. int i;
  461. for (i = (chip->dev_cfg->ngpios / 8) - 1; i >= 0; --i) {
  462. err = sx150x_i2c_read(chip->client,
  463. chip->dev_cfg->reg_irq_src - i,
  464. &val);
  465. if (err < 0)
  466. continue;
  467. sx150x_i2c_write(chip->client,
  468. chip->dev_cfg->reg_irq_src - i,
  469. val);
  470. for (n = 0; n < 8; ++n) {
  471. if (val & (1 << n)) {
  472. sub_irq = irq_find_mapping(
  473. chip->gpio_chip.irqdomain,
  474. (i * 8) + n);
  475. handle_nested_irq(sub_irq);
  476. ++nhandled;
  477. }
  478. }
  479. }
  480. return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
  481. }
  482. static void sx150x_irq_bus_lock(struct irq_data *d)
  483. {
  484. struct sx150x_chip *chip = gpiochip_get_data(irq_data_get_irq_chip_data(d));
  485. mutex_lock(&chip->lock);
  486. }
  487. static void sx150x_irq_bus_sync_unlock(struct irq_data *d)
  488. {
  489. struct sx150x_chip *chip = gpiochip_get_data(irq_data_get_irq_chip_data(d));
  490. unsigned n;
  491. if (chip->irq_update == NO_UPDATE_PENDING)
  492. goto out;
  493. n = chip->irq_update;
  494. chip->irq_update = NO_UPDATE_PENDING;
  495. /* Avoid updates if nothing changed */
  496. if (chip->dev_sense == chip->irq_sense &&
  497. chip->dev_masked == chip->irq_masked)
  498. goto out;
  499. chip->dev_sense = chip->irq_sense;
  500. chip->dev_masked = chip->irq_masked;
  501. if (chip->irq_masked & (1 << n)) {
  502. sx150x_write_cfg(chip, n, 1, chip->dev_cfg->reg_irq_mask, 1);
  503. sx150x_write_cfg(chip, n, 2, chip->dev_cfg->reg_sense, 0);
  504. } else {
  505. sx150x_write_cfg(chip, n, 1, chip->dev_cfg->reg_irq_mask, 0);
  506. sx150x_write_cfg(chip, n, 2, chip->dev_cfg->reg_sense,
  507. chip->irq_sense >> (n * 2));
  508. }
  509. out:
  510. mutex_unlock(&chip->lock);
  511. }
  512. static void sx150x_init_chip(struct sx150x_chip *chip,
  513. struct i2c_client *client,
  514. kernel_ulong_t driver_data,
  515. struct sx150x_platform_data *pdata)
  516. {
  517. mutex_init(&chip->lock);
  518. chip->client = client;
  519. chip->dev_cfg = &sx150x_devices[driver_data];
  520. chip->gpio_chip.parent = &client->dev;
  521. chip->gpio_chip.label = client->name;
  522. chip->gpio_chip.direction_input = sx150x_gpio_direction_input;
  523. chip->gpio_chip.direction_output = sx150x_gpio_direction_output;
  524. chip->gpio_chip.get = sx150x_gpio_get;
  525. chip->gpio_chip.set = sx150x_gpio_set;
  526. chip->gpio_chip.set_single_ended = sx150x_gpio_set_single_ended;
  527. chip->gpio_chip.base = pdata->gpio_base;
  528. chip->gpio_chip.can_sleep = true;
  529. chip->gpio_chip.ngpio = chip->dev_cfg->ngpios;
  530. #ifdef CONFIG_OF_GPIO
  531. chip->gpio_chip.of_node = client->dev.of_node;
  532. chip->gpio_chip.of_gpio_n_cells = 2;
  533. #endif
  534. if (pdata->oscio_is_gpo)
  535. ++chip->gpio_chip.ngpio;
  536. chip->irq_chip.name = client->name;
  537. chip->irq_chip.irq_mask = sx150x_irq_mask;
  538. chip->irq_chip.irq_unmask = sx150x_irq_unmask;
  539. chip->irq_chip.irq_set_type = sx150x_irq_set_type;
  540. chip->irq_chip.irq_bus_lock = sx150x_irq_bus_lock;
  541. chip->irq_chip.irq_bus_sync_unlock = sx150x_irq_bus_sync_unlock;
  542. chip->irq_summary = -1;
  543. chip->irq_base = -1;
  544. chip->irq_masked = ~0;
  545. chip->irq_sense = 0;
  546. chip->dev_masked = ~0;
  547. chip->dev_sense = 0;
  548. chip->irq_update = NO_UPDATE_PENDING;
  549. }
  550. static int sx150x_init_io(struct sx150x_chip *chip, u8 base, u16 cfg)
  551. {
  552. int err = 0;
  553. unsigned n;
  554. for (n = 0; err >= 0 && n < (chip->dev_cfg->ngpios / 8); ++n)
  555. err = sx150x_i2c_write(chip->client, base - n, cfg >> (n * 8));
  556. return err;
  557. }
  558. static int sx150x_reset(struct sx150x_chip *chip)
  559. {
  560. int err;
  561. err = i2c_smbus_write_byte_data(chip->client,
  562. chip->dev_cfg->pri.x789.reg_reset,
  563. 0x12);
  564. if (err < 0)
  565. return err;
  566. err = i2c_smbus_write_byte_data(chip->client,
  567. chip->dev_cfg->pri.x789.reg_reset,
  568. 0x34);
  569. return err;
  570. }
  571. static int sx150x_init_hw(struct sx150x_chip *chip,
  572. struct sx150x_platform_data *pdata)
  573. {
  574. int err = 0;
  575. if (pdata->reset_during_probe) {
  576. err = sx150x_reset(chip);
  577. if (err < 0)
  578. return err;
  579. }
  580. if (chip->dev_cfg->model == SX150X_789)
  581. err = sx150x_i2c_write(chip->client,
  582. chip->dev_cfg->pri.x789.reg_misc,
  583. 0x01);
  584. else if (chip->dev_cfg->model == SX150X_456)
  585. err = sx150x_i2c_write(chip->client,
  586. chip->dev_cfg->pri.x456.reg_advance,
  587. 0x04);
  588. else
  589. err = sx150x_i2c_write(chip->client,
  590. chip->dev_cfg->pri.x123.reg_advance,
  591. 0x00);
  592. if (err < 0)
  593. return err;
  594. err = sx150x_init_io(chip, chip->dev_cfg->reg_pullup,
  595. pdata->io_pullup_ena);
  596. if (err < 0)
  597. return err;
  598. err = sx150x_init_io(chip, chip->dev_cfg->reg_pulldn,
  599. pdata->io_pulldn_ena);
  600. if (err < 0)
  601. return err;
  602. if (chip->dev_cfg->model == SX150X_789) {
  603. err = sx150x_init_io(chip,
  604. chip->dev_cfg->pri.x789.reg_polarity,
  605. pdata->io_polarity);
  606. if (err < 0)
  607. return err;
  608. } else if (chip->dev_cfg->model == SX150X_456) {
  609. /* Set all pins to work in normal mode */
  610. err = sx150x_init_io(chip,
  611. chip->dev_cfg->pri.x456.reg_pld_mode,
  612. 0);
  613. if (err < 0)
  614. return err;
  615. } else {
  616. /* Set all pins to work in normal mode */
  617. err = sx150x_init_io(chip,
  618. chip->dev_cfg->pri.x123.reg_pld_mode,
  619. 0);
  620. if (err < 0)
  621. return err;
  622. }
  623. if (pdata->oscio_is_gpo)
  624. sx150x_set_oscio(chip, 0);
  625. return err;
  626. }
  627. static int sx150x_install_irq_chip(struct sx150x_chip *chip,
  628. int irq_summary,
  629. int irq_base)
  630. {
  631. int err;
  632. chip->irq_summary = irq_summary;
  633. chip->irq_base = irq_base;
  634. /* Add gpio chip to irq subsystem */
  635. err = gpiochip_irqchip_add(&chip->gpio_chip,
  636. &chip->irq_chip, chip->irq_base,
  637. handle_edge_irq, IRQ_TYPE_EDGE_BOTH);
  638. if (err) {
  639. dev_err(&chip->client->dev,
  640. "could not connect irqchip to gpiochip\n");
  641. return err;
  642. }
  643. err = devm_request_threaded_irq(&chip->client->dev,
  644. irq_summary, NULL, sx150x_irq_thread_fn,
  645. IRQF_ONESHOT | IRQF_SHARED | IRQF_TRIGGER_FALLING,
  646. chip->irq_chip.name, chip);
  647. if (err < 0) {
  648. chip->irq_summary = -1;
  649. chip->irq_base = -1;
  650. }
  651. return err;
  652. }
  653. static int sx150x_probe(struct i2c_client *client,
  654. const struct i2c_device_id *id)
  655. {
  656. static const u32 i2c_funcs = I2C_FUNC_SMBUS_BYTE_DATA |
  657. I2C_FUNC_SMBUS_WRITE_WORD_DATA;
  658. struct sx150x_platform_data *pdata;
  659. struct sx150x_chip *chip;
  660. int rc;
  661. pdata = dev_get_platdata(&client->dev);
  662. if (!pdata)
  663. return -EINVAL;
  664. if (!i2c_check_functionality(client->adapter, i2c_funcs))
  665. return -ENOSYS;
  666. chip = devm_kzalloc(&client->dev,
  667. sizeof(struct sx150x_chip), GFP_KERNEL);
  668. if (!chip)
  669. return -ENOMEM;
  670. sx150x_init_chip(chip, client, id->driver_data, pdata);
  671. rc = sx150x_init_hw(chip, pdata);
  672. if (rc < 0)
  673. return rc;
  674. rc = devm_gpiochip_add_data(&client->dev, &chip->gpio_chip, chip);
  675. if (rc)
  676. return rc;
  677. if (pdata->irq_summary >= 0) {
  678. rc = sx150x_install_irq_chip(chip,
  679. pdata->irq_summary,
  680. pdata->irq_base);
  681. if (rc < 0)
  682. return rc;
  683. }
  684. i2c_set_clientdata(client, chip);
  685. return 0;
  686. }
  687. static struct i2c_driver sx150x_driver = {
  688. .driver = {
  689. .name = "sx150x",
  690. .of_match_table = of_match_ptr(sx150x_of_match),
  691. },
  692. .probe = sx150x_probe,
  693. .id_table = sx150x_id,
  694. };
  695. static int __init sx150x_init(void)
  696. {
  697. return i2c_add_driver(&sx150x_driver);
  698. }
  699. subsys_initcall(sx150x_init);