/drivers/gpio/gpio-sx150x.c
C | 794 lines | 614 code | 95 blank | 85 comment | 64 complexity | 65f922d02b6ba21d4027a70a73cc90ef MD5 | raw file
1/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. 2 * 3 * Driver for Semtech SX150X I2C GPIO Expanders 4 * 5 * Author: Gregory Bean <gbean@codeaurora.org> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 and 9 * only version 2 as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 19 * 02110-1301, USA. 20 */ 21#include <linux/gpio.h> 22#include <linux/i2c.h> 23#include <linux/init.h> 24#include <linux/interrupt.h> 25#include <linux/irq.h> 26#include <linux/mutex.h> 27#include <linux/slab.h> 28#include <linux/of.h> 29#include <linux/of_address.h> 30#include <linux/of_irq.h> 31#include <linux/of_gpio.h> 32#include <linux/of_device.h> 33 34#define NO_UPDATE_PENDING -1 35 36/* The chip models of sx150x */ 37#define SX150X_123 0 38#define SX150X_456 1 39#define SX150X_789 2 40 41struct sx150x_123_pri { 42 u8 reg_pld_mode; 43 u8 reg_pld_table0; 44 u8 reg_pld_table1; 45 u8 reg_pld_table2; 46 u8 reg_pld_table3; 47 u8 reg_pld_table4; 48 u8 reg_advance; 49}; 50 51struct sx150x_456_pri { 52 u8 reg_pld_mode; 53 u8 reg_pld_table0; 54 u8 reg_pld_table1; 55 u8 reg_pld_table2; 56 u8 reg_pld_table3; 57 u8 reg_pld_table4; 58 u8 reg_advance; 59}; 60 61struct sx150x_789_pri { 62 u8 reg_drain; 63 u8 reg_polarity; 64 u8 reg_clock; 65 u8 reg_misc; 66 u8 reg_reset; 67 u8 ngpios; 68}; 69 70struct sx150x_device_data { 71 u8 model; 72 u8 reg_pullup; 73 u8 reg_pulldn; 74 u8 reg_dir; 75 u8 reg_data; 76 u8 reg_irq_mask; 77 u8 reg_irq_src; 78 u8 reg_sense; 79 u8 ngpios; 80 union { 81 struct sx150x_123_pri x123; 82 struct sx150x_456_pri x456; 83 struct sx150x_789_pri x789; 84 } pri; 85}; 86 87/** 88 * struct sx150x_platform_data - config data for SX150x driver 89 * @gpio_base: The index number of the first GPIO assigned to this 90 * GPIO expander. The expander will create a block of 91 * consecutively numbered gpios beginning at the given base, 92 * with the size of the block depending on the model of the 93 * expander chip. 94 * @oscio_is_gpo: If set to true, the driver will configure OSCIO as a GPO 95 * instead of as an oscillator, increasing the size of the 96 * GP(I)O pool created by this expander by one. The 97 * output-only GPO pin will be added at the end of the block. 98 * @io_pullup_ena: A bit-mask which enables or disables the pull-up resistor 99 * for each IO line in the expander. Setting the bit at 100 * position n will enable the pull-up for the IO at 101 * the corresponding offset. For chips with fewer than 102 * 16 IO pins, high-end bits are ignored. 103 * @io_pulldn_ena: A bit-mask which enables-or disables the pull-down 104 * resistor for each IO line in the expander. Setting the 105 * bit at position n will enable the pull-down for the IO at 106 * the corresponding offset. For chips with fewer than 107 * 16 IO pins, high-end bits are ignored. 108 * @io_polarity: A bit-mask which enables polarity inversion for each IO line 109 * in the expander. Setting the bit at position n inverts 110 * the polarity of that IO line, while clearing it results 111 * in normal polarity. For chips with fewer than 16 IO pins, 112 * high-end bits are ignored. 113 * @irq_summary: The 'summary IRQ' line to which the GPIO expander's INT line 114 * is connected, via which it reports interrupt events 115 * across all GPIO lines. This must be a real, 116 * pre-existing IRQ line. 117 * Setting this value < 0 disables the irq_chip functionality 118 * of the driver. 119 * @irq_base: The first 'virtual IRQ' line at which our block of GPIO-based 120 * IRQ lines will appear. Similarly to gpio_base, the expander 121 * will create a block of irqs beginning at this number. 122 * This value is ignored if irq_summary is < 0. 123 * @reset_during_probe: If set to true, the driver will trigger a full 124 * reset of the chip at the beginning of the probe 125 * in order to place it in a known state. 126 */ 127struct sx150x_platform_data { 128 unsigned gpio_base; 129 bool oscio_is_gpo; 130 u16 io_pullup_ena; 131 u16 io_pulldn_ena; 132 u16 io_polarity; 133 int irq_summary; 134 unsigned irq_base; 135 bool reset_during_probe; 136}; 137 138struct sx150x_chip { 139 struct gpio_chip gpio_chip; 140 struct i2c_client *client; 141 const struct sx150x_device_data *dev_cfg; 142 int irq_summary; 143 int irq_base; 144 int irq_update; 145 u32 irq_sense; 146 u32 irq_masked; 147 u32 dev_sense; 148 u32 dev_masked; 149 struct irq_chip irq_chip; 150 struct mutex lock; 151}; 152 153static const struct sx150x_device_data sx150x_devices[] = { 154 [0] = { /* sx1508q */ 155 .model = SX150X_789, 156 .reg_pullup = 0x03, 157 .reg_pulldn = 0x04, 158 .reg_dir = 0x07, 159 .reg_data = 0x08, 160 .reg_irq_mask = 0x09, 161 .reg_irq_src = 0x0c, 162 .reg_sense = 0x0b, 163 .pri.x789 = { 164 .reg_drain = 0x05, 165 .reg_polarity = 0x06, 166 .reg_clock = 0x0f, 167 .reg_misc = 0x10, 168 .reg_reset = 0x7d, 169 }, 170 .ngpios = 8, 171 }, 172 [1] = { /* sx1509q */ 173 .model = SX150X_789, 174 .reg_pullup = 0x07, 175 .reg_pulldn = 0x09, 176 .reg_dir = 0x0f, 177 .reg_data = 0x11, 178 .reg_irq_mask = 0x13, 179 .reg_irq_src = 0x19, 180 .reg_sense = 0x17, 181 .pri.x789 = { 182 .reg_drain = 0x0b, 183 .reg_polarity = 0x0d, 184 .reg_clock = 0x1e, 185 .reg_misc = 0x1f, 186 .reg_reset = 0x7d, 187 }, 188 .ngpios = 16 189 }, 190 [2] = { /* sx1506q */ 191 .model = SX150X_456, 192 .reg_pullup = 0x05, 193 .reg_pulldn = 0x07, 194 .reg_dir = 0x03, 195 .reg_data = 0x01, 196 .reg_irq_mask = 0x09, 197 .reg_irq_src = 0x0f, 198 .reg_sense = 0x0d, 199 .pri.x456 = { 200 .reg_pld_mode = 0x21, 201 .reg_pld_table0 = 0x23, 202 .reg_pld_table1 = 0x25, 203 .reg_pld_table2 = 0x27, 204 .reg_pld_table3 = 0x29, 205 .reg_pld_table4 = 0x2b, 206 .reg_advance = 0xad, 207 }, 208 .ngpios = 16 209 }, 210 [3] = { /* sx1502q */ 211 .model = SX150X_123, 212 .reg_pullup = 0x02, 213 .reg_pulldn = 0x03, 214 .reg_dir = 0x01, 215 .reg_data = 0x00, 216 .reg_irq_mask = 0x05, 217 .reg_irq_src = 0x08, 218 .reg_sense = 0x07, 219 .pri.x123 = { 220 .reg_pld_mode = 0x10, 221 .reg_pld_table0 = 0x11, 222 .reg_pld_table1 = 0x12, 223 .reg_pld_table2 = 0x13, 224 .reg_pld_table3 = 0x14, 225 .reg_pld_table4 = 0x15, 226 .reg_advance = 0xad, 227 }, 228 .ngpios = 8, 229 }, 230}; 231 232static const struct i2c_device_id sx150x_id[] = { 233 {"sx1508q", 0}, 234 {"sx1509q", 1}, 235 {"sx1506q", 2}, 236 {"sx1502q", 3}, 237 {} 238}; 239MODULE_DEVICE_TABLE(i2c, sx150x_id); 240 241static const struct of_device_id sx150x_of_match[] = { 242 { .compatible = "semtech,sx1508q" }, 243 { .compatible = "semtech,sx1509q" }, 244 { .compatible = "semtech,sx1506q" }, 245 { .compatible = "semtech,sx1502q" }, 246 {}, 247}; 248MODULE_DEVICE_TABLE(of, sx150x_of_match); 249 250static s32 sx150x_i2c_write(struct i2c_client *client, u8 reg, u8 val) 251{ 252 s32 err = i2c_smbus_write_byte_data(client, reg, val); 253 254 if (err < 0) 255 dev_warn(&client->dev, 256 "i2c write fail: can't write %02x to %02x: %d\n", 257 val, reg, err); 258 return err; 259} 260 261static s32 sx150x_i2c_read(struct i2c_client *client, u8 reg, u8 *val) 262{ 263 s32 err = i2c_smbus_read_byte_data(client, reg); 264 265 if (err >= 0) 266 *val = err; 267 else 268 dev_warn(&client->dev, 269 "i2c read fail: can't read from %02x: %d\n", 270 reg, err); 271 return err; 272} 273 274static inline bool offset_is_oscio(struct sx150x_chip *chip, unsigned offset) 275{ 276 return (chip->dev_cfg->ngpios == offset); 277} 278 279/* 280 * These utility functions solve the common problem of locating and setting 281 * configuration bits. Configuration bits are grouped into registers 282 * whose indexes increase downwards. For example, with eight-bit registers, 283 * sixteen gpios would have their config bits grouped in the following order: 284 * REGISTER N-1 [ f e d c b a 9 8 ] 285 * N [ 7 6 5 4 3 2 1 0 ] 286 * 287 * For multi-bit configurations, the pattern gets wider: 288 * REGISTER N-3 [ f f e e d d c c ] 289 * N-2 [ b b a a 9 9 8 8 ] 290 * N-1 [ 7 7 6 6 5 5 4 4 ] 291 * N [ 3 3 2 2 1 1 0 0 ] 292 * 293 * Given the address of the starting register 'N', the index of the gpio 294 * whose configuration we seek to change, and the width in bits of that 295 * configuration, these functions allow us to locate the correct 296 * register and mask the correct bits. 297 */ 298static inline void sx150x_find_cfg(u8 offset, u8 width, 299 u8 *reg, u8 *mask, u8 *shift) 300{ 301 *reg -= offset * width / 8; 302 *mask = (1 << width) - 1; 303 *shift = (offset * width) % 8; 304 *mask <<= *shift; 305} 306 307static s32 sx150x_write_cfg(struct sx150x_chip *chip, 308 u8 offset, u8 width, u8 reg, u8 val) 309{ 310 u8 mask; 311 u8 data; 312 u8 shift; 313 s32 err; 314 315 sx150x_find_cfg(offset, width, ®, &mask, &shift); 316 err = sx150x_i2c_read(chip->client, reg, &data); 317 if (err < 0) 318 return err; 319 320 data &= ~mask; 321 data |= (val << shift) & mask; 322 return sx150x_i2c_write(chip->client, reg, data); 323} 324 325static int sx150x_get_io(struct sx150x_chip *chip, unsigned offset) 326{ 327 u8 reg = chip->dev_cfg->reg_data; 328 u8 mask; 329 u8 data; 330 u8 shift; 331 s32 err; 332 333 sx150x_find_cfg(offset, 1, ®, &mask, &shift); 334 err = sx150x_i2c_read(chip->client, reg, &data); 335 if (err >= 0) 336 err = (data & mask) != 0 ? 1 : 0; 337 338 return err; 339} 340 341static void sx150x_set_oscio(struct sx150x_chip *chip, int val) 342{ 343 sx150x_i2c_write(chip->client, 344 chip->dev_cfg->pri.x789.reg_clock, 345 (val ? 0x1f : 0x10)); 346} 347 348static void sx150x_set_io(struct sx150x_chip *chip, unsigned offset, int val) 349{ 350 sx150x_write_cfg(chip, 351 offset, 352 1, 353 chip->dev_cfg->reg_data, 354 (val ? 1 : 0)); 355} 356 357static int sx150x_io_input(struct sx150x_chip *chip, unsigned offset) 358{ 359 return sx150x_write_cfg(chip, 360 offset, 361 1, 362 chip->dev_cfg->reg_dir, 363 1); 364} 365 366static int sx150x_io_output(struct sx150x_chip *chip, unsigned offset, int val) 367{ 368 int err; 369 370 err = sx150x_write_cfg(chip, 371 offset, 372 1, 373 chip->dev_cfg->reg_data, 374 (val ? 1 : 0)); 375 if (err >= 0) 376 err = sx150x_write_cfg(chip, 377 offset, 378 1, 379 chip->dev_cfg->reg_dir, 380 0); 381 return err; 382} 383 384static int sx150x_gpio_get(struct gpio_chip *gc, unsigned offset) 385{ 386 struct sx150x_chip *chip = gpiochip_get_data(gc); 387 int status = -EINVAL; 388 389 if (!offset_is_oscio(chip, offset)) { 390 mutex_lock(&chip->lock); 391 status = sx150x_get_io(chip, offset); 392 mutex_unlock(&chip->lock); 393 } 394 395 return (status < 0) ? status : !!status; 396} 397 398static void sx150x_gpio_set(struct gpio_chip *gc, unsigned offset, int val) 399{ 400 struct sx150x_chip *chip = gpiochip_get_data(gc); 401 402 mutex_lock(&chip->lock); 403 if (offset_is_oscio(chip, offset)) 404 sx150x_set_oscio(chip, val); 405 else 406 sx150x_set_io(chip, offset, val); 407 mutex_unlock(&chip->lock); 408} 409 410static int sx150x_gpio_set_single_ended(struct gpio_chip *gc, 411 unsigned offset, 412 enum single_ended_mode mode) 413{ 414 struct sx150x_chip *chip = gpiochip_get_data(gc); 415 416 /* On the SX160X 789 we can set open drain */ 417 if (chip->dev_cfg->model != SX150X_789) 418 return -ENOTSUPP; 419 420 if (mode == LINE_MODE_PUSH_PULL) 421 return sx150x_write_cfg(chip, 422 offset, 423 1, 424 chip->dev_cfg->pri.x789.reg_drain, 425 0); 426 427 if (mode == LINE_MODE_OPEN_DRAIN) 428 return sx150x_write_cfg(chip, 429 offset, 430 1, 431 chip->dev_cfg->pri.x789.reg_drain, 432 1); 433 return -ENOTSUPP; 434} 435 436static int sx150x_gpio_direction_input(struct gpio_chip *gc, unsigned offset) 437{ 438 struct sx150x_chip *chip = gpiochip_get_data(gc); 439 int status = -EINVAL; 440 441 if (!offset_is_oscio(chip, offset)) { 442 mutex_lock(&chip->lock); 443 status = sx150x_io_input(chip, offset); 444 mutex_unlock(&chip->lock); 445 } 446 return status; 447} 448 449static int sx150x_gpio_direction_output(struct gpio_chip *gc, 450 unsigned offset, 451 int val) 452{ 453 struct sx150x_chip *chip = gpiochip_get_data(gc); 454 int status = 0; 455 456 if (!offset_is_oscio(chip, offset)) { 457 mutex_lock(&chip->lock); 458 status = sx150x_io_output(chip, offset, val); 459 mutex_unlock(&chip->lock); 460 } 461 return status; 462} 463 464static void sx150x_irq_mask(struct irq_data *d) 465{ 466 struct sx150x_chip *chip = gpiochip_get_data(irq_data_get_irq_chip_data(d)); 467 unsigned n = d->hwirq; 468 469 chip->irq_masked |= (1 << n); 470 chip->irq_update = n; 471} 472 473static void sx150x_irq_unmask(struct irq_data *d) 474{ 475 struct sx150x_chip *chip = gpiochip_get_data(irq_data_get_irq_chip_data(d)); 476 unsigned n = d->hwirq; 477 478 chip->irq_masked &= ~(1 << n); 479 chip->irq_update = n; 480} 481 482static int sx150x_irq_set_type(struct irq_data *d, unsigned int flow_type) 483{ 484 struct sx150x_chip *chip = gpiochip_get_data(irq_data_get_irq_chip_data(d)); 485 unsigned n, val = 0; 486 487 if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) 488 return -EINVAL; 489 490 n = d->hwirq; 491 492 if (flow_type & IRQ_TYPE_EDGE_RISING) 493 val |= 0x1; 494 if (flow_type & IRQ_TYPE_EDGE_FALLING) 495 val |= 0x2; 496 497 chip->irq_sense &= ~(3UL << (n * 2)); 498 chip->irq_sense |= val << (n * 2); 499 chip->irq_update = n; 500 return 0; 501} 502 503static irqreturn_t sx150x_irq_thread_fn(int irq, void *dev_id) 504{ 505 struct sx150x_chip *chip = (struct sx150x_chip *)dev_id; 506 unsigned nhandled = 0; 507 unsigned sub_irq; 508 unsigned n; 509 s32 err; 510 u8 val; 511 int i; 512 513 for (i = (chip->dev_cfg->ngpios / 8) - 1; i >= 0; --i) { 514 err = sx150x_i2c_read(chip->client, 515 chip->dev_cfg->reg_irq_src - i, 516 &val); 517 if (err < 0) 518 continue; 519 520 sx150x_i2c_write(chip->client, 521 chip->dev_cfg->reg_irq_src - i, 522 val); 523 for (n = 0; n < 8; ++n) { 524 if (val & (1 << n)) { 525 sub_irq = irq_find_mapping( 526 chip->gpio_chip.irqdomain, 527 (i * 8) + n); 528 handle_nested_irq(sub_irq); 529 ++nhandled; 530 } 531 } 532 } 533 534 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 535} 536 537static void sx150x_irq_bus_lock(struct irq_data *d) 538{ 539 struct sx150x_chip *chip = gpiochip_get_data(irq_data_get_irq_chip_data(d)); 540 541 mutex_lock(&chip->lock); 542} 543 544static void sx150x_irq_bus_sync_unlock(struct irq_data *d) 545{ 546 struct sx150x_chip *chip = gpiochip_get_data(irq_data_get_irq_chip_data(d)); 547 unsigned n; 548 549 if (chip->irq_update == NO_UPDATE_PENDING) 550 goto out; 551 552 n = chip->irq_update; 553 chip->irq_update = NO_UPDATE_PENDING; 554 555 /* Avoid updates if nothing changed */ 556 if (chip->dev_sense == chip->irq_sense && 557 chip->dev_masked == chip->irq_masked) 558 goto out; 559 560 chip->dev_sense = chip->irq_sense; 561 chip->dev_masked = chip->irq_masked; 562 563 if (chip->irq_masked & (1 << n)) { 564 sx150x_write_cfg(chip, n, 1, chip->dev_cfg->reg_irq_mask, 1); 565 sx150x_write_cfg(chip, n, 2, chip->dev_cfg->reg_sense, 0); 566 } else { 567 sx150x_write_cfg(chip, n, 1, chip->dev_cfg->reg_irq_mask, 0); 568 sx150x_write_cfg(chip, n, 2, chip->dev_cfg->reg_sense, 569 chip->irq_sense >> (n * 2)); 570 } 571out: 572 mutex_unlock(&chip->lock); 573} 574 575static void sx150x_init_chip(struct sx150x_chip *chip, 576 struct i2c_client *client, 577 kernel_ulong_t driver_data, 578 struct sx150x_platform_data *pdata) 579{ 580 mutex_init(&chip->lock); 581 582 chip->client = client; 583 chip->dev_cfg = &sx150x_devices[driver_data]; 584 chip->gpio_chip.parent = &client->dev; 585 chip->gpio_chip.label = client->name; 586 chip->gpio_chip.direction_input = sx150x_gpio_direction_input; 587 chip->gpio_chip.direction_output = sx150x_gpio_direction_output; 588 chip->gpio_chip.get = sx150x_gpio_get; 589 chip->gpio_chip.set = sx150x_gpio_set; 590 chip->gpio_chip.set_single_ended = sx150x_gpio_set_single_ended; 591 chip->gpio_chip.base = pdata->gpio_base; 592 chip->gpio_chip.can_sleep = true; 593 chip->gpio_chip.ngpio = chip->dev_cfg->ngpios; 594#ifdef CONFIG_OF_GPIO 595 chip->gpio_chip.of_node = client->dev.of_node; 596 chip->gpio_chip.of_gpio_n_cells = 2; 597#endif 598 if (pdata->oscio_is_gpo) 599 ++chip->gpio_chip.ngpio; 600 601 chip->irq_chip.name = client->name; 602 chip->irq_chip.irq_mask = sx150x_irq_mask; 603 chip->irq_chip.irq_unmask = sx150x_irq_unmask; 604 chip->irq_chip.irq_set_type = sx150x_irq_set_type; 605 chip->irq_chip.irq_bus_lock = sx150x_irq_bus_lock; 606 chip->irq_chip.irq_bus_sync_unlock = sx150x_irq_bus_sync_unlock; 607 chip->irq_summary = -1; 608 chip->irq_base = -1; 609 chip->irq_masked = ~0; 610 chip->irq_sense = 0; 611 chip->dev_masked = ~0; 612 chip->dev_sense = 0; 613 chip->irq_update = NO_UPDATE_PENDING; 614} 615 616static int sx150x_init_io(struct sx150x_chip *chip, u8 base, u16 cfg) 617{ 618 int err = 0; 619 unsigned n; 620 621 for (n = 0; err >= 0 && n < (chip->dev_cfg->ngpios / 8); ++n) 622 err = sx150x_i2c_write(chip->client, base - n, cfg >> (n * 8)); 623 return err; 624} 625 626static int sx150x_reset(struct sx150x_chip *chip) 627{ 628 int err; 629 630 err = i2c_smbus_write_byte_data(chip->client, 631 chip->dev_cfg->pri.x789.reg_reset, 632 0x12); 633 if (err < 0) 634 return err; 635 636 err = i2c_smbus_write_byte_data(chip->client, 637 chip->dev_cfg->pri.x789.reg_reset, 638 0x34); 639 return err; 640} 641 642static int sx150x_init_hw(struct sx150x_chip *chip, 643 struct sx150x_platform_data *pdata) 644{ 645 int err = 0; 646 647 if (pdata->reset_during_probe) { 648 err = sx150x_reset(chip); 649 if (err < 0) 650 return err; 651 } 652 653 if (chip->dev_cfg->model == SX150X_789) 654 err = sx150x_i2c_write(chip->client, 655 chip->dev_cfg->pri.x789.reg_misc, 656 0x01); 657 else if (chip->dev_cfg->model == SX150X_456) 658 err = sx150x_i2c_write(chip->client, 659 chip->dev_cfg->pri.x456.reg_advance, 660 0x04); 661 else 662 err = sx150x_i2c_write(chip->client, 663 chip->dev_cfg->pri.x123.reg_advance, 664 0x00); 665 if (err < 0) 666 return err; 667 668 err = sx150x_init_io(chip, chip->dev_cfg->reg_pullup, 669 pdata->io_pullup_ena); 670 if (err < 0) 671 return err; 672 673 err = sx150x_init_io(chip, chip->dev_cfg->reg_pulldn, 674 pdata->io_pulldn_ena); 675 if (err < 0) 676 return err; 677 678 if (chip->dev_cfg->model == SX150X_789) { 679 err = sx150x_init_io(chip, 680 chip->dev_cfg->pri.x789.reg_polarity, 681 pdata->io_polarity); 682 if (err < 0) 683 return err; 684 } else if (chip->dev_cfg->model == SX150X_456) { 685 /* Set all pins to work in normal mode */ 686 err = sx150x_init_io(chip, 687 chip->dev_cfg->pri.x456.reg_pld_mode, 688 0); 689 if (err < 0) 690 return err; 691 } else { 692 /* Set all pins to work in normal mode */ 693 err = sx150x_init_io(chip, 694 chip->dev_cfg->pri.x123.reg_pld_mode, 695 0); 696 if (err < 0) 697 return err; 698 } 699 700 701 if (pdata->oscio_is_gpo) 702 sx150x_set_oscio(chip, 0); 703 704 return err; 705} 706 707static int sx150x_install_irq_chip(struct sx150x_chip *chip, 708 int irq_summary, 709 int irq_base) 710{ 711 int err; 712 713 chip->irq_summary = irq_summary; 714 chip->irq_base = irq_base; 715 716 /* Add gpio chip to irq subsystem */ 717 err = gpiochip_irqchip_add(&chip->gpio_chip, 718 &chip->irq_chip, chip->irq_base, 719 handle_edge_irq, IRQ_TYPE_EDGE_BOTH); 720 if (err) { 721 dev_err(&chip->client->dev, 722 "could not connect irqchip to gpiochip\n"); 723 return err; 724 } 725 726 err = devm_request_threaded_irq(&chip->client->dev, 727 irq_summary, NULL, sx150x_irq_thread_fn, 728 IRQF_ONESHOT | IRQF_SHARED | IRQF_TRIGGER_FALLING, 729 chip->irq_chip.name, chip); 730 if (err < 0) { 731 chip->irq_summary = -1; 732 chip->irq_base = -1; 733 } 734 735 return err; 736} 737 738static int sx150x_probe(struct i2c_client *client, 739 const struct i2c_device_id *id) 740{ 741 static const u32 i2c_funcs = I2C_FUNC_SMBUS_BYTE_DATA | 742 I2C_FUNC_SMBUS_WRITE_WORD_DATA; 743 struct sx150x_platform_data *pdata; 744 struct sx150x_chip *chip; 745 int rc; 746 747 pdata = dev_get_platdata(&client->dev); 748 if (!pdata) 749 return -EINVAL; 750 751 if (!i2c_check_functionality(client->adapter, i2c_funcs)) 752 return -ENOSYS; 753 754 chip = devm_kzalloc(&client->dev, 755 sizeof(struct sx150x_chip), GFP_KERNEL); 756 if (!chip) 757 return -ENOMEM; 758 759 sx150x_init_chip(chip, client, id->driver_data, pdata); 760 rc = sx150x_init_hw(chip, pdata); 761 if (rc < 0) 762 return rc; 763 764 rc = devm_gpiochip_add_data(&client->dev, &chip->gpio_chip, chip); 765 if (rc) 766 return rc; 767 768 if (pdata->irq_summary >= 0) { 769 rc = sx150x_install_irq_chip(chip, 770 pdata->irq_summary, 771 pdata->irq_base); 772 if (rc < 0) 773 return rc; 774 } 775 776 i2c_set_clientdata(client, chip); 777 778 return 0; 779} 780 781static struct i2c_driver sx150x_driver = { 782 .driver = { 783 .name = "sx150x", 784 .of_match_table = of_match_ptr(sx150x_of_match), 785 }, 786 .probe = sx150x_probe, 787 .id_table = sx150x_id, 788}; 789 790static int __init sx150x_init(void) 791{ 792 return i2c_add_driver(&sx150x_driver); 793} 794subsys_initcall(sx150x_init);