/drivers/gpio/gpio-sch.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * GPIO interface for Intel Poulsbo SCH
  4 *
  5 *  Copyright (c) 2010 CompuLab Ltd
  6 *  Author: Denis Turischev <denis@compulab.co.il>
  7 */
  8
  9#include <linux/acpi.h>
 10#include <linux/errno.h>
 11#include <linux/gpio/driver.h>
 12#include <linux/io.h>
 13#include <linux/kernel.h>
 14#include <linux/module.h>
 15#include <linux/pci_ids.h>
 16#include <linux/platform_device.h>
 17
 18#define GEN	0x00
 19#define GIO	0x04
 20#define GLV	0x08
 21
 22struct sch_gpio {
 23	struct gpio_chip chip;
 24	spinlock_t lock;
 25	unsigned short iobase;
 26	unsigned short resume_base;
 27};
 28
 29static unsigned sch_gpio_offset(struct sch_gpio *sch, unsigned gpio,
 30				unsigned reg)
 31{
 32	unsigned base = 0;
 33
 34	if (gpio >= sch->resume_base) {
 35		gpio -= sch->resume_base;
 36		base += 0x20;
 37	}
 38
 39	return base + reg + gpio / 8;
 40}
 41
 42static unsigned sch_gpio_bit(struct sch_gpio *sch, unsigned gpio)
 43{
 44	if (gpio >= sch->resume_base)
 45		gpio -= sch->resume_base;
 46	return gpio % 8;
 47}
 48
 49static int sch_gpio_reg_get(struct sch_gpio *sch, unsigned gpio, unsigned reg)
 50{
 51	unsigned short offset, bit;
 52	u8 reg_val;
 53
 54	offset = sch_gpio_offset(sch, gpio, reg);
 55	bit = sch_gpio_bit(sch, gpio);
 56
 57	reg_val = !!(inb(sch->iobase + offset) & BIT(bit));
 58
 59	return reg_val;
 60}
 61
 62static void sch_gpio_reg_set(struct sch_gpio *sch, unsigned gpio, unsigned reg,
 63			     int val)
 64{
 65	unsigned short offset, bit;
 66	u8 reg_val;
 67
 68	offset = sch_gpio_offset(sch, gpio, reg);
 69	bit = sch_gpio_bit(sch, gpio);
 70
 71	reg_val = inb(sch->iobase + offset);
 72
 73	if (val)
 74		outb(reg_val | BIT(bit), sch->iobase + offset);
 75	else
 76		outb((reg_val & ~BIT(bit)), sch->iobase + offset);
 77}
 78
 79static int sch_gpio_direction_in(struct gpio_chip *gc, unsigned gpio_num)
 80{
 81	struct sch_gpio *sch = gpiochip_get_data(gc);
 82
 83	spin_lock(&sch->lock);
 84	sch_gpio_reg_set(sch, gpio_num, GIO, 1);
 85	spin_unlock(&sch->lock);
 86	return 0;
 87}
 88
 89static int sch_gpio_get(struct gpio_chip *gc, unsigned gpio_num)
 90{
 91	struct sch_gpio *sch = gpiochip_get_data(gc);
 92	return sch_gpio_reg_get(sch, gpio_num, GLV);
 93}
 94
 95static void sch_gpio_set(struct gpio_chip *gc, unsigned gpio_num, int val)
 96{
 97	struct sch_gpio *sch = gpiochip_get_data(gc);
 98
 99	spin_lock(&sch->lock);
100	sch_gpio_reg_set(sch, gpio_num, GLV, val);
101	spin_unlock(&sch->lock);
102}
103
104static int sch_gpio_direction_out(struct gpio_chip *gc, unsigned gpio_num,
105				  int val)
106{
107	struct sch_gpio *sch = gpiochip_get_data(gc);
108
109	spin_lock(&sch->lock);
110	sch_gpio_reg_set(sch, gpio_num, GIO, 0);
111	spin_unlock(&sch->lock);
112
113	/*
114	 * according to the datasheet, writing to the level register has no
115	 * effect when GPIO is programmed as input.
116	 * Actually the the level register is read-only when configured as input.
117	 * Thus presetting the output level before switching to output is _NOT_ possible.
118	 * Hence we set the level after configuring the GPIO as output.
119	 * But we cannot prevent a short low pulse if direction is set to high
120	 * and an external pull-up is connected.
121	 */
122	sch_gpio_set(gc, gpio_num, val);
123	return 0;
124}
125
126static int sch_gpio_get_direction(struct gpio_chip *gc, unsigned gpio_num)
127{
128	struct sch_gpio *sch = gpiochip_get_data(gc);
129
130	if (sch_gpio_reg_get(sch, gpio_num, GIO))
131		return GPIO_LINE_DIRECTION_IN;
132
133	return GPIO_LINE_DIRECTION_OUT;
134}
135
136static const struct gpio_chip sch_gpio_chip = {
137	.label			= "sch_gpio",
138	.owner			= THIS_MODULE,
139	.direction_input	= sch_gpio_direction_in,
140	.get			= sch_gpio_get,
141	.direction_output	= sch_gpio_direction_out,
142	.set			= sch_gpio_set,
143	.get_direction		= sch_gpio_get_direction,
144};
145
146static int sch_gpio_probe(struct platform_device *pdev)
147{
148	struct sch_gpio *sch;
149	struct resource *res;
150
151	sch = devm_kzalloc(&pdev->dev, sizeof(*sch), GFP_KERNEL);
152	if (!sch)
153		return -ENOMEM;
154
155	res = platform_get_resource(pdev, IORESOURCE_IO, 0);
156	if (!res)
157		return -EBUSY;
158
159	if (!devm_request_region(&pdev->dev, res->start, resource_size(res),
160				 pdev->name))
161		return -EBUSY;
162
163	spin_lock_init(&sch->lock);
164	sch->iobase = res->start;
165	sch->chip = sch_gpio_chip;
166	sch->chip.label = dev_name(&pdev->dev);
167	sch->chip.parent = &pdev->dev;
168
169	switch (pdev->id) {
170	case PCI_DEVICE_ID_INTEL_SCH_LPC:
171		sch->resume_base = 10;
172		sch->chip.ngpio = 14;
173
174		/*
175		 * GPIO[6:0] enabled by default
176		 * GPIO7 is configured by the CMC as SLPIOVR
177		 * Enable GPIO[9:8] core powered gpios explicitly
178		 */
179		sch_gpio_reg_set(sch, 8, GEN, 1);
180		sch_gpio_reg_set(sch, 9, GEN, 1);
181		/*
182		 * SUS_GPIO[2:0] enabled by default
183		 * Enable SUS_GPIO3 resume powered gpio explicitly
184		 */
185		sch_gpio_reg_set(sch, 13, GEN, 1);
186		break;
187
188	case PCI_DEVICE_ID_INTEL_ITC_LPC:
189		sch->resume_base = 5;
190		sch->chip.ngpio = 14;
191		break;
192
193	case PCI_DEVICE_ID_INTEL_CENTERTON_ILB:
194		sch->resume_base = 21;
195		sch->chip.ngpio = 30;
196		break;
197
198	case PCI_DEVICE_ID_INTEL_QUARK_X1000_ILB:
199		sch->resume_base = 2;
200		sch->chip.ngpio = 8;
201		break;
202
203	default:
204		return -ENODEV;
205	}
206
207	platform_set_drvdata(pdev, sch);
208
209	return devm_gpiochip_add_data(&pdev->dev, &sch->chip, sch);
210}
211
212static struct platform_driver sch_gpio_driver = {
213	.driver = {
214		.name = "sch_gpio",
215	},
216	.probe		= sch_gpio_probe,
217};
218
219module_platform_driver(sch_gpio_driver);
220
221MODULE_AUTHOR("Denis Turischev <denis@compulab.co.il>");
222MODULE_DESCRIPTION("GPIO interface for Intel Poulsbo SCH");
223MODULE_LICENSE("GPL v2");
224MODULE_ALIAS("platform:sch_gpio");