/drivers/scsi/mvumi.h

http://github.com/mirrors/linux · C Header · 557 lines · 439 code · 77 blank · 41 comment · 11 complexity · 93b32ea96cdffd7f6d88d2b6c237f709 MD5 · raw file

  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Marvell UMI head file
  4. *
  5. * Copyright 2011 Marvell. <jyli@marvell.com>
  6. */
  7. #ifndef MVUMI_H
  8. #define MVUMI_H
  9. #define MAX_BASE_ADDRESS 6
  10. #define VER_MAJOR 1
  11. #define VER_MINOR 1
  12. #define VER_OEM 0
  13. #define VER_BUILD 1500
  14. #define MV_DRIVER_NAME "mvumi"
  15. #define PCI_DEVICE_ID_MARVELL_MV9143 0x9143
  16. #define PCI_DEVICE_ID_MARVELL_MV9580 0x9580
  17. #define MVUMI_INTERNAL_CMD_WAIT_TIME 45
  18. #define MVUMI_INQUIRY_LENGTH 44
  19. #define MVUMI_INQUIRY_UUID_OFF 36
  20. #define MVUMI_INQUIRY_UUID_LEN 8
  21. #define IS_DMA64 (sizeof(dma_addr_t) == 8)
  22. enum mvumi_qc_result {
  23. MV_QUEUE_COMMAND_RESULT_SENT = 0,
  24. MV_QUEUE_COMMAND_RESULT_NO_RESOURCE,
  25. };
  26. struct mvumi_hw_regs {
  27. /* For CPU */
  28. void *main_int_cause_reg;
  29. void *enpointa_mask_reg;
  30. void *enpointb_mask_reg;
  31. void *rstoutn_en_reg;
  32. void *ctrl_sts_reg;
  33. void *rstoutn_mask_reg;
  34. void *sys_soft_rst_reg;
  35. /* For Doorbell */
  36. void *pciea_to_arm_drbl_reg;
  37. void *arm_to_pciea_drbl_reg;
  38. void *arm_to_pciea_mask_reg;
  39. void *pciea_to_arm_msg0;
  40. void *pciea_to_arm_msg1;
  41. void *arm_to_pciea_msg0;
  42. void *arm_to_pciea_msg1;
  43. /* reset register */
  44. void *reset_request;
  45. void *reset_enable;
  46. /* For Message Unit */
  47. void *inb_list_basel;
  48. void *inb_list_baseh;
  49. void *inb_aval_count_basel;
  50. void *inb_aval_count_baseh;
  51. void *inb_write_pointer;
  52. void *inb_read_pointer;
  53. void *outb_list_basel;
  54. void *outb_list_baseh;
  55. void *outb_copy_basel;
  56. void *outb_copy_baseh;
  57. void *outb_copy_pointer;
  58. void *outb_read_pointer;
  59. void *inb_isr_cause;
  60. void *outb_isr_cause;
  61. void *outb_coal_cfg;
  62. void *outb_coal_timeout;
  63. /* Bit setting for HW */
  64. u32 int_comaout;
  65. u32 int_comaerr;
  66. u32 int_dl_cpu2pciea;
  67. u32 int_mu;
  68. u32 int_drbl_int_mask;
  69. u32 int_main_int_mask;
  70. u32 cl_pointer_toggle;
  71. u32 cl_slot_num_mask;
  72. u32 clic_irq;
  73. u32 clic_in_err;
  74. u32 clic_out_err;
  75. };
  76. struct mvumi_dyn_list_entry {
  77. u32 src_low_addr;
  78. u32 src_high_addr;
  79. u32 if_length;
  80. u32 reserve;
  81. };
  82. #define SCSI_CMD_MARVELL_SPECIFIC 0xE1
  83. #define CDB_CORE_MODULE 0x1
  84. #define CDB_CORE_SHUTDOWN 0xB
  85. enum {
  86. DRBL_HANDSHAKE = 1 << 0,
  87. DRBL_SOFT_RESET = 1 << 1,
  88. DRBL_BUS_CHANGE = 1 << 2,
  89. DRBL_EVENT_NOTIFY = 1 << 3,
  90. DRBL_MU_RESET = 1 << 4,
  91. DRBL_HANDSHAKE_ISR = DRBL_HANDSHAKE,
  92. /*
  93. * Command flag is the flag for the CDB command itself
  94. */
  95. /* 1-non data; 0-data command */
  96. CMD_FLAG_NON_DATA = 1 << 0,
  97. CMD_FLAG_DMA = 1 << 1,
  98. CMD_FLAG_PIO = 1 << 2,
  99. /* 1-host read data */
  100. CMD_FLAG_DATA_IN = 1 << 3,
  101. /* 1-host write data */
  102. CMD_FLAG_DATA_OUT = 1 << 4,
  103. CMD_FLAG_PRDT_IN_HOST = 1 << 5,
  104. };
  105. #define APICDB0_EVENT 0xF4
  106. #define APICDB1_EVENT_GETEVENT 0
  107. #define APICDB1_HOST_GETEVENT 1
  108. #define MAX_EVENTS_RETURNED 6
  109. #define DEVICE_OFFLINE 0
  110. #define DEVICE_ONLINE 1
  111. struct mvumi_hotplug_event {
  112. u16 size;
  113. u8 dummy[2];
  114. u8 bitmap[];
  115. };
  116. struct mvumi_driver_event {
  117. u32 time_stamp;
  118. u32 sequence_no;
  119. u32 event_id;
  120. u8 severity;
  121. u8 param_count;
  122. u16 device_id;
  123. u32 params[4];
  124. u8 sense_data_length;
  125. u8 Reserved1;
  126. u8 sense_data[30];
  127. };
  128. struct mvumi_event_req {
  129. unsigned char count;
  130. unsigned char reserved[3];
  131. struct mvumi_driver_event events[MAX_EVENTS_RETURNED];
  132. };
  133. struct mvumi_events_wq {
  134. struct work_struct work_q;
  135. struct mvumi_hba *mhba;
  136. unsigned int event;
  137. void *param;
  138. };
  139. #define HS_CAPABILITY_SUPPORT_COMPACT_SG (1U << 4)
  140. #define HS_CAPABILITY_SUPPORT_PRD_HOST (1U << 5)
  141. #define HS_CAPABILITY_SUPPORT_DYN_SRC (1U << 6)
  142. #define HS_CAPABILITY_NEW_PAGE_IO_DEPTH_DEF (1U << 14)
  143. #define MVUMI_MAX_SG_ENTRY 32
  144. #define SGD_EOT (1L << 27)
  145. #define SGD_EOT_CP (1L << 22)
  146. struct mvumi_sgl {
  147. u32 baseaddr_l;
  148. u32 baseaddr_h;
  149. u32 flags;
  150. u32 size;
  151. };
  152. struct mvumi_compact_sgl {
  153. u32 baseaddr_l;
  154. u32 baseaddr_h;
  155. u32 flags;
  156. };
  157. #define GET_COMPACT_SGD_SIZE(sgd) \
  158. ((((struct mvumi_compact_sgl *)(sgd))->flags) & 0x3FFFFFL)
  159. #define SET_COMPACT_SGD_SIZE(sgd, sz) do { \
  160. (((struct mvumi_compact_sgl *)(sgd))->flags) &= ~0x3FFFFFL; \
  161. (((struct mvumi_compact_sgl *)(sgd))->flags) |= (sz); \
  162. } while (0)
  163. #define sgd_getsz(_mhba, sgd, sz) do { \
  164. if (_mhba->hba_capability & HS_CAPABILITY_SUPPORT_COMPACT_SG) \
  165. (sz) = GET_COMPACT_SGD_SIZE(sgd); \
  166. else \
  167. (sz) = (sgd)->size; \
  168. } while (0)
  169. #define sgd_setsz(_mhba, sgd, sz) do { \
  170. if (_mhba->hba_capability & HS_CAPABILITY_SUPPORT_COMPACT_SG) \
  171. SET_COMPACT_SGD_SIZE(sgd, sz); \
  172. else \
  173. (sgd)->size = (sz); \
  174. } while (0)
  175. #define sgd_inc(_mhba, sgd) do { \
  176. if (_mhba->hba_capability & HS_CAPABILITY_SUPPORT_COMPACT_SG) \
  177. sgd = (struct mvumi_sgl *)(((unsigned char *) (sgd)) + 12); \
  178. else \
  179. sgd = (struct mvumi_sgl *)(((unsigned char *) (sgd)) + 16); \
  180. } while (0)
  181. struct mvumi_res {
  182. struct list_head entry;
  183. dma_addr_t bus_addr;
  184. void *virt_addr;
  185. unsigned int size;
  186. unsigned short type; /* enum Resource_Type */
  187. };
  188. /* Resource type */
  189. enum resource_type {
  190. RESOURCE_CACHED_MEMORY = 0,
  191. RESOURCE_UNCACHED_MEMORY
  192. };
  193. struct mvumi_sense_data {
  194. u8 error_code:7;
  195. u8 valid:1;
  196. u8 segment_number;
  197. u8 sense_key:4;
  198. u8 reserved:1;
  199. u8 incorrect_length:1;
  200. u8 end_of_media:1;
  201. u8 file_mark:1;
  202. u8 information[4];
  203. u8 additional_sense_length;
  204. u8 command_specific_information[4];
  205. u8 additional_sense_code;
  206. u8 additional_sense_code_qualifier;
  207. u8 field_replaceable_unit_code;
  208. u8 sense_key_specific[3];
  209. };
  210. /* Request initiator must set the status to REQ_STATUS_PENDING. */
  211. #define REQ_STATUS_PENDING 0x80
  212. struct mvumi_cmd {
  213. struct list_head queue_pointer;
  214. struct mvumi_msg_frame *frame;
  215. dma_addr_t frame_phys;
  216. struct scsi_cmnd *scmd;
  217. atomic_t sync_cmd;
  218. void *data_buf;
  219. unsigned short request_id;
  220. unsigned char cmd_status;
  221. };
  222. /*
  223. * the function type of the in bound frame
  224. */
  225. #define CL_FUN_SCSI_CMD 0x1
  226. struct mvumi_msg_frame {
  227. u16 device_id;
  228. u16 tag;
  229. u8 cmd_flag;
  230. u8 req_function;
  231. u8 cdb_length;
  232. u8 sg_counts;
  233. u32 data_transfer_length;
  234. u16 request_id;
  235. u16 reserved1;
  236. u8 cdb[MAX_COMMAND_SIZE];
  237. u32 payload[1];
  238. };
  239. /*
  240. * the respond flag for data_payload of the out bound frame
  241. */
  242. #define CL_RSP_FLAG_NODATA 0x0
  243. #define CL_RSP_FLAG_SENSEDATA 0x1
  244. struct mvumi_rsp_frame {
  245. u16 device_id;
  246. u16 tag;
  247. u8 req_status;
  248. u8 rsp_flag; /* Indicates the type of Data_Payload.*/
  249. u16 request_id;
  250. u32 payload[1];
  251. };
  252. struct mvumi_ob_data {
  253. struct list_head list;
  254. unsigned char data[];
  255. };
  256. struct version_info {
  257. u32 ver_major;
  258. u32 ver_minor;
  259. u32 ver_oem;
  260. u32 ver_build;
  261. };
  262. #define FW_MAX_DELAY 30
  263. #define MVUMI_FW_BUSY (1U << 0)
  264. #define MVUMI_FW_ATTACH (1U << 1)
  265. #define MVUMI_FW_ALLOC (1U << 2)
  266. /*
  267. * State is the state of the MU
  268. */
  269. #define FW_STATE_IDLE 0
  270. #define FW_STATE_STARTING 1
  271. #define FW_STATE_HANDSHAKING 2
  272. #define FW_STATE_STARTED 3
  273. #define FW_STATE_ABORT 4
  274. #define HANDSHAKE_SIGNATURE 0x5A5A5A5AL
  275. #define HANDSHAKE_READYSTATE 0x55AA5AA5L
  276. #define HANDSHAKE_DONESTATE 0x55AAA55AL
  277. /* HandShake Status definition */
  278. #define HS_STATUS_OK 1
  279. #define HS_STATUS_ERR 2
  280. #define HS_STATUS_INVALID 3
  281. /* HandShake State/Cmd definition */
  282. #define HS_S_START 1
  283. #define HS_S_RESET 2
  284. #define HS_S_PAGE_ADDR 3
  285. #define HS_S_QUERY_PAGE 4
  286. #define HS_S_SEND_PAGE 5
  287. #define HS_S_END 6
  288. #define HS_S_ABORT 7
  289. #define HS_PAGE_VERIFY_SIZE 128
  290. #define HS_GET_STATE(a) (a & 0xFFFF)
  291. #define HS_GET_STATUS(a) ((a & 0xFFFF0000) >> 16)
  292. #define HS_SET_STATE(a, b) (a |= (b & 0xFFFF))
  293. #define HS_SET_STATUS(a, b) (a |= ((b & 0xFFFF) << 16))
  294. /* handshake frame */
  295. struct mvumi_hs_frame {
  296. u16 size;
  297. /* host information */
  298. u8 host_type;
  299. u8 reserved_1[1];
  300. struct version_info host_ver; /* bios or driver version */
  301. /* controller information */
  302. u32 system_io_bus;
  303. u32 slot_number;
  304. u32 intr_level;
  305. u32 intr_vector;
  306. /* communication list configuration */
  307. u32 ib_baseaddr_l;
  308. u32 ib_baseaddr_h;
  309. u32 ob_baseaddr_l;
  310. u32 ob_baseaddr_h;
  311. u8 ib_entry_size;
  312. u8 ob_entry_size;
  313. u8 ob_depth;
  314. u8 ib_depth;
  315. /* system time */
  316. u64 seconds_since1970;
  317. };
  318. struct mvumi_hs_header {
  319. u8 page_code;
  320. u8 checksum;
  321. u16 frame_length;
  322. u32 frame_content[1];
  323. };
  324. /*
  325. * the page code type of the handshake header
  326. */
  327. #define HS_PAGE_FIRM_CAP 0x1
  328. #define HS_PAGE_HOST_INFO 0x2
  329. #define HS_PAGE_FIRM_CTL 0x3
  330. #define HS_PAGE_CL_INFO 0x4
  331. #define HS_PAGE_TOTAL 0x5
  332. #define HSP_SIZE(i) sizeof(struct mvumi_hs_page##i)
  333. #define HSP_MAX_SIZE ({ \
  334. int size, m1, m2; \
  335. m1 = max(HSP_SIZE(1), HSP_SIZE(3)); \
  336. m2 = max(HSP_SIZE(2), HSP_SIZE(4)); \
  337. size = max(m1, m2); \
  338. size; \
  339. })
  340. /* The format of the page code for Firmware capability */
  341. struct mvumi_hs_page1 {
  342. u8 pagecode;
  343. u8 checksum;
  344. u16 frame_length;
  345. u16 number_of_ports;
  346. u16 max_devices_support;
  347. u16 max_io_support;
  348. u16 umi_ver;
  349. u32 max_transfer_size;
  350. struct version_info fw_ver;
  351. u8 cl_in_max_entry_size;
  352. u8 cl_out_max_entry_size;
  353. u8 cl_inout_list_depth;
  354. u8 total_pages;
  355. u16 capability;
  356. u16 reserved1;
  357. };
  358. /* The format of the page code for Host information */
  359. struct mvumi_hs_page2 {
  360. u8 pagecode;
  361. u8 checksum;
  362. u16 frame_length;
  363. u8 host_type;
  364. u8 host_cap;
  365. u8 reserved[2];
  366. struct version_info host_ver;
  367. u32 system_io_bus;
  368. u32 slot_number;
  369. u32 intr_level;
  370. u32 intr_vector;
  371. u64 seconds_since1970;
  372. };
  373. /* The format of the page code for firmware control */
  374. struct mvumi_hs_page3 {
  375. u8 pagecode;
  376. u8 checksum;
  377. u16 frame_length;
  378. u16 control;
  379. u8 reserved[2];
  380. u32 host_bufferaddr_l;
  381. u32 host_bufferaddr_h;
  382. u32 host_eventaddr_l;
  383. u32 host_eventaddr_h;
  384. };
  385. struct mvumi_hs_page4 {
  386. u8 pagecode;
  387. u8 checksum;
  388. u16 frame_length;
  389. u32 ib_baseaddr_l;
  390. u32 ib_baseaddr_h;
  391. u32 ob_baseaddr_l;
  392. u32 ob_baseaddr_h;
  393. u8 ib_entry_size;
  394. u8 ob_entry_size;
  395. u8 ob_depth;
  396. u8 ib_depth;
  397. };
  398. struct mvumi_tag {
  399. unsigned short *stack;
  400. unsigned short top;
  401. unsigned short size;
  402. };
  403. struct mvumi_device {
  404. struct list_head list;
  405. struct scsi_device *sdev;
  406. u64 wwid;
  407. u8 dev_type;
  408. int id;
  409. };
  410. struct mvumi_hba {
  411. void *base_addr[MAX_BASE_ADDRESS];
  412. u32 pci_base[MAX_BASE_ADDRESS];
  413. void *mmio;
  414. struct list_head cmd_pool;
  415. struct Scsi_Host *shost;
  416. wait_queue_head_t int_cmd_wait_q;
  417. struct pci_dev *pdev;
  418. unsigned int unique_id;
  419. atomic_t fw_outstanding;
  420. struct mvumi_instance_template *instancet;
  421. void *ib_list;
  422. dma_addr_t ib_list_phys;
  423. void *ib_frame;
  424. dma_addr_t ib_frame_phys;
  425. void *ob_list;
  426. dma_addr_t ob_list_phys;
  427. void *ib_shadow;
  428. dma_addr_t ib_shadow_phys;
  429. void *ob_shadow;
  430. dma_addr_t ob_shadow_phys;
  431. void *handshake_page;
  432. dma_addr_t handshake_page_phys;
  433. unsigned int global_isr;
  434. unsigned int isr_status;
  435. unsigned short max_sge;
  436. unsigned short max_target_id;
  437. unsigned char *target_map;
  438. unsigned int max_io;
  439. unsigned int list_num_io;
  440. unsigned int ib_max_size;
  441. unsigned int ob_max_size;
  442. unsigned int ib_max_size_setting;
  443. unsigned int ob_max_size_setting;
  444. unsigned int max_transfer_size;
  445. unsigned char hba_total_pages;
  446. unsigned char fw_flag;
  447. unsigned char request_id_enabled;
  448. unsigned char eot_flag;
  449. unsigned short hba_capability;
  450. unsigned short io_seq;
  451. unsigned int ib_cur_slot;
  452. unsigned int ob_cur_slot;
  453. unsigned int fw_state;
  454. struct mutex sas_discovery_mutex;
  455. struct list_head ob_data_list;
  456. struct list_head free_ob_list;
  457. struct list_head res_list;
  458. struct list_head waiting_req_list;
  459. struct mvumi_tag tag_pool;
  460. struct mvumi_cmd **tag_cmd;
  461. struct mvumi_hw_regs *regs;
  462. struct mutex device_lock;
  463. struct list_head mhba_dev_list;
  464. struct list_head shost_dev_list;
  465. struct task_struct *dm_thread;
  466. atomic_t pnp_count;
  467. };
  468. struct mvumi_instance_template {
  469. void (*fire_cmd) (struct mvumi_hba *, struct mvumi_cmd *);
  470. void (*enable_intr) (struct mvumi_hba *);
  471. void (*disable_intr) (struct mvumi_hba *);
  472. int (*clear_intr) (void *);
  473. unsigned int (*read_fw_status_reg) (struct mvumi_hba *);
  474. unsigned int (*check_ib_list) (struct mvumi_hba *);
  475. int (*check_ob_list) (struct mvumi_hba *, unsigned int *,
  476. unsigned int *);
  477. int (*reset_host) (struct mvumi_hba *);
  478. };
  479. extern struct timezone sys_tz;
  480. #endif