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/drivers/scsi/aic94xx/aic94xx_seq.c

http://github.com/mirrors/linux
C | 1397 lines | 905 code | 204 blank | 288 comment | 83 complexity | 41e2644f812e91afa12b1a731aaba813 MD5 | raw file
   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Aic94xx SAS/SATA driver sequencer interface.
   4 *
   5 * Copyright (C) 2005 Adaptec, Inc.  All rights reserved.
   6 * Copyright (C) 2005 Luben Tuikov <luben_tuikov@adaptec.com>
   7 *
   8 * Parts of this code adapted from David Chaw's adp94xx_seq.c.
   9 */
  10
  11#include <linux/delay.h>
  12#include <linux/gfp.h>
  13#include <linux/pci.h>
  14#include <linux/module.h>
  15#include <linux/firmware.h>
  16#include "aic94xx_reg.h"
  17#include "aic94xx_hwi.h"
  18
  19#include "aic94xx_seq.h"
  20#include "aic94xx_dump.h"
  21
  22/* It takes no more than 0.05 us for an instruction
  23 * to complete. So waiting for 1 us should be more than
  24 * plenty.
  25 */
  26#define PAUSE_DELAY 1
  27#define PAUSE_TRIES 1000
  28
  29static const struct firmware *sequencer_fw;
  30static u16 cseq_vecs[CSEQ_NUM_VECS], lseq_vecs[LSEQ_NUM_VECS], mode2_task,
  31	cseq_idle_loop, lseq_idle_loop;
  32static const u8 *cseq_code, *lseq_code;
  33static u32 cseq_code_size, lseq_code_size;
  34
  35static u16 first_scb_site_no = 0xFFFF;
  36static u16 last_scb_site_no;
  37
  38/* ---------- Pause/Unpause CSEQ/LSEQ ---------- */
  39
  40/**
  41 * asd_pause_cseq - pause the central sequencer
  42 * @asd_ha: pointer to host adapter structure
  43 *
  44 * Return 0 on success, negative on failure.
  45 */
  46static int asd_pause_cseq(struct asd_ha_struct *asd_ha)
  47{
  48	int	count = PAUSE_TRIES;
  49	u32	arp2ctl;
  50
  51	arp2ctl = asd_read_reg_dword(asd_ha, CARP2CTL);
  52	if (arp2ctl & PAUSED)
  53		return 0;
  54
  55	asd_write_reg_dword(asd_ha, CARP2CTL, arp2ctl | EPAUSE);
  56	do {
  57		arp2ctl = asd_read_reg_dword(asd_ha, CARP2CTL);
  58		if (arp2ctl & PAUSED)
  59			return 0;
  60		udelay(PAUSE_DELAY);
  61	} while (--count > 0);
  62
  63	ASD_DPRINTK("couldn't pause CSEQ\n");
  64	return -1;
  65}
  66
  67/**
  68 * asd_unpause_cseq - unpause the central sequencer.
  69 * @asd_ha: pointer to host adapter structure.
  70 *
  71 * Return 0 on success, negative on error.
  72 */
  73static int asd_unpause_cseq(struct asd_ha_struct *asd_ha)
  74{
  75	u32	arp2ctl;
  76	int	count = PAUSE_TRIES;
  77
  78	arp2ctl = asd_read_reg_dword(asd_ha, CARP2CTL);
  79	if (!(arp2ctl & PAUSED))
  80		return 0;
  81
  82	asd_write_reg_dword(asd_ha, CARP2CTL, arp2ctl & ~EPAUSE);
  83	do {
  84		arp2ctl = asd_read_reg_dword(asd_ha, CARP2CTL);
  85		if (!(arp2ctl & PAUSED))
  86			return 0;
  87		udelay(PAUSE_DELAY);
  88	} while (--count > 0);
  89
  90	ASD_DPRINTK("couldn't unpause the CSEQ\n");
  91	return -1;
  92}
  93
  94/**
  95 * asd_seq_pause_lseq - pause a link sequencer
  96 * @asd_ha: pointer to a host adapter structure
  97 * @lseq: link sequencer of interest
  98 *
  99 * Return 0 on success, negative on error.
 100 */
 101static int asd_seq_pause_lseq(struct asd_ha_struct *asd_ha, int lseq)
 102{
 103	u32    arp2ctl;
 104	int    count = PAUSE_TRIES;
 105
 106	arp2ctl = asd_read_reg_dword(asd_ha, LmARP2CTL(lseq));
 107	if (arp2ctl & PAUSED)
 108		return 0;
 109
 110	asd_write_reg_dword(asd_ha, LmARP2CTL(lseq), arp2ctl | EPAUSE);
 111	do {
 112		arp2ctl = asd_read_reg_dword(asd_ha, LmARP2CTL(lseq));
 113		if (arp2ctl & PAUSED)
 114			return 0;
 115		udelay(PAUSE_DELAY);
 116	} while (--count > 0);
 117
 118	ASD_DPRINTK("couldn't pause LSEQ %d\n", lseq);
 119	return -1;
 120}
 121
 122/**
 123 * asd_pause_lseq - pause the link sequencer(s)
 124 * @asd_ha: pointer to host adapter structure
 125 * @lseq_mask: mask of link sequencers of interest
 126 *
 127 * Return 0 on success, negative on failure.
 128 */
 129static int asd_pause_lseq(struct asd_ha_struct *asd_ha, u8 lseq_mask)
 130{
 131	int lseq;
 132	int err = 0;
 133
 134	for_each_sequencer(lseq_mask, lseq_mask, lseq) {
 135		err = asd_seq_pause_lseq(asd_ha, lseq);
 136		if (err)
 137			return err;
 138	}
 139
 140	return err;
 141}
 142
 143/**
 144 * asd_seq_unpause_lseq - unpause a link sequencer
 145 * @asd_ha: pointer to host adapter structure
 146 * @lseq: link sequencer of interest
 147 *
 148 * Return 0 on success, negative on error.
 149 */
 150static int asd_seq_unpause_lseq(struct asd_ha_struct *asd_ha, int lseq)
 151{
 152	u32 arp2ctl;
 153	int count = PAUSE_TRIES;
 154
 155	arp2ctl = asd_read_reg_dword(asd_ha, LmARP2CTL(lseq));
 156	if (!(arp2ctl & PAUSED))
 157		return 0;
 158
 159	asd_write_reg_dword(asd_ha, LmARP2CTL(lseq), arp2ctl & ~EPAUSE);
 160	do {
 161		arp2ctl = asd_read_reg_dword(asd_ha, LmARP2CTL(lseq));
 162		if (!(arp2ctl & PAUSED))
 163			return 0;
 164		udelay(PAUSE_DELAY);
 165	} while (--count > 0);
 166
 167	ASD_DPRINTK("couldn't unpause LSEQ %d\n", lseq);
 168	return 0;
 169}
 170
 171
 172/* ---------- Downloading CSEQ/LSEQ microcode ---------- */
 173
 174static int asd_verify_cseq(struct asd_ha_struct *asd_ha, const u8 *_prog,
 175			   u32 size)
 176{
 177	u32 addr = CSEQ_RAM_REG_BASE_ADR;
 178	const u32 *prog = (u32 *) _prog;
 179	u32 i;
 180
 181	for (i = 0; i < size; i += 4, prog++, addr += 4) {
 182		u32 val = asd_read_reg_dword(asd_ha, addr);
 183
 184		if (le32_to_cpu(*prog) != val) {
 185			asd_printk("%s: cseq verify failed at %u "
 186				   "read:0x%x, wanted:0x%x\n",
 187				   pci_name(asd_ha->pcidev),
 188				   i, val, le32_to_cpu(*prog));
 189			return -1;
 190		}
 191	}
 192	ASD_DPRINTK("verified %d bytes, passed\n", size);
 193	return 0;
 194}
 195
 196/**
 197 * asd_verify_lseq - verify the microcode of a link sequencer
 198 * @asd_ha: pointer to host adapter structure
 199 * @_prog: pointer to the microcode
 200 * @size: size of the microcode in bytes
 201 * @lseq: link sequencer of interest
 202 *
 203 * The link sequencer code is accessed in 4 KB pages, which are selected
 204 * by setting LmRAMPAGE (bits 8 and 9) of the LmBISTCTL1 register.
 205 * The 10 KB LSEQm instruction code is mapped, page at a time, at
 206 * LmSEQRAM address.
 207 */
 208static int asd_verify_lseq(struct asd_ha_struct *asd_ha, const u8 *_prog,
 209			   u32 size, int lseq)
 210{
 211#define LSEQ_CODEPAGE_SIZE 4096
 212	int pages =  (size + LSEQ_CODEPAGE_SIZE - 1) / LSEQ_CODEPAGE_SIZE;
 213	u32 page;
 214	const u32 *prog = (u32 *) _prog;
 215
 216	for (page = 0; page < pages; page++) {
 217		u32 i;
 218
 219		asd_write_reg_dword(asd_ha, LmBISTCTL1(lseq),
 220				    page << LmRAMPAGE_LSHIFT);
 221		for (i = 0; size > 0 && i < LSEQ_CODEPAGE_SIZE;
 222		     i += 4, prog++, size-=4) {
 223
 224			u32 val = asd_read_reg_dword(asd_ha, LmSEQRAM(lseq)+i);
 225
 226			if (le32_to_cpu(*prog) != val) {
 227				asd_printk("%s: LSEQ%d verify failed "
 228					   "page:%d, offs:%d\n",
 229					   pci_name(asd_ha->pcidev),
 230					   lseq, page, i);
 231				return -1;
 232			}
 233		}
 234	}
 235	ASD_DPRINTK("LSEQ%d verified %d bytes, passed\n", lseq,
 236		    (int)((u8 *)prog-_prog));
 237	return 0;
 238}
 239
 240/**
 241 * asd_verify_seq -- verify CSEQ/LSEQ microcode
 242 * @asd_ha: pointer to host adapter structure
 243 * @prog: pointer to microcode
 244 * @size: size of the microcode
 245 * @lseq_mask: if 0, verify CSEQ microcode, else mask of LSEQs of interest
 246 *
 247 * Return 0 if microcode is correct, negative on mismatch.
 248 */
 249static int asd_verify_seq(struct asd_ha_struct *asd_ha, const u8 *prog,
 250			      u32 size, u8 lseq_mask)
 251{
 252	if (lseq_mask == 0)
 253		return asd_verify_cseq(asd_ha, prog, size);
 254	else {
 255		int lseq, err;
 256
 257		for_each_sequencer(lseq_mask, lseq_mask, lseq) {
 258			err = asd_verify_lseq(asd_ha, prog, size, lseq);
 259			if (err)
 260				return err;
 261		}
 262	}
 263
 264	return 0;
 265}
 266#define ASD_DMA_MODE_DOWNLOAD
 267#ifdef ASD_DMA_MODE_DOWNLOAD
 268/* This is the size of the CSEQ Mapped instruction page */
 269#define MAX_DMA_OVLY_COUNT ((1U << 14)-1)
 270static int asd_download_seq(struct asd_ha_struct *asd_ha,
 271			    const u8 * const prog, u32 size, u8 lseq_mask)
 272{
 273	u32 comstaten;
 274	u32 reg;
 275	int page;
 276	const int pages = (size + MAX_DMA_OVLY_COUNT - 1) / MAX_DMA_OVLY_COUNT;
 277	struct asd_dma_tok *token;
 278	int err = 0;
 279
 280	if (size % 4) {
 281		asd_printk("sequencer program not multiple of 4\n");
 282		return -1;
 283	}
 284
 285	asd_pause_cseq(asd_ha);
 286	asd_pause_lseq(asd_ha, 0xFF);
 287
 288	/* save, disable and clear interrupts */
 289	comstaten = asd_read_reg_dword(asd_ha, COMSTATEN);
 290	asd_write_reg_dword(asd_ha, COMSTATEN, 0);
 291	asd_write_reg_dword(asd_ha, COMSTAT, COMSTAT_MASK);
 292
 293	asd_write_reg_dword(asd_ha, CHIMINTEN, RST_CHIMINTEN);
 294	asd_write_reg_dword(asd_ha, CHIMINT, CHIMINT_MASK);
 295
 296	token = asd_alloc_coherent(asd_ha, MAX_DMA_OVLY_COUNT, GFP_KERNEL);
 297	if (!token) {
 298		asd_printk("out of memory for dma SEQ download\n");
 299		err = -ENOMEM;
 300		goto out;
 301	}
 302	ASD_DPRINTK("dma-ing %d bytes\n", size);
 303
 304	for (page = 0; page < pages; page++) {
 305		int i;
 306		u32 left = min(size-page*MAX_DMA_OVLY_COUNT,
 307			       (u32)MAX_DMA_OVLY_COUNT);
 308
 309		memcpy(token->vaddr, prog + page*MAX_DMA_OVLY_COUNT, left);
 310		asd_write_reg_addr(asd_ha, OVLYDMAADR, token->dma_handle);
 311		asd_write_reg_dword(asd_ha, OVLYDMACNT, left);
 312		reg = !page ? RESETOVLYDMA : 0;
 313		reg |= (STARTOVLYDMA | OVLYHALTERR);
 314		reg |= (lseq_mask ? (((u32)lseq_mask) << 8) : OVLYCSEQ);
 315		/* Start DMA. */
 316		asd_write_reg_dword(asd_ha, OVLYDMACTL, reg);
 317
 318		for (i = PAUSE_TRIES*100; i > 0; i--) {
 319			u32 dmadone = asd_read_reg_dword(asd_ha, OVLYDMACTL);
 320			if (!(dmadone & OVLYDMAACT))
 321				break;
 322			udelay(PAUSE_DELAY);
 323		}
 324	}
 325
 326	reg = asd_read_reg_dword(asd_ha, COMSTAT);
 327	if (!(reg & OVLYDMADONE) || (reg & OVLYERR)
 328	    || (asd_read_reg_dword(asd_ha, CHIMINT) & DEVEXCEPT_MASK)){
 329		asd_printk("%s: error DMA-ing sequencer code\n",
 330			   pci_name(asd_ha->pcidev));
 331		err = -ENODEV;
 332	}
 333
 334	asd_free_coherent(asd_ha, token);
 335 out:
 336	asd_write_reg_dword(asd_ha, COMSTATEN, comstaten);
 337
 338	return err ? : asd_verify_seq(asd_ha, prog, size, lseq_mask);
 339}
 340#else /* ASD_DMA_MODE_DOWNLOAD */
 341static int asd_download_seq(struct asd_ha_struct *asd_ha, const u8 *_prog,
 342			    u32 size, u8 lseq_mask)
 343{
 344	int i;
 345	u32 reg = 0;
 346	const u32 *prog = (u32 *) _prog;
 347
 348	if (size % 4) {
 349		asd_printk("sequencer program not multiple of 4\n");
 350		return -1;
 351	}
 352
 353	asd_pause_cseq(asd_ha);
 354	asd_pause_lseq(asd_ha, 0xFF);
 355
 356	reg |= (lseq_mask ? (((u32)lseq_mask) << 8) : OVLYCSEQ);
 357	reg |= PIOCMODE;
 358
 359	asd_write_reg_dword(asd_ha, OVLYDMACNT, size);
 360	asd_write_reg_dword(asd_ha, OVLYDMACTL, reg);
 361
 362	ASD_DPRINTK("downloading %s sequencer%s in PIO mode...\n",
 363		    lseq_mask ? "LSEQ" : "CSEQ", lseq_mask ? "s" : "");
 364
 365	for (i = 0; i < size; i += 4, prog++)
 366		asd_write_reg_dword(asd_ha, SPIODATA, *prog);
 367
 368	reg = (reg & ~PIOCMODE) | OVLYHALTERR;
 369	asd_write_reg_dword(asd_ha, OVLYDMACTL, reg);
 370
 371	return asd_verify_seq(asd_ha, _prog, size, lseq_mask);
 372}
 373#endif /* ASD_DMA_MODE_DOWNLOAD */
 374
 375/**
 376 * asd_seq_download_seqs - download the sequencer microcode
 377 * @asd_ha: pointer to host adapter structure
 378 *
 379 * Download the central and link sequencer microcode.
 380 */
 381static int asd_seq_download_seqs(struct asd_ha_struct *asd_ha)
 382{
 383	int 	err;
 384
 385	if (!asd_ha->hw_prof.enabled_phys) {
 386		asd_printk("%s: no enabled phys!\n", pci_name(asd_ha->pcidev));
 387		return -ENODEV;
 388	}
 389
 390	/* Download the CSEQ */
 391	ASD_DPRINTK("downloading CSEQ...\n");
 392	err = asd_download_seq(asd_ha, cseq_code, cseq_code_size, 0);
 393	if (err) {
 394		asd_printk("CSEQ download failed:%d\n", err);
 395		return err;
 396	}
 397
 398	/* Download the Link Sequencers code. All of the Link Sequencers
 399	 * microcode can be downloaded at the same time.
 400	 */
 401	ASD_DPRINTK("downloading LSEQs...\n");
 402	err = asd_download_seq(asd_ha, lseq_code, lseq_code_size,
 403			       asd_ha->hw_prof.enabled_phys);
 404	if (err) {
 405		/* Try it one at a time */
 406		u8 lseq;
 407		u8 lseq_mask = asd_ha->hw_prof.enabled_phys;
 408
 409		for_each_sequencer(lseq_mask, lseq_mask, lseq) {
 410			err = asd_download_seq(asd_ha, lseq_code,
 411					       lseq_code_size, 1<<lseq);
 412			if (err)
 413				break;
 414		}
 415	}
 416	if (err)
 417		asd_printk("LSEQs download failed:%d\n", err);
 418
 419	return err;
 420}
 421
 422/* ---------- Initializing the chip, chip memory, etc. ---------- */
 423
 424/**
 425 * asd_init_cseq_mip - initialize CSEQ mode independent pages 4-7
 426 * @asd_ha: pointer to host adapter structure
 427 */
 428static void asd_init_cseq_mip(struct asd_ha_struct *asd_ha)
 429{
 430	/* CSEQ Mode Independent, page 4 setup. */
 431	asd_write_reg_word(asd_ha, CSEQ_Q_EXE_HEAD, 0xFFFF);
 432	asd_write_reg_word(asd_ha, CSEQ_Q_EXE_TAIL, 0xFFFF);
 433	asd_write_reg_word(asd_ha, CSEQ_Q_DONE_HEAD, 0xFFFF);
 434	asd_write_reg_word(asd_ha, CSEQ_Q_DONE_TAIL, 0xFFFF);
 435	asd_write_reg_word(asd_ha, CSEQ_Q_SEND_HEAD, 0xFFFF);
 436	asd_write_reg_word(asd_ha, CSEQ_Q_SEND_TAIL, 0xFFFF);
 437	asd_write_reg_word(asd_ha, CSEQ_Q_DMA2CHIM_HEAD, 0xFFFF);
 438	asd_write_reg_word(asd_ha, CSEQ_Q_DMA2CHIM_TAIL, 0xFFFF);
 439	asd_write_reg_word(asd_ha, CSEQ_Q_COPY_HEAD, 0xFFFF);
 440	asd_write_reg_word(asd_ha, CSEQ_Q_COPY_TAIL, 0xFFFF);
 441	asd_write_reg_word(asd_ha, CSEQ_REG0, 0);
 442	asd_write_reg_word(asd_ha, CSEQ_REG1, 0);
 443	asd_write_reg_dword(asd_ha, CSEQ_REG2, 0);
 444	asd_write_reg_byte(asd_ha, CSEQ_LINK_CTL_Q_MAP, 0);
 445	{
 446		u8 con = asd_read_reg_byte(asd_ha, CCONEXIST);
 447		u8 val = hweight8(con);
 448		asd_write_reg_byte(asd_ha, CSEQ_MAX_CSEQ_MODE, (val<<4)|val);
 449	}
 450	asd_write_reg_word(asd_ha, CSEQ_FREE_LIST_HACK_COUNT, 0);
 451
 452	/* CSEQ Mode independent, page 5 setup. */
 453	asd_write_reg_dword(asd_ha, CSEQ_EST_NEXUS_REQ_QUEUE, 0);
 454	asd_write_reg_dword(asd_ha, CSEQ_EST_NEXUS_REQ_QUEUE+4, 0);
 455	asd_write_reg_dword(asd_ha, CSEQ_EST_NEXUS_REQ_COUNT, 0);
 456	asd_write_reg_dword(asd_ha, CSEQ_EST_NEXUS_REQ_COUNT+4, 0);
 457	asd_write_reg_word(asd_ha, CSEQ_Q_EST_NEXUS_HEAD, 0xFFFF);
 458	asd_write_reg_word(asd_ha, CSEQ_Q_EST_NEXUS_TAIL, 0xFFFF);
 459	asd_write_reg_word(asd_ha, CSEQ_NEED_EST_NEXUS_SCB, 0);
 460	asd_write_reg_byte(asd_ha, CSEQ_EST_NEXUS_REQ_HEAD, 0);
 461	asd_write_reg_byte(asd_ha, CSEQ_EST_NEXUS_REQ_TAIL, 0);
 462	asd_write_reg_byte(asd_ha, CSEQ_EST_NEXUS_SCB_OFFSET, 0);
 463
 464	/* CSEQ Mode independent, page 6 setup. */
 465	asd_write_reg_word(asd_ha, CSEQ_INT_ROUT_RET_ADDR0, 0);
 466	asd_write_reg_word(asd_ha, CSEQ_INT_ROUT_RET_ADDR1, 0);
 467	asd_write_reg_word(asd_ha, CSEQ_INT_ROUT_SCBPTR, 0);
 468	asd_write_reg_byte(asd_ha, CSEQ_INT_ROUT_MODE, 0);
 469	asd_write_reg_byte(asd_ha, CSEQ_ISR_SCRATCH_FLAGS, 0);
 470	asd_write_reg_word(asd_ha, CSEQ_ISR_SAVE_SINDEX, 0);
 471	asd_write_reg_word(asd_ha, CSEQ_ISR_SAVE_DINDEX, 0);
 472	asd_write_reg_word(asd_ha, CSEQ_Q_MONIRTT_HEAD, 0xFFFF);
 473	asd_write_reg_word(asd_ha, CSEQ_Q_MONIRTT_TAIL, 0xFFFF);
 474	/* Calculate the free scb mask. */
 475	{
 476		u16 cmdctx = asd_get_cmdctx_size(asd_ha);
 477		cmdctx = (~((cmdctx/128)-1)) >> 8;
 478		asd_write_reg_byte(asd_ha, CSEQ_FREE_SCB_MASK, (u8)cmdctx);
 479	}
 480	asd_write_reg_word(asd_ha, CSEQ_BUILTIN_FREE_SCB_HEAD,
 481			   first_scb_site_no);
 482	asd_write_reg_word(asd_ha, CSEQ_BUILTIN_FREE_SCB_TAIL,
 483			   last_scb_site_no);
 484	asd_write_reg_word(asd_ha, CSEQ_EXTENDED_FREE_SCB_HEAD, 0xFFFF);
 485	asd_write_reg_word(asd_ha, CSEQ_EXTENDED_FREE_SCB_TAIL, 0xFFFF);
 486
 487	/* CSEQ Mode independent, page 7 setup. */
 488	asd_write_reg_dword(asd_ha, CSEQ_EMPTY_REQ_QUEUE, 0);
 489	asd_write_reg_dword(asd_ha, CSEQ_EMPTY_REQ_QUEUE+4, 0);
 490	asd_write_reg_dword(asd_ha, CSEQ_EMPTY_REQ_COUNT, 0);
 491	asd_write_reg_dword(asd_ha, CSEQ_EMPTY_REQ_COUNT+4, 0);
 492	asd_write_reg_word(asd_ha, CSEQ_Q_EMPTY_HEAD, 0xFFFF);
 493	asd_write_reg_word(asd_ha, CSEQ_Q_EMPTY_TAIL, 0xFFFF);
 494	asd_write_reg_word(asd_ha, CSEQ_NEED_EMPTY_SCB, 0);
 495	asd_write_reg_byte(asd_ha, CSEQ_EMPTY_REQ_HEAD, 0);
 496	asd_write_reg_byte(asd_ha, CSEQ_EMPTY_REQ_TAIL, 0);
 497	asd_write_reg_byte(asd_ha, CSEQ_EMPTY_SCB_OFFSET, 0);
 498	asd_write_reg_word(asd_ha, CSEQ_PRIMITIVE_DATA, 0);
 499	asd_write_reg_dword(asd_ha, CSEQ_TIMEOUT_CONST, 0);
 500}
 501
 502/**
 503 * asd_init_cseq_mdp - initialize CSEQ Mode dependent pages
 504 * @asd_ha: pointer to host adapter structure
 505 */
 506static void asd_init_cseq_mdp(struct asd_ha_struct *asd_ha)
 507{
 508	int	i;
 509	int	moffs;
 510
 511	moffs = CSEQ_PAGE_SIZE * 2;
 512
 513	/* CSEQ Mode dependent, modes 0-7, page 0 setup. */
 514	for (i = 0; i < 8; i++) {
 515		asd_write_reg_word(asd_ha, i*moffs+CSEQ_LRM_SAVE_SINDEX, 0);
 516		asd_write_reg_word(asd_ha, i*moffs+CSEQ_LRM_SAVE_SCBPTR, 0);
 517		asd_write_reg_word(asd_ha, i*moffs+CSEQ_Q_LINK_HEAD, 0xFFFF);
 518		asd_write_reg_word(asd_ha, i*moffs+CSEQ_Q_LINK_TAIL, 0xFFFF);
 519		asd_write_reg_byte(asd_ha, i*moffs+CSEQ_LRM_SAVE_SCRPAGE, 0);
 520	}
 521
 522	/* CSEQ Mode dependent, mode 0-7, page 1 and 2 shall be ignored. */
 523
 524	/* CSEQ Mode dependent, mode 8, page 0 setup. */
 525	asd_write_reg_word(asd_ha, CSEQ_RET_ADDR, 0xFFFF);
 526	asd_write_reg_word(asd_ha, CSEQ_RET_SCBPTR, 0);
 527	asd_write_reg_word(asd_ha, CSEQ_SAVE_SCBPTR, 0);
 528	asd_write_reg_word(asd_ha, CSEQ_EMPTY_TRANS_CTX, 0);
 529	asd_write_reg_word(asd_ha, CSEQ_RESP_LEN, 0);
 530	asd_write_reg_word(asd_ha, CSEQ_TMF_SCBPTR, 0);
 531	asd_write_reg_word(asd_ha, CSEQ_GLOBAL_PREV_SCB, 0);
 532	asd_write_reg_word(asd_ha, CSEQ_GLOBAL_HEAD, 0);
 533	asd_write_reg_word(asd_ha, CSEQ_CLEAR_LU_HEAD, 0);
 534	asd_write_reg_byte(asd_ha, CSEQ_TMF_OPCODE, 0);
 535	asd_write_reg_byte(asd_ha, CSEQ_SCRATCH_FLAGS, 0);
 536	asd_write_reg_word(asd_ha, CSEQ_HSB_SITE, 0);
 537	asd_write_reg_word(asd_ha, CSEQ_FIRST_INV_SCB_SITE,
 538			   (u16)last_scb_site_no+1);
 539	asd_write_reg_word(asd_ha, CSEQ_FIRST_INV_DDB_SITE,
 540			   (u16)asd_ha->hw_prof.max_ddbs);
 541
 542	/* CSEQ Mode dependent, mode 8, page 1 setup. */
 543	asd_write_reg_dword(asd_ha, CSEQ_LUN_TO_CLEAR, 0);
 544	asd_write_reg_dword(asd_ha, CSEQ_LUN_TO_CLEAR + 4, 0);
 545	asd_write_reg_dword(asd_ha, CSEQ_LUN_TO_CHECK, 0);
 546	asd_write_reg_dword(asd_ha, CSEQ_LUN_TO_CHECK + 4, 0);
 547
 548	/* CSEQ Mode dependent, mode 8, page 2 setup. */
 549	/* Tell the sequencer the bus address of the first SCB. */
 550	asd_write_reg_addr(asd_ha, CSEQ_HQ_NEW_POINTER,
 551			   asd_ha->seq.next_scb.dma_handle);
 552	ASD_DPRINTK("First SCB dma_handle: 0x%llx\n",
 553		    (unsigned long long)asd_ha->seq.next_scb.dma_handle);
 554
 555	/* Tell the sequencer the first Done List entry address. */
 556	asd_write_reg_addr(asd_ha, CSEQ_HQ_DONE_BASE,
 557			   asd_ha->seq.actual_dl->dma_handle);
 558
 559	/* Initialize the Q_DONE_POINTER with the least significant
 560	 * 4 bytes of the first Done List address. */
 561	asd_write_reg_dword(asd_ha, CSEQ_HQ_DONE_POINTER,
 562			    ASD_BUSADDR_LO(asd_ha->seq.actual_dl->dma_handle));
 563
 564	asd_write_reg_byte(asd_ha, CSEQ_HQ_DONE_PASS, ASD_DEF_DL_TOGGLE);
 565
 566	/* CSEQ Mode dependent, mode 8, page 3 shall be ignored. */
 567}
 568
 569/**
 570 * asd_init_cseq_scratch -- setup and init CSEQ
 571 * @asd_ha: pointer to host adapter structure
 572 *
 573 * Setup and initialize Central sequencers. Initialize the mode
 574 * independent and dependent scratch page to the default settings.
 575 */
 576static void asd_init_cseq_scratch(struct asd_ha_struct *asd_ha)
 577{
 578	asd_init_cseq_mip(asd_ha);
 579	asd_init_cseq_mdp(asd_ha);
 580}
 581
 582/**
 583 * asd_init_lseq_mip -- initialize LSEQ Mode independent pages 0-3
 584 * @asd_ha: pointer to host adapter structure
 585 */
 586static void asd_init_lseq_mip(struct asd_ha_struct *asd_ha, u8 lseq)
 587{
 588	int i;
 589
 590	/* LSEQ Mode independent page 0 setup. */
 591	asd_write_reg_word(asd_ha, LmSEQ_Q_TGTXFR_HEAD(lseq), 0xFFFF);
 592	asd_write_reg_word(asd_ha, LmSEQ_Q_TGTXFR_TAIL(lseq), 0xFFFF);
 593	asd_write_reg_byte(asd_ha, LmSEQ_LINK_NUMBER(lseq), lseq);
 594	asd_write_reg_byte(asd_ha, LmSEQ_SCRATCH_FLAGS(lseq),
 595			   ASD_NOTIFY_ENABLE_SPINUP);
 596	asd_write_reg_dword(asd_ha, LmSEQ_CONNECTION_STATE(lseq),0x08000000);
 597	asd_write_reg_word(asd_ha, LmSEQ_CONCTL(lseq), 0);
 598	asd_write_reg_byte(asd_ha, LmSEQ_CONSTAT(lseq), 0);
 599	asd_write_reg_byte(asd_ha, LmSEQ_CONNECTION_MODES(lseq), 0);
 600	asd_write_reg_word(asd_ha, LmSEQ_REG1_ISR(lseq), 0);
 601	asd_write_reg_word(asd_ha, LmSEQ_REG2_ISR(lseq), 0);
 602	asd_write_reg_word(asd_ha, LmSEQ_REG3_ISR(lseq), 0);
 603	asd_write_reg_dword(asd_ha, LmSEQ_REG0_ISR(lseq), 0);
 604	asd_write_reg_dword(asd_ha, LmSEQ_REG0_ISR(lseq)+4, 0);
 605
 606	/* LSEQ Mode independent page 1 setup. */
 607	asd_write_reg_word(asd_ha, LmSEQ_EST_NEXUS_SCBPTR0(lseq), 0xFFFF);
 608	asd_write_reg_word(asd_ha, LmSEQ_EST_NEXUS_SCBPTR1(lseq), 0xFFFF);
 609	asd_write_reg_word(asd_ha, LmSEQ_EST_NEXUS_SCBPTR2(lseq), 0xFFFF);
 610	asd_write_reg_word(asd_ha, LmSEQ_EST_NEXUS_SCBPTR3(lseq), 0xFFFF);
 611	asd_write_reg_byte(asd_ha, LmSEQ_EST_NEXUS_SCB_OPCODE0(lseq), 0);
 612	asd_write_reg_byte(asd_ha, LmSEQ_EST_NEXUS_SCB_OPCODE1(lseq), 0);
 613	asd_write_reg_byte(asd_ha, LmSEQ_EST_NEXUS_SCB_OPCODE2(lseq), 0);
 614	asd_write_reg_byte(asd_ha, LmSEQ_EST_NEXUS_SCB_OPCODE3(lseq), 0);
 615	asd_write_reg_byte(asd_ha, LmSEQ_EST_NEXUS_SCB_HEAD(lseq), 0);
 616	asd_write_reg_byte(asd_ha, LmSEQ_EST_NEXUS_SCB_TAIL(lseq), 0);
 617	asd_write_reg_byte(asd_ha, LmSEQ_EST_NEXUS_BUF_AVAIL(lseq), 0);
 618	asd_write_reg_dword(asd_ha, LmSEQ_TIMEOUT_CONST(lseq), 0);
 619	asd_write_reg_word(asd_ha, LmSEQ_ISR_SAVE_SINDEX(lseq), 0);
 620	asd_write_reg_word(asd_ha, LmSEQ_ISR_SAVE_DINDEX(lseq), 0);
 621
 622	/* LSEQ Mode Independent page 2 setup. */
 623	asd_write_reg_word(asd_ha, LmSEQ_EMPTY_SCB_PTR0(lseq), 0xFFFF);
 624	asd_write_reg_word(asd_ha, LmSEQ_EMPTY_SCB_PTR1(lseq), 0xFFFF);
 625	asd_write_reg_word(asd_ha, LmSEQ_EMPTY_SCB_PTR2(lseq), 0xFFFF);
 626	asd_write_reg_word(asd_ha, LmSEQ_EMPTY_SCB_PTR3(lseq), 0xFFFF);
 627	asd_write_reg_byte(asd_ha, LmSEQ_EMPTY_SCB_OPCD0(lseq), 0);
 628	asd_write_reg_byte(asd_ha, LmSEQ_EMPTY_SCB_OPCD1(lseq), 0);
 629	asd_write_reg_byte(asd_ha, LmSEQ_EMPTY_SCB_OPCD2(lseq), 0);
 630	asd_write_reg_byte(asd_ha, LmSEQ_EMPTY_SCB_OPCD3(lseq), 0);
 631	asd_write_reg_byte(asd_ha, LmSEQ_EMPTY_SCB_HEAD(lseq), 0);
 632	asd_write_reg_byte(asd_ha, LmSEQ_EMPTY_SCB_TAIL(lseq), 0);
 633	asd_write_reg_byte(asd_ha, LmSEQ_EMPTY_BUFS_AVAIL(lseq), 0);
 634	for (i = 0; i < 12; i += 4)
 635		asd_write_reg_dword(asd_ha, LmSEQ_ATA_SCR_REGS(lseq) + i, 0);
 636
 637	/* LSEQ Mode Independent page 3 setup. */
 638
 639	/* Device present timer timeout */
 640	asd_write_reg_dword(asd_ha, LmSEQ_DEV_PRES_TMR_TOUT_CONST(lseq),
 641			    ASD_DEV_PRESENT_TIMEOUT);
 642
 643	/* SATA interlock timer disabled */
 644	asd_write_reg_dword(asd_ha, LmSEQ_SATA_INTERLOCK_TIMEOUT(lseq),
 645			    ASD_SATA_INTERLOCK_TIMEOUT);
 646
 647	/* STP shutdown timer timeout constant, IGNORED by the sequencer,
 648	 * always 0. */
 649	asd_write_reg_dword(asd_ha, LmSEQ_STP_SHUTDOWN_TIMEOUT(lseq),
 650			    ASD_STP_SHUTDOWN_TIMEOUT);
 651
 652	asd_write_reg_dword(asd_ha, LmSEQ_SRST_ASSERT_TIMEOUT(lseq),
 653			    ASD_SRST_ASSERT_TIMEOUT);
 654
 655	asd_write_reg_dword(asd_ha, LmSEQ_RCV_FIS_TIMEOUT(lseq),
 656			    ASD_RCV_FIS_TIMEOUT);
 657
 658	asd_write_reg_dword(asd_ha, LmSEQ_ONE_MILLISEC_TIMEOUT(lseq),
 659			    ASD_ONE_MILLISEC_TIMEOUT);
 660
 661	/* COM_INIT timer */
 662	asd_write_reg_dword(asd_ha, LmSEQ_TEN_MS_COMINIT_TIMEOUT(lseq),
 663			    ASD_TEN_MILLISEC_TIMEOUT);
 664
 665	asd_write_reg_dword(asd_ha, LmSEQ_SMP_RCV_TIMEOUT(lseq),
 666			    ASD_SMP_RCV_TIMEOUT);
 667}
 668
 669/**
 670 * asd_init_lseq_mdp -- initialize LSEQ mode dependent pages.
 671 * @asd_ha: pointer to host adapter structure
 672 */
 673static void asd_init_lseq_mdp(struct asd_ha_struct *asd_ha,  int lseq)
 674{
 675	int    i;
 676	u32    moffs;
 677	u16 ret_addr[] = {
 678		0xFFFF,		  /* mode 0 */
 679		0xFFFF,		  /* mode 1 */
 680		mode2_task,	  /* mode 2 */
 681		0,
 682		0xFFFF,		  /* mode 4/5 */
 683		0xFFFF,		  /* mode 4/5 */
 684	};
 685
 686	/*
 687	 * Mode 0,1,2 and 4/5 have common field on page 0 for the first
 688	 * 14 bytes.
 689	 */
 690	for (i = 0; i < 3; i++) {
 691		moffs = i * LSEQ_MODE_SCRATCH_SIZE;
 692		asd_write_reg_word(asd_ha, LmSEQ_RET_ADDR(lseq)+moffs,
 693				   ret_addr[i]);
 694		asd_write_reg_word(asd_ha, LmSEQ_REG0_MODE(lseq)+moffs, 0);
 695		asd_write_reg_word(asd_ha, LmSEQ_MODE_FLAGS(lseq)+moffs, 0);
 696		asd_write_reg_word(asd_ha, LmSEQ_RET_ADDR2(lseq)+moffs,0xFFFF);
 697		asd_write_reg_word(asd_ha, LmSEQ_RET_ADDR1(lseq)+moffs,0xFFFF);
 698		asd_write_reg_byte(asd_ha, LmSEQ_OPCODE_TO_CSEQ(lseq)+moffs,0);
 699		asd_write_reg_word(asd_ha, LmSEQ_DATA_TO_CSEQ(lseq)+moffs,0);
 700	}
 701	/*
 702	 *  Mode 5 page 0 overlaps the same scratch page with Mode 0 page 3.
 703	 */
 704	asd_write_reg_word(asd_ha,
 705			 LmSEQ_RET_ADDR(lseq)+LSEQ_MODE5_PAGE0_OFFSET,
 706			   ret_addr[5]);
 707	asd_write_reg_word(asd_ha,
 708			 LmSEQ_REG0_MODE(lseq)+LSEQ_MODE5_PAGE0_OFFSET,0);
 709	asd_write_reg_word(asd_ha,
 710			 LmSEQ_MODE_FLAGS(lseq)+LSEQ_MODE5_PAGE0_OFFSET, 0);
 711	asd_write_reg_word(asd_ha,
 712			 LmSEQ_RET_ADDR2(lseq)+LSEQ_MODE5_PAGE0_OFFSET,0xFFFF);
 713	asd_write_reg_word(asd_ha,
 714			 LmSEQ_RET_ADDR1(lseq)+LSEQ_MODE5_PAGE0_OFFSET,0xFFFF);
 715	asd_write_reg_byte(asd_ha,
 716		         LmSEQ_OPCODE_TO_CSEQ(lseq)+LSEQ_MODE5_PAGE0_OFFSET,0);
 717	asd_write_reg_word(asd_ha,
 718		         LmSEQ_DATA_TO_CSEQ(lseq)+LSEQ_MODE5_PAGE0_OFFSET, 0);
 719
 720	/* LSEQ Mode dependent 0, page 0 setup. */
 721	asd_write_reg_word(asd_ha, LmSEQ_FIRST_INV_DDB_SITE(lseq),
 722			   (u16)asd_ha->hw_prof.max_ddbs);
 723	asd_write_reg_word(asd_ha, LmSEQ_EMPTY_TRANS_CTX(lseq), 0);
 724	asd_write_reg_word(asd_ha, LmSEQ_RESP_LEN(lseq), 0);
 725	asd_write_reg_word(asd_ha, LmSEQ_FIRST_INV_SCB_SITE(lseq),
 726			   (u16)last_scb_site_no+1);
 727	asd_write_reg_word(asd_ha, LmSEQ_INTEN_SAVE(lseq),
 728			    (u16) ((LmM0INTEN_MASK & 0xFFFF0000) >> 16));
 729	asd_write_reg_word(asd_ha, LmSEQ_INTEN_SAVE(lseq) + 2,
 730			    (u16) LmM0INTEN_MASK & 0xFFFF);
 731	asd_write_reg_byte(asd_ha, LmSEQ_LINK_RST_FRM_LEN(lseq), 0);
 732	asd_write_reg_byte(asd_ha, LmSEQ_LINK_RST_PROTOCOL(lseq), 0);
 733	asd_write_reg_byte(asd_ha, LmSEQ_RESP_STATUS(lseq), 0);
 734	asd_write_reg_byte(asd_ha, LmSEQ_LAST_LOADED_SGE(lseq), 0);
 735	asd_write_reg_word(asd_ha, LmSEQ_SAVE_SCBPTR(lseq), 0);
 736
 737	/* LSEQ mode dependent, mode 1, page 0 setup. */
 738	asd_write_reg_word(asd_ha, LmSEQ_Q_XMIT_HEAD(lseq), 0xFFFF);
 739	asd_write_reg_word(asd_ha, LmSEQ_M1_EMPTY_TRANS_CTX(lseq), 0);
 740	asd_write_reg_word(asd_ha, LmSEQ_INI_CONN_TAG(lseq), 0);
 741	asd_write_reg_byte(asd_ha, LmSEQ_FAILED_OPEN_STATUS(lseq), 0);
 742	asd_write_reg_byte(asd_ha, LmSEQ_XMIT_REQUEST_TYPE(lseq), 0);
 743	asd_write_reg_byte(asd_ha, LmSEQ_M1_RESP_STATUS(lseq), 0);
 744	asd_write_reg_byte(asd_ha, LmSEQ_M1_LAST_LOADED_SGE(lseq), 0);
 745	asd_write_reg_word(asd_ha, LmSEQ_M1_SAVE_SCBPTR(lseq), 0);
 746
 747	/* LSEQ Mode dependent mode 2, page 0 setup */
 748	asd_write_reg_word(asd_ha, LmSEQ_PORT_COUNTER(lseq), 0);
 749	asd_write_reg_word(asd_ha, LmSEQ_PM_TABLE_PTR(lseq), 0);
 750	asd_write_reg_word(asd_ha, LmSEQ_SATA_INTERLOCK_TMR_SAVE(lseq), 0);
 751	asd_write_reg_word(asd_ha, LmSEQ_IP_BITL(lseq), 0);
 752	asd_write_reg_word(asd_ha, LmSEQ_COPY_SMP_CONN_TAG(lseq), 0);
 753	asd_write_reg_byte(asd_ha, LmSEQ_P0M2_OFFS1AH(lseq), 0);
 754
 755	/* LSEQ Mode dependent, mode 4/5, page 0 setup. */
 756	asd_write_reg_byte(asd_ha, LmSEQ_SAVED_OOB_STATUS(lseq), 0);
 757	asd_write_reg_byte(asd_ha, LmSEQ_SAVED_OOB_MODE(lseq), 0);
 758	asd_write_reg_word(asd_ha, LmSEQ_Q_LINK_HEAD(lseq), 0xFFFF);
 759	asd_write_reg_byte(asd_ha, LmSEQ_LINK_RST_ERR(lseq), 0);
 760	asd_write_reg_byte(asd_ha, LmSEQ_SAVED_OOB_SIGNALS(lseq), 0);
 761	asd_write_reg_byte(asd_ha, LmSEQ_SAS_RESET_MODE(lseq), 0);
 762	asd_write_reg_byte(asd_ha, LmSEQ_LINK_RESET_RETRY_COUNT(lseq), 0);
 763	asd_write_reg_byte(asd_ha, LmSEQ_NUM_LINK_RESET_RETRIES(lseq), 0);
 764	asd_write_reg_word(asd_ha, LmSEQ_OOB_INT_ENABLES(lseq), 0);
 765	/*
 766	 * Set the desired interval between transmissions of the NOTIFY
 767	 * (ENABLE SPINUP) primitive.  Must be initialized to val - 1.
 768	 */
 769	asd_write_reg_word(asd_ha, LmSEQ_NOTIFY_TIMER_TIMEOUT(lseq),
 770			   ASD_NOTIFY_TIMEOUT - 1);
 771	/* No delay for the first NOTIFY to be sent to the attached target. */
 772	asd_write_reg_word(asd_ha, LmSEQ_NOTIFY_TIMER_DOWN_COUNT(lseq),
 773			   ASD_NOTIFY_DOWN_COUNT);
 774	asd_write_reg_word(asd_ha, LmSEQ_NOTIFY_TIMER_INITIAL_COUNT(lseq),
 775			   ASD_NOTIFY_DOWN_COUNT);
 776
 777	/* LSEQ Mode dependent, mode 0 and 1, page 1 setup. */
 778	for (i = 0; i < 2; i++)	{
 779		int j;
 780		/* Start from Page 1 of Mode 0 and 1. */
 781		moffs = LSEQ_PAGE_SIZE + i*LSEQ_MODE_SCRATCH_SIZE;
 782		/* All the fields of page 1 can be initialized to 0. */
 783		for (j = 0; j < LSEQ_PAGE_SIZE; j += 4)
 784			asd_write_reg_dword(asd_ha, LmSCRATCH(lseq)+moffs+j,0);
 785	}
 786
 787	/* LSEQ Mode dependent, mode 2, page 1 setup. */
 788	asd_write_reg_dword(asd_ha, LmSEQ_INVALID_DWORD_COUNT(lseq), 0);
 789	asd_write_reg_dword(asd_ha, LmSEQ_DISPARITY_ERROR_COUNT(lseq), 0);
 790	asd_write_reg_dword(asd_ha, LmSEQ_LOSS_OF_SYNC_COUNT(lseq), 0);
 791
 792	/* LSEQ Mode dependent, mode 4/5, page 1. */
 793	for (i = 0; i < LSEQ_PAGE_SIZE; i+=4)
 794		asd_write_reg_dword(asd_ha, LmSEQ_FRAME_TYPE_MASK(lseq)+i, 0);
 795	asd_write_reg_byte(asd_ha, LmSEQ_FRAME_TYPE_MASK(lseq), 0xFF);
 796	asd_write_reg_byte(asd_ha, LmSEQ_HASHED_DEST_ADDR_MASK(lseq), 0xFF);
 797	asd_write_reg_byte(asd_ha, LmSEQ_HASHED_DEST_ADDR_MASK(lseq)+1,0xFF);
 798	asd_write_reg_byte(asd_ha, LmSEQ_HASHED_DEST_ADDR_MASK(lseq)+2,0xFF);
 799	asd_write_reg_byte(asd_ha, LmSEQ_HASHED_SRC_ADDR_MASK(lseq), 0xFF);
 800	asd_write_reg_byte(asd_ha, LmSEQ_HASHED_SRC_ADDR_MASK(lseq)+1, 0xFF);
 801	asd_write_reg_byte(asd_ha, LmSEQ_HASHED_SRC_ADDR_MASK(lseq)+2, 0xFF);
 802	asd_write_reg_dword(asd_ha, LmSEQ_DATA_OFFSET(lseq), 0xFFFFFFFF);
 803
 804	/* LSEQ Mode dependent, mode 0, page 2 setup. */
 805	asd_write_reg_dword(asd_ha, LmSEQ_SMP_RCV_TIMER_TERM_TS(lseq), 0);
 806	asd_write_reg_byte(asd_ha, LmSEQ_DEVICE_BITS(lseq), 0);
 807	asd_write_reg_word(asd_ha, LmSEQ_SDB_DDB(lseq), 0);
 808	asd_write_reg_byte(asd_ha, LmSEQ_SDB_NUM_TAGS(lseq), 0);
 809	asd_write_reg_byte(asd_ha, LmSEQ_SDB_CURR_TAG(lseq), 0);
 810
 811	/* LSEQ Mode Dependent 1, page 2 setup. */
 812	asd_write_reg_dword(asd_ha, LmSEQ_TX_ID_ADDR_FRAME(lseq), 0);
 813	asd_write_reg_dword(asd_ha, LmSEQ_TX_ID_ADDR_FRAME(lseq)+4, 0);
 814	asd_write_reg_dword(asd_ha, LmSEQ_OPEN_TIMER_TERM_TS(lseq), 0);
 815	asd_write_reg_dword(asd_ha, LmSEQ_SRST_AS_TIMER_TERM_TS(lseq), 0);
 816	asd_write_reg_dword(asd_ha, LmSEQ_LAST_LOADED_SG_EL(lseq), 0);
 817
 818	/* LSEQ Mode Dependent 2, page 2 setup. */
 819	/* The LmSEQ_STP_SHUTDOWN_TIMER_TERM_TS is IGNORED by the sequencer,
 820	 * i.e. always 0. */
 821	asd_write_reg_dword(asd_ha, LmSEQ_STP_SHUTDOWN_TIMER_TERM_TS(lseq),0);
 822	asd_write_reg_dword(asd_ha, LmSEQ_CLOSE_TIMER_TERM_TS(lseq), 0);
 823	asd_write_reg_dword(asd_ha, LmSEQ_BREAK_TIMER_TERM_TS(lseq), 0);
 824	asd_write_reg_dword(asd_ha, LmSEQ_DWS_RESET_TIMER_TERM_TS(lseq), 0);
 825	asd_write_reg_dword(asd_ha,LmSEQ_SATA_INTERLOCK_TIMER_TERM_TS(lseq),0);
 826	asd_write_reg_dword(asd_ha, LmSEQ_MCTL_TIMER_TERM_TS(lseq), 0);
 827
 828	/* LSEQ Mode Dependent 4/5, page 2 setup. */
 829	asd_write_reg_dword(asd_ha, LmSEQ_COMINIT_TIMER_TERM_TS(lseq), 0);
 830	asd_write_reg_dword(asd_ha, LmSEQ_RCV_ID_TIMER_TERM_TS(lseq), 0);
 831	asd_write_reg_dword(asd_ha, LmSEQ_RCV_FIS_TIMER_TERM_TS(lseq), 0);
 832	asd_write_reg_dword(asd_ha, LmSEQ_DEV_PRES_TIMER_TERM_TS(lseq),	0);
 833}
 834
 835/**
 836 * asd_init_lseq_scratch -- setup and init link sequencers
 837 * @asd_ha: pointer to host adapter struct
 838 */
 839static void asd_init_lseq_scratch(struct asd_ha_struct *asd_ha)
 840{
 841	u8 lseq;
 842	u8 lseq_mask;
 843
 844	lseq_mask = asd_ha->hw_prof.enabled_phys;
 845	for_each_sequencer(lseq_mask, lseq_mask, lseq) {
 846		asd_init_lseq_mip(asd_ha, lseq);
 847		asd_init_lseq_mdp(asd_ha, lseq);
 848	}
 849}
 850
 851/**
 852 * asd_init_scb_sites -- initialize sequencer SCB sites (memory).
 853 * @asd_ha: pointer to host adapter structure
 854 *
 855 * This should be done before initializing common CSEQ and LSEQ
 856 * scratch since those areas depend on some computed values here,
 857 * last_scb_site_no, etc.
 858 */
 859static void asd_init_scb_sites(struct asd_ha_struct *asd_ha)
 860{
 861	u16	site_no;
 862	u16     max_scbs = 0;
 863
 864	for (site_no = asd_ha->hw_prof.max_scbs-1;
 865	     site_no != (u16) -1;
 866	     site_no--) {
 867		u16	i;
 868
 869		/* Initialize all fields in the SCB site to 0. */
 870		for (i = 0; i < ASD_SCB_SIZE; i += 4)
 871			asd_scbsite_write_dword(asd_ha, site_no, i, 0);
 872
 873		/* Initialize SCB Site Opcode field to invalid. */
 874		asd_scbsite_write_byte(asd_ha, site_no,
 875				       offsetof(struct scb_header, opcode),
 876				       0xFF);
 877
 878		/* Initialize SCB Site Flags field to mean a response
 879		 * frame has been received.  This means inadvertent
 880		 * frames received to be dropped. */
 881		asd_scbsite_write_byte(asd_ha, site_no, 0x49, 0x01);
 882
 883		/* Workaround needed by SEQ to fix a SATA issue is to exclude
 884		 * certain SCB sites from the free list. */
 885		if (!SCB_SITE_VALID(site_no))
 886			continue;
 887
 888		if (last_scb_site_no == 0)
 889			last_scb_site_no = site_no;
 890
 891		/* For every SCB site, we need to initialize the
 892		 * following fields: Q_NEXT, SCB_OPCODE, SCB_FLAGS,
 893		 * and SG Element Flag. */
 894
 895		/* Q_NEXT field of the last SCB is invalidated. */
 896		asd_scbsite_write_word(asd_ha, site_no, 0, first_scb_site_no);
 897
 898		first_scb_site_no = site_no;
 899		max_scbs++;
 900	}
 901	asd_ha->hw_prof.max_scbs = max_scbs;
 902	ASD_DPRINTK("max_scbs:%d\n", asd_ha->hw_prof.max_scbs);
 903	ASD_DPRINTK("first_scb_site_no:0x%x\n", first_scb_site_no);
 904	ASD_DPRINTK("last_scb_site_no:0x%x\n", last_scb_site_no);
 905}
 906
 907/**
 908 * asd_init_cseq_cio - initialize CSEQ CIO registers
 909 * @asd_ha: pointer to host adapter structure
 910 */
 911static void asd_init_cseq_cio(struct asd_ha_struct *asd_ha)
 912{
 913	int i;
 914
 915	asd_write_reg_byte(asd_ha, CSEQCOMINTEN, 0);
 916	asd_write_reg_byte(asd_ha, CSEQDLCTL, ASD_DL_SIZE_BITS);
 917	asd_write_reg_byte(asd_ha, CSEQDLOFFS, 0);
 918	asd_write_reg_byte(asd_ha, CSEQDLOFFS+1, 0);
 919	asd_ha->seq.scbpro = 0;
 920	asd_write_reg_dword(asd_ha, SCBPRO, 0);
 921	asd_write_reg_dword(asd_ha, CSEQCON, 0);
 922
 923	/* Initialize CSEQ Mode 11 Interrupt Vectors.
 924	 * The addresses are 16 bit wide and in dword units.
 925	 * The values of their macros are in byte units.
 926	 * Thus we have to divide by 4. */
 927	asd_write_reg_word(asd_ha, CM11INTVEC0, cseq_vecs[0]);
 928	asd_write_reg_word(asd_ha, CM11INTVEC1, cseq_vecs[1]);
 929	asd_write_reg_word(asd_ha, CM11INTVEC2, cseq_vecs[2]);
 930
 931	/* Enable ARP2HALTC (ARP2 Halted from Halt Code Write). */
 932	asd_write_reg_byte(asd_ha, CARP2INTEN, EN_ARP2HALTC);
 933
 934	/* Initialize CSEQ Scratch Page to 0x04. */
 935	asd_write_reg_byte(asd_ha, CSCRATCHPAGE, 0x04);
 936
 937	/* Initialize CSEQ Mode[0-8] Dependent registers. */
 938	/* Initialize Scratch Page to 0. */
 939	for (i = 0; i < 9; i++)
 940		asd_write_reg_byte(asd_ha, CMnSCRATCHPAGE(i), 0);
 941
 942	/* Reset the ARP2 Program Count. */
 943	asd_write_reg_word(asd_ha, CPRGMCNT, cseq_idle_loop);
 944
 945	for (i = 0; i < 8; i++) {
 946		/* Initialize Mode n Link m Interrupt Enable. */
 947		asd_write_reg_dword(asd_ha, CMnINTEN(i), EN_CMnRSPMBXF);
 948		/* Initialize Mode n Request Mailbox. */
 949		asd_write_reg_dword(asd_ha, CMnREQMBX(i), 0);
 950	}
 951}
 952
 953/**
 954 * asd_init_lseq_cio -- initialize LmSEQ CIO registers
 955 * @asd_ha: pointer to host adapter structure
 956 */
 957static void asd_init_lseq_cio(struct asd_ha_struct *asd_ha, int lseq)
 958{
 959	u8  *sas_addr;
 960	int  i;
 961
 962	/* Enable ARP2HALTC (ARP2 Halted from Halt Code Write). */
 963	asd_write_reg_dword(asd_ha, LmARP2INTEN(lseq), EN_ARP2HALTC);
 964
 965	asd_write_reg_byte(asd_ha, LmSCRATCHPAGE(lseq), 0);
 966
 967	/* Initialize Mode 0,1, and 2 SCRATCHPAGE to 0. */
 968	for (i = 0; i < 3; i++)
 969		asd_write_reg_byte(asd_ha, LmMnSCRATCHPAGE(lseq, i), 0);
 970
 971	/* Initialize Mode 5 SCRATCHPAGE to 0. */
 972	asd_write_reg_byte(asd_ha, LmMnSCRATCHPAGE(lseq, 5), 0);
 973
 974	asd_write_reg_dword(asd_ha, LmRSPMBX(lseq), 0);
 975	/* Initialize Mode 0,1,2 and 5 Interrupt Enable and
 976	 * Interrupt registers. */
 977	asd_write_reg_dword(asd_ha, LmMnINTEN(lseq, 0), LmM0INTEN_MASK);
 978	asd_write_reg_dword(asd_ha, LmMnINT(lseq, 0), 0xFFFFFFFF);
 979	/* Mode 1 */
 980	asd_write_reg_dword(asd_ha, LmMnINTEN(lseq, 1), LmM1INTEN_MASK);
 981	asd_write_reg_dword(asd_ha, LmMnINT(lseq, 1), 0xFFFFFFFF);
 982	/* Mode 2 */
 983	asd_write_reg_dword(asd_ha, LmMnINTEN(lseq, 2), LmM2INTEN_MASK);
 984	asd_write_reg_dword(asd_ha, LmMnINT(lseq, 2), 0xFFFFFFFF);
 985	/* Mode 5 */
 986	asd_write_reg_dword(asd_ha, LmMnINTEN(lseq, 5), LmM5INTEN_MASK);
 987	asd_write_reg_dword(asd_ha, LmMnINT(lseq, 5), 0xFFFFFFFF);
 988
 989	/* Enable HW Timer status. */
 990	asd_write_reg_byte(asd_ha, LmHWTSTATEN(lseq), LmHWTSTATEN_MASK);
 991
 992	/* Enable Primitive Status 0 and 1. */
 993	asd_write_reg_dword(asd_ha, LmPRIMSTAT0EN(lseq), LmPRIMSTAT0EN_MASK);
 994	asd_write_reg_dword(asd_ha, LmPRIMSTAT1EN(lseq), LmPRIMSTAT1EN_MASK);
 995
 996	/* Enable Frame Error. */
 997	asd_write_reg_dword(asd_ha, LmFRMERREN(lseq), LmFRMERREN_MASK);
 998	asd_write_reg_byte(asd_ha, LmMnHOLDLVL(lseq, 0), 0x50);
 999
1000	/* Initialize Mode 0 Transfer Level to 512. */
1001	asd_write_reg_byte(asd_ha,  LmMnXFRLVL(lseq, 0), LmMnXFRLVL_512);
1002	/* Initialize Mode 1 Transfer Level to 256. */
1003	asd_write_reg_byte(asd_ha, LmMnXFRLVL(lseq, 1), LmMnXFRLVL_256);
1004
1005	/* Initialize Program Count. */
1006	asd_write_reg_word(asd_ha, LmPRGMCNT(lseq), lseq_idle_loop);
1007
1008	/* Enable Blind SG Move. */
1009	asd_write_reg_dword(asd_ha, LmMODECTL(lseq), LmBLIND48);
1010	asd_write_reg_word(asd_ha, LmM3SATATIMER(lseq),
1011			   ASD_SATA_INTERLOCK_TIMEOUT);
1012
1013	(void) asd_read_reg_dword(asd_ha, LmREQMBX(lseq));
1014
1015	/* Clear Primitive Status 0 and 1. */
1016	asd_write_reg_dword(asd_ha, LmPRMSTAT0(lseq), 0xFFFFFFFF);
1017	asd_write_reg_dword(asd_ha, LmPRMSTAT1(lseq), 0xFFFFFFFF);
1018
1019	/* Clear HW Timer status. */
1020	asd_write_reg_byte(asd_ha, LmHWTSTAT(lseq), 0xFF);
1021
1022	/* Clear DMA Errors for Mode 0 and 1. */
1023	asd_write_reg_byte(asd_ha, LmMnDMAERRS(lseq, 0), 0xFF);
1024	asd_write_reg_byte(asd_ha, LmMnDMAERRS(lseq, 1), 0xFF);
1025
1026	/* Clear SG DMA Errors for Mode 0 and 1. */
1027	asd_write_reg_byte(asd_ha, LmMnSGDMAERRS(lseq, 0), 0xFF);
1028	asd_write_reg_byte(asd_ha, LmMnSGDMAERRS(lseq, 1), 0xFF);
1029
1030	/* Clear Mode 0 Buffer Parity Error. */
1031	asd_write_reg_byte(asd_ha, LmMnBUFSTAT(lseq, 0), LmMnBUFPERR);
1032
1033	/* Clear Mode 0 Frame Error register. */
1034	asd_write_reg_dword(asd_ha, LmMnFRMERR(lseq, 0), 0xFFFFFFFF);
1035
1036	/* Reset LSEQ external interrupt arbiter. */
1037	asd_write_reg_byte(asd_ha, LmARP2INTCTL(lseq), RSTINTCTL);
1038
1039	/* Set the Phy SAS for the LmSEQ WWN. */
1040	sas_addr = asd_ha->phys[lseq].phy_desc->sas_addr;
1041	for (i = 0; i < SAS_ADDR_SIZE; i++)
1042		asd_write_reg_byte(asd_ha, LmWWN(lseq) + i, sas_addr[i]);
1043
1044	/* Set the Transmit Size to 1024 bytes, 0 = 256 Dwords. */
1045	asd_write_reg_byte(asd_ha, LmMnXMTSIZE(lseq, 1), 0);
1046
1047	/* Set the Bus Inactivity Time Limit Timer. */
1048	asd_write_reg_word(asd_ha, LmBITL_TIMER(lseq), 9);
1049
1050	/* Enable SATA Port Multiplier. */
1051	asd_write_reg_byte(asd_ha, LmMnSATAFS(lseq, 1), 0x80);
1052
1053	/* Initialize Interrupt Vector[0-10] address in Mode 3.
1054	 * See the comment on CSEQ_INT_* */
1055	asd_write_reg_word(asd_ha, LmM3INTVEC0(lseq), lseq_vecs[0]);
1056	asd_write_reg_word(asd_ha, LmM3INTVEC1(lseq), lseq_vecs[1]);
1057	asd_write_reg_word(asd_ha, LmM3INTVEC2(lseq), lseq_vecs[2]);
1058	asd_write_reg_word(asd_ha, LmM3INTVEC3(lseq), lseq_vecs[3]);
1059	asd_write_reg_word(asd_ha, LmM3INTVEC4(lseq), lseq_vecs[4]);
1060	asd_write_reg_word(asd_ha, LmM3INTVEC5(lseq), lseq_vecs[5]);
1061	asd_write_reg_word(asd_ha, LmM3INTVEC6(lseq), lseq_vecs[6]);
1062	asd_write_reg_word(asd_ha, LmM3INTVEC7(lseq), lseq_vecs[7]);
1063	asd_write_reg_word(asd_ha, LmM3INTVEC8(lseq), lseq_vecs[8]);
1064	asd_write_reg_word(asd_ha, LmM3INTVEC9(lseq), lseq_vecs[9]);
1065	asd_write_reg_word(asd_ha, LmM3INTVEC10(lseq), lseq_vecs[10]);
1066	/*
1067	 * Program the Link LED control, applicable only for
1068	 * Chip Rev. B or later.
1069	 */
1070	asd_write_reg_dword(asd_ha, LmCONTROL(lseq),
1071			    (LEDTIMER | LEDMODE_TXRX | LEDTIMERS_100ms));
1072
1073	/* Set the Align Rate for SAS and STP mode. */
1074	asd_write_reg_byte(asd_ha, LmM1SASALIGN(lseq), SAS_ALIGN_DEFAULT);
1075	asd_write_reg_byte(asd_ha, LmM1STPALIGN(lseq), STP_ALIGN_DEFAULT);
1076}
1077
1078
1079/**
1080 * asd_post_init_cseq -- clear CSEQ Mode n Int. status and Response mailbox
1081 * @asd_ha: pointer to host adapter struct
1082 */
1083static void asd_post_init_cseq(struct asd_ha_struct *asd_ha)
1084{
1085	int i;
1086
1087	for (i = 0; i < 8; i++)
1088		asd_write_reg_dword(asd_ha, CMnINT(i), 0xFFFFFFFF);
1089	for (i = 0; i < 8; i++)
1090		asd_read_reg_dword(asd_ha, CMnRSPMBX(i));
1091	/* Reset the external interrupt arbiter. */
1092	asd_write_reg_byte(asd_ha, CARP2INTCTL, RSTINTCTL);
1093}
1094
1095/**
1096 * asd_init_ddb_0 -- initialize DDB 0
1097 * @asd_ha: pointer to host adapter structure
1098 *
1099 * Initialize DDB site 0 which is used internally by the sequencer.
1100 */
1101static void asd_init_ddb_0(struct asd_ha_struct *asd_ha)
1102{
1103	int	i;
1104
1105	/* Zero out the DDB explicitly */
1106	for (i = 0; i < sizeof(struct asd_ddb_seq_shared); i+=4)
1107		asd_ddbsite_write_dword(asd_ha, 0, i, 0);
1108
1109	asd_ddbsite_write_word(asd_ha, 0,
1110		 offsetof(struct asd_ddb_seq_shared, q_free_ddb_head), 0);
1111	asd_ddbsite_write_word(asd_ha, 0,
1112		 offsetof(struct asd_ddb_seq_shared, q_free_ddb_tail),
1113			       asd_ha->hw_prof.max_ddbs-1);
1114	asd_ddbsite_write_word(asd_ha, 0,
1115		 offsetof(struct asd_ddb_seq_shared, q_free_ddb_cnt), 0);
1116	asd_ddbsite_write_word(asd_ha, 0,
1117		 offsetof(struct asd_ddb_seq_shared, q_used_ddb_head), 0xFFFF);
1118	asd_ddbsite_write_word(asd_ha, 0,
1119		 offsetof(struct asd_ddb_seq_shared, q_used_ddb_tail), 0xFFFF);
1120	asd_ddbsite_write_word(asd_ha, 0,
1121		 offsetof(struct asd_ddb_seq_shared, shared_mem_lock), 0);
1122	asd_ddbsite_write_word(asd_ha, 0,
1123		 offsetof(struct asd_ddb_seq_shared, smp_conn_tag), 0);
1124	asd_ddbsite_write_word(asd_ha, 0,
1125		 offsetof(struct asd_ddb_seq_shared, est_nexus_buf_cnt), 0);
1126	asd_ddbsite_write_word(asd_ha, 0,
1127		 offsetof(struct asd_ddb_seq_shared, est_nexus_buf_thresh),
1128			       asd_ha->hw_prof.num_phys * 2);
1129	asd_ddbsite_write_byte(asd_ha, 0,
1130		 offsetof(struct asd_ddb_seq_shared, settable_max_contexts),0);
1131	asd_ddbsite_write_byte(asd_ha, 0,
1132	       offsetof(struct asd_ddb_seq_shared, conn_not_active), 0xFF);
1133	asd_ddbsite_write_byte(asd_ha, 0,
1134	       offsetof(struct asd_ddb_seq_shared, phy_is_up), 0x00);
1135	/* DDB 0 is reserved */
1136	set_bit(0, asd_ha->hw_prof.ddb_bitmap);
1137}
1138
1139static void asd_seq_init_ddb_sites(struct asd_ha_struct *asd_ha)
1140{
1141	unsigned int i;
1142	unsigned int ddb_site;
1143
1144	for (ddb_site = 0 ; ddb_site < ASD_MAX_DDBS; ddb_site++)
1145		for (i = 0; i < sizeof(struct asd_ddb_ssp_smp_target_port); i+= 4)
1146			asd_ddbsite_write_dword(asd_ha, ddb_site, i, 0);
1147}
1148
1149/**
1150 * asd_seq_setup_seqs -- setup and initialize central and link sequencers
1151 * @asd_ha: pointer to host adapter structure
1152 */
1153static void asd_seq_setup_seqs(struct asd_ha_struct *asd_ha)
1154{
1155	int 		lseq;
1156	u8		lseq_mask;
1157
1158	/* Initialize DDB sites */
1159	asd_seq_init_ddb_sites(asd_ha);
1160
1161	/* Initialize SCB sites. Done first to compute some values which
1162	 * the rest of the init code depends on. */
1163	asd_init_scb_sites(asd_ha);
1164
1165	/* Initialize CSEQ Scratch RAM registers. */
1166	asd_init_cseq_scratch(asd_ha);
1167
1168	/* Initialize LmSEQ Scratch RAM registers. */
1169	asd_init_lseq_scratch(asd_ha);
1170
1171	/* Initialize CSEQ CIO registers. */
1172	asd_init_cseq_cio(asd_ha);
1173
1174	asd_init_ddb_0(asd_ha);
1175
1176	/* Initialize LmSEQ CIO registers. */
1177	lseq_mask = asd_ha->hw_prof.enabled_phys;
1178	for_each_sequencer(lseq_mask, lseq_mask, lseq)
1179		asd_init_lseq_cio(asd_ha, lseq);
1180	asd_post_init_cseq(asd_ha);
1181}
1182
1183
1184/**
1185 * asd_seq_start_cseq -- start the central sequencer, CSEQ
1186 * @asd_ha: pointer to host adapter structure
1187 */
1188static int asd_seq_start_cseq(struct asd_ha_struct *asd_ha)
1189{
1190	/* Reset the ARP2 instruction to location zero. */
1191	asd_write_reg_word(asd_ha, CPRGMCNT, cseq_idle_loop);
1192
1193	/* Unpause the CSEQ  */
1194	return asd_unpause_cseq(asd_ha);
1195}
1196
1197/**
1198 * asd_seq_start_lseq -- start a link sequencer
1199 * @asd_ha: pointer to host adapter structure
1200 * @lseq: the link sequencer of interest
1201 */
1202static int asd_seq_start_lseq(struct asd_ha_struct *asd_ha, int lseq)
1203{
1204	/* Reset the ARP2 instruction to location zero. */
1205	asd_write_reg_word(asd_ha, LmPRGMCNT(lseq), lseq_idle_loop);
1206
1207	/* Unpause the LmSEQ  */
1208	return asd_seq_unpause_lseq(asd_ha, lseq);
1209}
1210
1211int asd_release_firmware(void)
1212{
1213	release_firmware(sequencer_fw);
1214	return 0;
1215}
1216
1217static int asd_request_firmware(struct asd_ha_struct *asd_ha)
1218{
1219	int err, i;
1220	struct sequencer_file_header header;
1221	const struct sequencer_file_header *hdr_ptr;
1222	u32 csum = 0;
1223	u16 *ptr_cseq_vecs, *ptr_lseq_vecs;
1224
1225	if (sequencer_fw)
1226		/* already loaded */
1227		return 0;
1228
1229	err = request_firmware(&sequencer_fw,
1230			       SAS_RAZOR_SEQUENCER_FW_FILE,
1231			       &asd_ha->pcidev->dev);
1232	if (err)
1233		return err;
1234
1235	hdr_ptr = (const struct sequencer_file_header *)sequencer_fw->data;
1236
1237	header.csum = le32_to_cpu(hdr_ptr->csum);
1238	header.major = le32_to_cpu(hdr_ptr->major);
1239	header.minor = le32_to_cpu(hdr_ptr->minor);
1240	header.cseq_table_offset = le32_to_cpu(hdr_ptr->cseq_table_offset);
1241	header.cseq_table_size = le32_to_cpu(hdr_ptr->cseq_table_size);
1242	header.lseq_table_offset = le32_to_cpu(hdr_ptr->lseq_table_offset);
1243	header.lseq_table_size = le32_to_cpu(hdr_ptr->lseq_table_size);
1244	header.cseq_code_offset = le32_to_cpu(hdr_ptr->cseq_code_offset);
1245	header.cseq_code_size = le32_to_cpu(hdr_ptr->cseq_code_size);
1246	header.lseq_code_offset = le32_to_cpu(hdr_ptr->lseq_code_offset);
1247	header.lseq_code_size = le32_to_cpu(hdr_ptr->lseq_code_size);
1248	header.mode2_task = le16_to_cpu(hdr_ptr->mode2_task);
1249	header.cseq_idle_loop = le16_to_cpu(hdr_ptr->cseq_idle_loop);
1250	header.lseq_idle_loop = le16_to_cpu(hdr_ptr->lseq_idle_loop);
1251
1252	for (i = sizeof(header.csum); i < sequencer_fw->size; i++)
1253		csum += sequencer_fw->data[i];
1254
1255	if (csum != header.csum) {
1256		asd_printk("Firmware file checksum mismatch\n");
1257		return -EINVAL;
1258	}
1259
1260	if (header.cseq_table_size != CSEQ_NUM_VECS ||
1261	    header.lseq_table_size != LSEQ_NUM_VECS) {
1262		asd_printk("Firmware file table size mismatch\n");
1263		return -EINVAL;
1264	}
1265
1266	asd_printk("Found sequencer Firmware version %d.%d (%s)\n",
1267		   header.major, header.minor, hdr_ptr->version);
1268
1269	if (header.major != SAS_RAZOR_SEQUENCER_FW_MAJOR) {
1270		asd_printk("Firmware Major Version Mismatch;"
1271			   "driver requires version %d.X",
1272			   SAS_RAZOR_SEQUENCER_FW_MAJOR);
1273		return -EINVAL;
1274	}
1275
1276	ptr_cseq_vecs = (u16 *)&sequencer_fw->data[header.cseq_table_offset];
1277	ptr_lseq_vecs = (u16 *)&sequencer_fw->data[header.lseq_table_offset];
1278	mode2_task = header.mode2_task;
1279	cseq_idle_loop = header.cseq_idle_loop;
1280	lseq_idle_loop = header.lseq_idle_loop;
1281
1282	for (i = 0; i < CSEQ_NUM_VECS; i++)
1283		cseq_vecs[i] = le16_to_cpu(ptr_cseq_vecs[i]);
1284
1285	for (i = 0; i < LSEQ_NUM_VECS; i++)
1286		lseq_vecs[i] = le16_to_cpu(ptr_lseq_vecs[i]);
1287
1288	cseq_code = &sequencer_fw->data[header.cseq_code_offset];
1289	cseq_code_size = header.cseq_code_size;
1290	lseq_code = &sequencer_fw->data[header.lseq_code_offset];
1291	lseq_code_size = header.lseq_code_size;
1292
1293	return 0;
1294}
1295
1296int asd_init_seqs(struct asd_ha_struct *asd_ha)
1297{
1298	int err;
1299
1300	err = asd_request_firmware(asd_ha);
1301
1302	if (err) {
1303		asd_printk("Failed to load sequencer firmware file %s, error %d\n",
1304			   SAS_RAZOR_SEQUENCER_FW_FILE, err);
1305		return err;
1306	}
1307
1308	err = asd_seq_download_seqs(asd_ha);
1309	if (err) {
1310		asd_printk("couldn't download sequencers for %s\n",
1311			   pci_name(asd_ha->pcidev));
1312		return err;
1313	}
1314
1315	asd_seq_setup_seqs(asd_ha);
1316
1317	return 0;
1318}
1319
1320int asd_start_seqs(struct asd_ha_struct *asd_ha)
1321{
1322	int err;
1323	u8  lseq_mask;
1324	int lseq;
1325
1326	err = asd_seq_start_cseq(asd_ha);
1327	if (err) {
1328		asd_printk("couldn't start CSEQ for %s\n",
1329			   pci_name(asd_ha->pcidev));
1330		return err;
1331	}
1332
1333	lseq_mask = asd_ha->hw_prof.enabled_phys;
1334	for_each_sequencer(lseq_mask, lseq_mask, lseq) {
1335		err = asd_seq_start_lseq(asd_ha, lseq);
1336		if (err) {
1337			asd_printk("couldn't start LSEQ %d for %s\n", lseq,
1338				   pci_name(asd_ha->pcidev));
1339			return err;
1340		}
1341	}
1342
1343	return 0;
1344}
1345
1346/**
1347 * asd_update_port_links -- update port_map_by_links and phy_is_up
1348 * @sas_phy: pointer to the phy which has been added to a port
1349 *
1350 * 1) When a link reset has completed and we got BYTES DMAED with a
1351 * valid frame we call this function for that phy, to indicate that
1352 * the phy is up, i.e. we update the phy_is_up in DDB 0.  The
1353 * sequencer checks phy_is_up when pending SCBs are to be sent, and
1354 * when an open address frame has been received.
1355 *
1356 * 2) When we know of ports, we call this function to update the map
1357 * of phys participaing in that port, i.e. we update the
1358 * port_map_by_links in DDB 0.  When a HARD_RESET primitive has been
1359 * received, the sequencer disables all phys in that port.
1360 * port_map_by_links is also used as the conn_mask byte in the
1361 * initiator/target port DDB.
1362 */
1363void asd_update_port_links(struct asd_ha_struct *asd_ha, struct asd_phy *phy)
1364{
1365	const u8 phy_mask = (u8) phy->asd_port->phy_mask;
1366	u8  phy_is_up;
1367	u8  mask;
1368	int i, err;
1369	unsigned long flags;
1370
1371	spin_lock_irqsave(&asd_ha->hw_prof.ddb_lock, flags);
1372	for_each_phy(phy_mask, mask, i)
1373		asd_ddbsite_write_byte(asd_ha, 0,
1374				       offsetof(struct asd_ddb_seq_shared,
1375						port_map_by_links)+i,phy_mask);
1376
1377	for (i = 0; i < 12; i++) {
1378		phy_is_up = asd_ddbsite_read_byte(asd_ha, 0,
1379			  offsetof(struct asd_ddb_seq_shared, phy_is_up));
1380		err = asd_ddbsite_update_byte(asd_ha, 0,
1381				offsetof(struct asd_ddb_seq_shared, phy_is_up),
1382				phy_is_up,
1383				phy_is_up | phy_mask);
1384		if (!err)
1385			break;
1386		else if (err == -EFAULT) {
1387			asd_printk("phy_is_up: parity error in DDB 0\n");
1388			break;
1389		}
1390	}
1391	spin_unlock_irqrestore(&asd_ha->hw_prof.ddb_lock, flags);
1392
1393	if (err)
1394		asd_printk("couldn't update DDB 0:error:%d\n", err);
1395}
1396
1397MODULE_FIRMWARE(SAS_RAZOR_SEQUENCER_FW_FILE);