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/drivers/scsi/arcmsr/arcmsr.h

http://github.com/mirrors/linux
C Header | 949 lines | 683 code | 19 blank | 247 comment | 2 complexity | 473b3ddcf6aa61a29cf96efbd14cfba4 MD5 | raw file
  1/*
  2*******************************************************************************
  3**        O.S   : Linux
  4**   FILE NAME  : arcmsr.h
  5**        BY    : Nick Cheng
  6**   Description: SCSI RAID Device Driver for
  7**                ARECA RAID Host adapter
  8*******************************************************************************
  9** Copyright (C) 2002 - 2005, Areca Technology Corporation All rights reserved.
 10**
 11**     Web site: www.areca.com.tw
 12**       E-mail: support@areca.com.tw
 13**
 14** This program is free software; you can redistribute it and/or modify
 15** it under the terms of the GNU General Public License version 2 as
 16** published by the Free Software Foundation.
 17** This program is distributed in the hope that it will be useful,
 18** but WITHOUT ANY WARRANTY; without even the implied warranty of
 19** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 20** GNU General Public License for more details.
 21*******************************************************************************
 22** Redistribution and use in source and binary forms, with or without
 23** modification, are permitted provided that the following conditions
 24** are met:
 25** 1. Redistributions of source code must retain the above copyright
 26**    notice, this list of conditions and the following disclaimer.
 27** 2. Redistributions in binary form must reproduce the above copyright
 28**    notice, this list of conditions and the following disclaimer in the
 29**    documentation and/or other materials provided with the distribution.
 30** 3. The name of the author may not be used to endorse or promote products
 31**    derived from this software without specific prior written permission.
 32**
 33** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 34** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 35** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 36** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 37** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT
 38** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 39** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY
 40** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 41**(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF
 42** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 43*******************************************************************************
 44*/
 45#include <linux/interrupt.h>
 46struct device_attribute;
 47/*The limit of outstanding scsi command that firmware can handle*/
 48#define ARCMSR_MAX_FREECCB_NUM		1024
 49#define ARCMSR_MAX_OUTSTANDING_CMD	1024
 50#define ARCMSR_DEFAULT_OUTSTANDING_CMD	128
 51#define ARCMSR_MIN_OUTSTANDING_CMD	32
 52#define ARCMSR_DRIVER_VERSION		"v1.40.00.10-20190116"
 53#define ARCMSR_SCSI_INITIATOR_ID	255
 54#define ARCMSR_MAX_XFER_SECTORS		512
 55#define ARCMSR_MAX_XFER_SECTORS_B	4096
 56#define ARCMSR_MAX_XFER_SECTORS_C	304
 57#define ARCMSR_MAX_TARGETID		17
 58#define ARCMSR_MAX_TARGETLUN		8
 59#define ARCMSR_MAX_CMD_PERLUN		128
 60#define ARCMSR_DEFAULT_CMD_PERLUN	32
 61#define ARCMSR_MIN_CMD_PERLUN		1
 62#define ARCMSR_MAX_QBUFFER		4096
 63#define ARCMSR_DEFAULT_SG_ENTRIES	38
 64#define ARCMSR_MAX_HBB_POSTQUEUE	264
 65#define ARCMSR_MAX_ARC1214_POSTQUEUE	256
 66#define ARCMSR_MAX_ARC1214_DONEQUEUE	257
 67#define ARCMSR_MAX_HBE_DONEQUEUE	512
 68#define ARCMSR_MAX_XFER_LEN		0x26000 /* 152K */
 69#define ARCMSR_CDB_SG_PAGE_LENGTH	256
 70#define ARCMST_NUM_MSIX_VECTORS		4
 71#ifndef PCI_DEVICE_ID_ARECA_1880
 72#define PCI_DEVICE_ID_ARECA_1880	0x1880
 73#endif
 74#ifndef PCI_DEVICE_ID_ARECA_1214
 75#define PCI_DEVICE_ID_ARECA_1214	0x1214
 76#endif
 77#ifndef PCI_DEVICE_ID_ARECA_1203
 78#define PCI_DEVICE_ID_ARECA_1203	0x1203
 79#endif
 80#ifndef PCI_DEVICE_ID_ARECA_1884
 81#define PCI_DEVICE_ID_ARECA_1884	0x1884
 82#endif
 83#define	ARCMSR_HOURS			(1000 * 60 * 60 * 4)
 84#define	ARCMSR_MINUTES			(1000 * 60 * 60)
 85/*
 86**********************************************************************************
 87**
 88**********************************************************************************
 89*/
 90#define ARC_SUCCESS	0
 91#define ARC_FAILURE	1
 92/*
 93*******************************************************************************
 94**        split 64bits dma addressing
 95*******************************************************************************
 96*/
 97#define dma_addr_hi32(addr)	(uint32_t) ((addr>>16)>>16)
 98#define dma_addr_lo32(addr)	(uint32_t) (addr & 0xffffffff)
 99/*
100*******************************************************************************
101**        MESSAGE CONTROL CODE
102*******************************************************************************
103*/
104struct CMD_MESSAGE
105{
106      uint32_t HeaderLength;
107      uint8_t  Signature[8];
108      uint32_t Timeout;
109      uint32_t ControlCode;
110      uint32_t ReturnCode;
111      uint32_t Length;
112};
113/*
114*******************************************************************************
115**        IOP Message Transfer Data for user space
116*******************************************************************************
117*/
118#define	ARCMSR_API_DATA_BUFLEN	1032
119struct CMD_MESSAGE_FIELD
120{
121    struct CMD_MESSAGE			cmdmessage;
122    uint8_t				messagedatabuffer[ARCMSR_API_DATA_BUFLEN];
123};
124/* IOP message transfer */
125#define ARCMSR_MESSAGE_FAIL			0x0001
126/* DeviceType */
127#define ARECA_SATA_RAID				0x90000000
128/* FunctionCode */
129#define FUNCTION_READ_RQBUFFER			0x0801
130#define FUNCTION_WRITE_WQBUFFER			0x0802
131#define FUNCTION_CLEAR_RQBUFFER			0x0803
132#define FUNCTION_CLEAR_WQBUFFER			0x0804
133#define FUNCTION_CLEAR_ALLQBUFFER		0x0805
134#define FUNCTION_RETURN_CODE_3F			0x0806
135#define FUNCTION_SAY_HELLO			0x0807
136#define FUNCTION_SAY_GOODBYE			0x0808
137#define FUNCTION_FLUSH_ADAPTER_CACHE		0x0809
138#define FUNCTION_GET_FIRMWARE_STATUS		0x080A
139#define FUNCTION_HARDWARE_RESET			0x080B
140/* ARECA IO CONTROL CODE*/
141#define ARCMSR_MESSAGE_READ_RQBUFFER       \
142	ARECA_SATA_RAID | FUNCTION_READ_RQBUFFER
143#define ARCMSR_MESSAGE_WRITE_WQBUFFER      \
144	ARECA_SATA_RAID | FUNCTION_WRITE_WQBUFFER
145#define ARCMSR_MESSAGE_CLEAR_RQBUFFER      \
146	ARECA_SATA_RAID | FUNCTION_CLEAR_RQBUFFER
147#define ARCMSR_MESSAGE_CLEAR_WQBUFFER      \
148	ARECA_SATA_RAID | FUNCTION_CLEAR_WQBUFFER
149#define ARCMSR_MESSAGE_CLEAR_ALLQBUFFER    \
150	ARECA_SATA_RAID | FUNCTION_CLEAR_ALLQBUFFER
151#define ARCMSR_MESSAGE_RETURN_CODE_3F      \
152	ARECA_SATA_RAID | FUNCTION_RETURN_CODE_3F
153#define ARCMSR_MESSAGE_SAY_HELLO           \
154	ARECA_SATA_RAID | FUNCTION_SAY_HELLO
155#define ARCMSR_MESSAGE_SAY_GOODBYE         \
156	ARECA_SATA_RAID | FUNCTION_SAY_GOODBYE
157#define ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE \
158	ARECA_SATA_RAID | FUNCTION_FLUSH_ADAPTER_CACHE
159/* ARECA IOCTL ReturnCode */
160#define ARCMSR_MESSAGE_RETURNCODE_OK		0x00000001
161#define ARCMSR_MESSAGE_RETURNCODE_ERROR		0x00000006
162#define ARCMSR_MESSAGE_RETURNCODE_3F		0x0000003F
163#define ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON	0x00000088
164/*
165*************************************************************
166**   structure for holding DMA address data
167*************************************************************
168*/
169#define IS_DMA64	(sizeof(dma_addr_t) == 8)
170#define IS_SG64_ADDR	0x01000000 /* bit24 */
171struct  SG32ENTRY
172{
173	__le32		length;
174	__le32		address;
175}__attribute__ ((packed));
176struct  SG64ENTRY
177{
178	__le32		length;
179	__le32		address;
180	__le32		addresshigh;
181}__attribute__ ((packed));
182/*
183********************************************************************
184**      Q Buffer of IOP Message Transfer
185********************************************************************
186*/
187struct QBUFFER
188{
189	uint32_t      data_len;
190	uint8_t       data[124];
191};
192/*
193*******************************************************************************
194**      FIRMWARE INFO for Intel IOP R 80331 processor (Type A)
195*******************************************************************************
196*/
197struct FIRMWARE_INFO
198{
199	uint32_t	signature;		/*0, 00-03*/
200	uint32_t	request_len;		/*1, 04-07*/
201	uint32_t	numbers_queue;		/*2, 08-11*/
202	uint32_t	sdram_size;		/*3, 12-15*/
203	uint32_t	ide_channels;		/*4, 16-19*/
204	char		vendor[40];		/*5, 20-59*/
205	char		model[8];		/*15, 60-67*/
206	char		firmware_ver[16];     	/*17, 68-83*/
207	char		device_map[16];		/*21, 84-99*/
208	uint32_t	cfgVersion;		/*25,100-103 Added for checking of new firmware capability*/
209	uint8_t		cfgSerial[16];		/*26,104-119*/
210	uint32_t	cfgPicStatus;		/*30,120-123*/
211};
212/* signature of set and get firmware config */
213#define ARCMSR_SIGNATURE_GET_CONFIG		0x87974060
214#define ARCMSR_SIGNATURE_SET_CONFIG		0x87974063
215/* message code of inbound message register */
216#define ARCMSR_INBOUND_MESG0_NOP		0x00000000
217#define ARCMSR_INBOUND_MESG0_GET_CONFIG		0x00000001
218#define ARCMSR_INBOUND_MESG0_SET_CONFIG		0x00000002
219#define ARCMSR_INBOUND_MESG0_ABORT_CMD		0x00000003
220#define ARCMSR_INBOUND_MESG0_STOP_BGRB		0x00000004
221#define ARCMSR_INBOUND_MESG0_FLUSH_CACHE	0x00000005
222#define ARCMSR_INBOUND_MESG0_START_BGRB		0x00000006
223#define ARCMSR_INBOUND_MESG0_CHK331PENDING	0x00000007
224#define ARCMSR_INBOUND_MESG0_SYNC_TIMER		0x00000008
225/* doorbell interrupt generator */
226#define ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK	0x00000001
227#define ARCMSR_INBOUND_DRIVER_DATA_READ_OK	0x00000002
228#define ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK	0x00000001
229#define ARCMSR_OUTBOUND_IOP331_DATA_READ_OK	0x00000002
230/* ccb areca cdb flag */
231#define ARCMSR_CCBPOST_FLAG_SGL_BSIZE		0x80000000
232#define ARCMSR_CCBPOST_FLAG_IAM_BIOS		0x40000000
233#define ARCMSR_CCBREPLY_FLAG_IAM_BIOS		0x40000000
234#define ARCMSR_CCBREPLY_FLAG_ERROR_MODE0	0x10000000
235#define ARCMSR_CCBREPLY_FLAG_ERROR_MODE1	0x00000001
236/* outbound firmware ok */
237#define ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK	0x80000000
238/* ARC-1680 Bus Reset*/
239#define ARCMSR_ARC1680_BUS_RESET		0x00000003
240/* ARC-1880 Bus Reset*/
241#define ARCMSR_ARC1880_RESET_ADAPTER		0x00000024
242#define ARCMSR_ARC1880_DiagWrite_ENABLE		0x00000080
243
244/*
245************************************************************************
246**                SPEC. for Areca Type B adapter
247************************************************************************
248*/
249/* ARECA HBB COMMAND for its FIRMWARE */
250/* window of "instruction flags" from driver to iop */
251#define ARCMSR_DRV2IOP_DOORBELL                       0x00020400
252#define ARCMSR_DRV2IOP_DOORBELL_MASK                  0x00020404
253/* window of "instruction flags" from iop to driver */
254#define ARCMSR_IOP2DRV_DOORBELL                       0x00020408
255#define ARCMSR_IOP2DRV_DOORBELL_MASK                  0x0002040C
256/* window of "instruction flags" from iop to driver */
257#define ARCMSR_IOP2DRV_DOORBELL_1203                  0x00021870
258#define ARCMSR_IOP2DRV_DOORBELL_MASK_1203             0x00021874
259/* window of "instruction flags" from driver to iop */
260#define ARCMSR_DRV2IOP_DOORBELL_1203                  0x00021878
261#define ARCMSR_DRV2IOP_DOORBELL_MASK_1203             0x0002187C
262/* ARECA FLAG LANGUAGE */
263/* ioctl transfer */
264#define ARCMSR_IOP2DRV_DATA_WRITE_OK                  0x00000001
265/* ioctl transfer */
266#define ARCMSR_IOP2DRV_DATA_READ_OK                   0x00000002
267#define ARCMSR_IOP2DRV_CDB_DONE                       0x00000004
268#define ARCMSR_IOP2DRV_MESSAGE_CMD_DONE               0x00000008
269
270#define ARCMSR_DOORBELL_HANDLE_INT		      0x0000000F
271#define ARCMSR_DOORBELL_INT_CLEAR_PATTERN   	      0xFF00FFF0
272#define ARCMSR_MESSAGE_INT_CLEAR_PATTERN	      0xFF00FFF7
273/* (ARCMSR_INBOUND_MESG0_GET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
274#define ARCMSR_MESSAGE_GET_CONFIG		      0x00010008
275/* (ARCMSR_INBOUND_MESG0_SET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
276#define ARCMSR_MESSAGE_SET_CONFIG		      0x00020008
277/* (ARCMSR_INBOUND_MESG0_ABORT_CMD<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
278#define ARCMSR_MESSAGE_ABORT_CMD		      0x00030008
279/* (ARCMSR_INBOUND_MESG0_STOP_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
280#define ARCMSR_MESSAGE_STOP_BGRB		      0x00040008
281/* (ARCMSR_INBOUND_MESG0_FLUSH_CACHE<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
282#define ARCMSR_MESSAGE_FLUSH_CACHE                    0x00050008
283/* (ARCMSR_INBOUND_MESG0_START_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
284#define ARCMSR_MESSAGE_START_BGRB		      0x00060008
285#define ARCMSR_MESSAGE_SYNC_TIMER		      0x00080008
286#define ARCMSR_MESSAGE_START_DRIVER_MODE	      0x000E0008
287#define ARCMSR_MESSAGE_SET_POST_WINDOW		      0x000F0008
288#define ARCMSR_MESSAGE_ACTIVE_EOI_MODE		      0x00100008
289/* ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK */
290#define ARCMSR_MESSAGE_FIRMWARE_OK		      0x80000000
291/* ioctl transfer */
292#define ARCMSR_DRV2IOP_DATA_WRITE_OK                  0x00000001
293/* ioctl transfer */
294#define ARCMSR_DRV2IOP_DATA_READ_OK                   0x00000002
295#define ARCMSR_DRV2IOP_CDB_POSTED                     0x00000004
296#define ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED             0x00000008
297#define ARCMSR_DRV2IOP_END_OF_INTERRUPT	              0x00000010
298
299/* data tunnel buffer between user space program and its firmware */
300/* user space data to iop 128bytes */
301#define ARCMSR_MESSAGE_WBUFFER			      0x0000fe00
302/* iop data to user space 128bytes */
303#define ARCMSR_MESSAGE_RBUFFER			      0x0000ff00
304/* iop message_rwbuffer for message command */
305#define ARCMSR_MESSAGE_RWBUFFER			      0x0000fa00
306
307#define MEM_BASE0(x)	(u32 __iomem *)((unsigned long)acb->mem_base0 + x)
308#define MEM_BASE1(x)	(u32 __iomem *)((unsigned long)acb->mem_base1 + x)
309/* 
310************************************************************************
311**                SPEC. for Areca HBC adapter
312************************************************************************
313*/
314#define ARCMSR_HBC_ISR_THROTTLING_LEVEL		12
315#define ARCMSR_HBC_ISR_MAX_DONE_QUEUE		20
316/* Host Interrupt Mask */
317#define ARCMSR_HBCMU_UTILITY_A_ISR_MASK		0x00000001 /* When clear, the Utility_A interrupt routes to the host.*/
318#define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK	0x00000004 /* When clear, the General Outbound Doorbell interrupt routes to the host.*/
319#define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK	0x00000008 /* When clear, the Outbound Post List FIFO Not Empty interrupt routes to the host.*/
320#define ARCMSR_HBCMU_ALL_INTMASKENABLE		0x0000000D /* disable all ISR */
321/* Host Interrupt Status */
322#define ARCMSR_HBCMU_UTILITY_A_ISR		0x00000001
323	/*
324	** Set when the Utility_A Interrupt bit is set in the Outbound Doorbell Register.
325	** It clears by writing a 1 to the Utility_A bit in the Outbound Doorbell Clear Register or through automatic clearing (if enabled).
326	*/
327#define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR	0x00000004
328	/*
329	** Set if Outbound Doorbell register bits 30:1 have a non-zero
330	** value. This bit clears only when Outbound Doorbell bits
331	** 30:1 are ALL clear. Only a write to the Outbound Doorbell
332	** Clear register clears bits in the Outbound Doorbell register.
333	*/
334#define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR	0x00000008
335	/*
336	** Set whenever the Outbound Post List Producer/Consumer
337	** Register (FIFO) is not empty. It clears when the Outbound
338	** Post List FIFO is empty.
339	*/
340#define ARCMSR_HBCMU_SAS_ALL_INT		0x00000010
341	/*
342	** This bit indicates a SAS interrupt from a source external to
343	** the PCIe core. This bit is not maskable.
344	*/
345	/* DoorBell*/
346#define ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK			0x00000002
347#define ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK			0x00000004
348	/*inbound message 0 ready*/
349#define ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE			0x00000008
350	/*more than 12 request completed in a time*/
351#define ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING		0x00000010
352#define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK			0x00000002
353	/*outbound DATA WRITE isr door bell clear*/
354#define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_DOORBELL_CLEAR		0x00000002
355#define ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK			0x00000004
356	/*outbound DATA READ isr door bell clear*/
357#define ARCMSR_HBCMU_IOP2DRV_DATA_READ_DOORBELL_CLEAR		0x00000004
358	/*outbound message 0 ready*/
359#define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE			0x00000008
360	/*outbound message cmd isr door bell clear*/
361#define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR	0x00000008
362	/*ARCMSR_HBAMU_MESSAGE_FIRMWARE_OK*/
363#define ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK			0x80000000
364/*
365*******************************************************************************
366**                SPEC. for Areca Type D adapter
367*******************************************************************************
368*/
369#define ARCMSR_ARC1214_CHIP_ID				0x00004
370#define ARCMSR_ARC1214_CPU_MEMORY_CONFIGURATION		0x00008
371#define ARCMSR_ARC1214_I2_HOST_INTERRUPT_MASK		0x00034
372#define ARCMSR_ARC1214_SAMPLE_RESET			0x00100
373#define ARCMSR_ARC1214_RESET_REQUEST			0x00108
374#define ARCMSR_ARC1214_MAIN_INTERRUPT_STATUS		0x00200
375#define ARCMSR_ARC1214_PCIE_F0_INTERRUPT_ENABLE		0x0020C
376#define ARCMSR_ARC1214_INBOUND_MESSAGE0			0x00400
377#define ARCMSR_ARC1214_INBOUND_MESSAGE1			0x00404
378#define ARCMSR_ARC1214_OUTBOUND_MESSAGE0		0x00420
379#define ARCMSR_ARC1214_OUTBOUND_MESSAGE1		0x00424
380#define ARCMSR_ARC1214_INBOUND_DOORBELL			0x00460
381#define ARCMSR_ARC1214_OUTBOUND_DOORBELL		0x00480
382#define ARCMSR_ARC1214_OUTBOUND_DOORBELL_ENABLE		0x00484
383#define ARCMSR_ARC1214_INBOUND_LIST_BASE_LOW		0x01000
384#define ARCMSR_ARC1214_INBOUND_LIST_BASE_HIGH		0x01004
385#define ARCMSR_ARC1214_INBOUND_LIST_WRITE_POINTER	0x01018
386#define ARCMSR_ARC1214_OUTBOUND_LIST_BASE_LOW		0x01060
387#define ARCMSR_ARC1214_OUTBOUND_LIST_BASE_HIGH		0x01064
388#define ARCMSR_ARC1214_OUTBOUND_LIST_COPY_POINTER	0x0106C
389#define ARCMSR_ARC1214_OUTBOUND_LIST_READ_POINTER	0x01070
390#define ARCMSR_ARC1214_OUTBOUND_INTERRUPT_CAUSE		0x01088
391#define ARCMSR_ARC1214_OUTBOUND_INTERRUPT_ENABLE	0x0108C
392#define ARCMSR_ARC1214_MESSAGE_WBUFFER			0x02000
393#define ARCMSR_ARC1214_MESSAGE_RBUFFER			0x02100
394#define ARCMSR_ARC1214_MESSAGE_RWBUFFER			0x02200
395/* Host Interrupt Mask */
396#define ARCMSR_ARC1214_ALL_INT_ENABLE			0x00001010
397#define ARCMSR_ARC1214_ALL_INT_DISABLE			0x00000000
398/* Host Interrupt Status */
399#define ARCMSR_ARC1214_OUTBOUND_DOORBELL_ISR		0x00001000
400#define ARCMSR_ARC1214_OUTBOUND_POSTQUEUE_ISR		0x00000010
401/* DoorBell*/
402#define ARCMSR_ARC1214_DRV2IOP_DATA_IN_READY		0x00000001
403#define ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ		0x00000002
404/*inbound message 0 ready*/
405#define ARCMSR_ARC1214_IOP2DRV_DATA_WRITE_OK		0x00000001
406/*outbound DATA WRITE isr door bell clear*/
407#define ARCMSR_ARC1214_IOP2DRV_DATA_READ_OK		0x00000002
408/*outbound message 0 ready*/
409#define ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE		0x02000000
410/*outbound message cmd isr door bell clear*/
411/*ARCMSR_HBAMU_MESSAGE_FIRMWARE_OK*/
412#define ARCMSR_ARC1214_MESSAGE_FIRMWARE_OK		0x80000000
413#define ARCMSR_ARC1214_OUTBOUND_LIST_INTERRUPT_CLEAR	0x00000001
414/*
415*******************************************************************************
416**                SPEC. for Areca Type E adapter
417*******************************************************************************
418*/
419#define ARCMSR_SIGNATURE_1884			0x188417D3
420
421#define ARCMSR_HBEMU_DRV2IOP_DATA_WRITE_OK	0x00000002
422#define ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK	0x00000004
423#define ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE	0x00000008
424
425#define ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK	0x00000002
426#define ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK	0x00000004
427#define ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE	0x00000008
428
429#define ARCMSR_HBEMU_MESSAGE_FIRMWARE_OK	0x80000000
430
431#define ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR	0x00000001
432#define ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR	0x00000008
433#define ARCMSR_HBEMU_ALL_INTMASKENABLE		0x00000009
434
435/* ARC-1884 doorbell sync */
436#define ARCMSR_HBEMU_DOORBELL_SYNC		0x100
437#define ARCMSR_ARC188X_RESET_ADAPTER		0x00000004
438#define ARCMSR_ARC1884_DiagWrite_ENABLE		0x00000080
439/*
440*******************************************************************************
441**    ARECA SCSI COMMAND DESCRIPTOR BLOCK size 0x1F8 (504)
442*******************************************************************************
443*/
444struct ARCMSR_CDB
445{
446	uint8_t		Bus;
447	uint8_t		TargetID;
448	uint8_t		LUN;
449	uint8_t		Function;
450	uint8_t		CdbLength;
451	uint8_t		sgcount;
452	uint8_t		Flags;
453#define ARCMSR_CDB_FLAG_SGL_BSIZE          0x01
454#define ARCMSR_CDB_FLAG_BIOS               0x02
455#define ARCMSR_CDB_FLAG_WRITE              0x04
456#define ARCMSR_CDB_FLAG_SIMPLEQ            0x00
457#define ARCMSR_CDB_FLAG_HEADQ              0x08
458#define ARCMSR_CDB_FLAG_ORDEREDQ           0x10
459
460	uint8_t		msgPages;
461	uint32_t	msgContext;
462	uint32_t	DataLength;
463	uint8_t		Cdb[16];
464	uint8_t		DeviceStatus;
465#define ARCMSR_DEV_CHECK_CONDITION	    0x02
466#define ARCMSR_DEV_SELECT_TIMEOUT	    0xF0
467#define ARCMSR_DEV_ABORTED		    0xF1
468#define ARCMSR_DEV_INIT_FAIL		    0xF2
469
470	uint8_t		SenseData[15];
471	union
472	{
473		struct SG32ENTRY	sg32entry[1];
474		struct SG64ENTRY	sg64entry[1];
475	} u;
476};
477/*
478*******************************************************************************
479**     Messaging Unit (MU) of the Intel R 80331 I/O processor(Type A) and Type B processor
480*******************************************************************************
481*/
482struct MessageUnit_A
483{
484	uint32_t	resrved0[4];			/*0000 000F*/
485	uint32_t	inbound_msgaddr0;		/*0010 0013*/
486	uint32_t	inbound_msgaddr1;		/*0014 0017*/
487	uint32_t	outbound_msgaddr0;		/*0018 001B*/
488	uint32_t	outbound_msgaddr1;		/*001C 001F*/
489	uint32_t	inbound_doorbell;		/*0020 0023*/
490	uint32_t	inbound_intstatus;		/*0024 0027*/
491	uint32_t	inbound_intmask;		/*0028 002B*/
492	uint32_t	outbound_doorbell;		/*002C 002F*/
493	uint32_t	outbound_intstatus;		/*0030 0033*/
494	uint32_t	outbound_intmask;		/*0034 0037*/
495	uint32_t	reserved1[2];			/*0038 003F*/
496	uint32_t	inbound_queueport;		/*0040 0043*/
497	uint32_t	outbound_queueport;     	/*0044 0047*/
498	uint32_t	reserved2[2];			/*0048 004F*/
499	uint32_t	reserved3[492];			/*0050 07FF 492*/
500	uint32_t	reserved4[128];			/*0800 09FF 128*/
501	uint32_t	message_rwbuffer[256];		/*0a00 0DFF 256*/
502	uint32_t	message_wbuffer[32];		/*0E00 0E7F  32*/
503	uint32_t	reserved5[32];			/*0E80 0EFF  32*/
504	uint32_t	message_rbuffer[32];		/*0F00 0F7F  32*/
505	uint32_t	reserved6[32];			/*0F80 0FFF  32*/
506};
507
508struct MessageUnit_B
509{
510	uint32_t	post_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE];
511	uint32_t	done_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE];
512	uint32_t	postq_index;
513	uint32_t	doneq_index;
514	uint32_t	__iomem *drv2iop_doorbell;
515	uint32_t	__iomem *drv2iop_doorbell_mask;
516	uint32_t	__iomem *iop2drv_doorbell;
517	uint32_t	__iomem *iop2drv_doorbell_mask;
518	uint32_t	__iomem *message_rwbuffer;
519	uint32_t	__iomem *message_wbuffer;
520	uint32_t	__iomem *message_rbuffer;
521};
522/*
523*********************************************************************
524** LSI
525*********************************************************************
526*/
527struct MessageUnit_C{
528	uint32_t	message_unit_status;			/*0000 0003*/
529	uint32_t	slave_error_attribute;			/*0004 0007*/
530	uint32_t	slave_error_address;			/*0008 000B*/
531	uint32_t	posted_outbound_doorbell;		/*000C 000F*/
532	uint32_t	master_error_attribute;			/*0010 0013*/
533	uint32_t	master_error_address_low;		/*0014 0017*/
534	uint32_t	master_error_address_high;		/*0018 001B*/
535	uint32_t	hcb_size;				/*001C 001F*/
536	uint32_t	inbound_doorbell;			/*0020 0023*/
537	uint32_t	diagnostic_rw_data;			/*0024 0027*/
538	uint32_t	diagnostic_rw_address_low;		/*0028 002B*/
539	uint32_t	diagnostic_rw_address_high;		/*002C 002F*/
540	uint32_t	host_int_status;			/*0030 0033*/
541	uint32_t	host_int_mask;				/*0034 0037*/
542	uint32_t	dcr_data;				/*0038 003B*/
543	uint32_t	dcr_address;				/*003C 003F*/
544	uint32_t	inbound_queueport;			/*0040 0043*/
545	uint32_t	outbound_queueport;			/*0044 0047*/
546	uint32_t	hcb_pci_address_low;			/*0048 004B*/
547	uint32_t	hcb_pci_address_high;			/*004C 004F*/
548	uint32_t	iop_int_status;				/*0050 0053*/
549	uint32_t	iop_int_mask;				/*0054 0057*/
550	uint32_t	iop_inbound_queue_port;			/*0058 005B*/
551	uint32_t	iop_outbound_queue_port;		/*005C 005F*/
552	uint32_t	inbound_free_list_index;		/*0060 0063*/
553	uint32_t	inbound_post_list_index;		/*0064 0067*/
554	uint32_t	outbound_free_list_index;		/*0068 006B*/
555	uint32_t	outbound_post_list_index;		/*006C 006F*/
556	uint32_t	inbound_doorbell_clear;			/*0070 0073*/
557	uint32_t	i2o_message_unit_control;		/*0074 0077*/
558	uint32_t	last_used_message_source_address_low;	/*0078 007B*/
559	uint32_t	last_used_message_source_address_high;	/*007C 007F*/
560	uint32_t	pull_mode_data_byte_count[4];		/*0080 008F*/
561	uint32_t	message_dest_address_index;		/*0090 0093*/
562	uint32_t	done_queue_not_empty_int_counter_timer;	/*0094 0097*/
563	uint32_t	utility_A_int_counter_timer;		/*0098 009B*/
564	uint32_t	outbound_doorbell;			/*009C 009F*/
565	uint32_t	outbound_doorbell_clear;		/*00A0 00A3*/
566	uint32_t	message_source_address_index;		/*00A4 00A7*/
567	uint32_t	message_done_queue_index;		/*00A8 00AB*/
568	uint32_t	reserved0;				/*00AC 00AF*/
569	uint32_t	inbound_msgaddr0;			/*00B0 00B3*/
570	uint32_t	inbound_msgaddr1;			/*00B4 00B7*/
571	uint32_t	outbound_msgaddr0;			/*00B8 00BB*/
572	uint32_t	outbound_msgaddr1;			/*00BC 00BF*/
573	uint32_t	inbound_queueport_low;			/*00C0 00C3*/
574	uint32_t	inbound_queueport_high;			/*00C4 00C7*/
575	uint32_t	outbound_queueport_low;			/*00C8 00CB*/
576	uint32_t	outbound_queueport_high;		/*00CC 00CF*/
577	uint32_t	iop_inbound_queue_port_low;		/*00D0 00D3*/
578	uint32_t	iop_inbound_queue_port_high;		/*00D4 00D7*/
579	uint32_t	iop_outbound_queue_port_low;		/*00D8 00DB*/
580	uint32_t	iop_outbound_queue_port_high;		/*00DC 00DF*/
581	uint32_t	message_dest_queue_port_low;		/*00E0 00E3*/
582	uint32_t	message_dest_queue_port_high;		/*00E4 00E7*/
583	uint32_t	last_used_message_dest_address_low;	/*00E8 00EB*/
584	uint32_t	last_used_message_dest_address_high;	/*00EC 00EF*/
585	uint32_t	message_done_queue_base_address_low;	/*00F0 00F3*/
586	uint32_t	message_done_queue_base_address_high;	/*00F4 00F7*/
587	uint32_t	host_diagnostic;			/*00F8 00FB*/
588	uint32_t	write_sequence;				/*00FC 00FF*/
589	uint32_t	reserved1[34];				/*0100 0187*/
590	uint32_t	reserved2[1950];			/*0188 1FFF*/
591	uint32_t	message_wbuffer[32];			/*2000 207F*/
592	uint32_t	reserved3[32];				/*2080 20FF*/
593	uint32_t	message_rbuffer[32];			/*2100 217F*/
594	uint32_t	reserved4[32];				/*2180 21FF*/
595	uint32_t	msgcode_rwbuffer[256];			/*2200 23FF*/
596};
597/*
598*********************************************************************
599**     Messaging Unit (MU) of Type D processor
600*********************************************************************
601*/
602struct InBound_SRB {
603	uint32_t addressLow; /* pointer to SRB block */
604	uint32_t addressHigh;
605	uint32_t length; /* in DWORDs */
606	uint32_t reserved0;
607};
608
609struct OutBound_SRB {
610	uint32_t addressLow; /* pointer to SRB block */
611	uint32_t addressHigh;
612};
613
614struct MessageUnit_D {
615	struct InBound_SRB	post_qbuffer[ARCMSR_MAX_ARC1214_POSTQUEUE];
616	volatile struct OutBound_SRB
617				done_qbuffer[ARCMSR_MAX_ARC1214_DONEQUEUE];
618	u16 postq_index;
619	volatile u16 doneq_index;
620	u32 __iomem *chip_id;			/* 0x00004 */
621	u32 __iomem *cpu_mem_config;		/* 0x00008 */
622	u32 __iomem *i2o_host_interrupt_mask;	/* 0x00034 */
623	u32 __iomem *sample_at_reset;		/* 0x00100 */
624	u32 __iomem *reset_request;		/* 0x00108 */
625	u32 __iomem *host_int_status;		/* 0x00200 */
626	u32 __iomem *pcief0_int_enable;		/* 0x0020C */
627	u32 __iomem *inbound_msgaddr0;		/* 0x00400 */
628	u32 __iomem *inbound_msgaddr1;		/* 0x00404 */
629	u32 __iomem *outbound_msgaddr0;		/* 0x00420 */
630	u32 __iomem *outbound_msgaddr1;		/* 0x00424 */
631	u32 __iomem *inbound_doorbell;		/* 0x00460 */
632	u32 __iomem *outbound_doorbell;		/* 0x00480 */
633	u32 __iomem *outbound_doorbell_enable;	/* 0x00484 */
634	u32 __iomem *inboundlist_base_low;	/* 0x01000 */
635	u32 __iomem *inboundlist_base_high;	/* 0x01004 */
636	u32 __iomem *inboundlist_write_pointer;	/* 0x01018 */
637	u32 __iomem *outboundlist_base_low;	/* 0x01060 */
638	u32 __iomem *outboundlist_base_high;	/* 0x01064 */
639	u32 __iomem *outboundlist_copy_pointer;	/* 0x0106C */
640	u32 __iomem *outboundlist_read_pointer;	/* 0x01070 0x01072 */
641	u32 __iomem *outboundlist_interrupt_cause;	/* 0x1088 */
642	u32 __iomem *outboundlist_interrupt_enable;	/* 0x108C */
643	u32 __iomem *message_wbuffer;		/* 0x2000 */
644	u32 __iomem *message_rbuffer;		/* 0x2100 */
645	u32 __iomem *msgcode_rwbuffer;		/* 0x2200 */
646};
647/*
648*********************************************************************
649**     Messaging Unit (MU) of Type E processor(LSI)
650*********************************************************************
651*/
652struct MessageUnit_E{
653	uint32_t	iobound_doorbell;			/*0000 0003*/
654	uint32_t	write_sequence_3xxx;			/*0004 0007*/
655	uint32_t	host_diagnostic_3xxx;			/*0008 000B*/
656	uint32_t	posted_outbound_doorbell;		/*000C 000F*/
657	uint32_t	master_error_attribute;			/*0010 0013*/
658	uint32_t	master_error_address_low;		/*0014 0017*/
659	uint32_t	master_error_address_high;		/*0018 001B*/
660	uint32_t	hcb_size;				/*001C 001F*/
661	uint32_t	inbound_doorbell;			/*0020 0023*/
662	uint32_t	diagnostic_rw_data;			/*0024 0027*/
663	uint32_t	diagnostic_rw_address_low;		/*0028 002B*/
664	uint32_t	diagnostic_rw_address_high;		/*002C 002F*/
665	uint32_t	host_int_status;			/*0030 0033*/
666	uint32_t	host_int_mask;				/*0034 0037*/
667	uint32_t	dcr_data;				/*0038 003B*/
668	uint32_t	dcr_address;				/*003C 003F*/
669	uint32_t	inbound_queueport;			/*0040 0043*/
670	uint32_t	outbound_queueport;			/*0044 0047*/
671	uint32_t	hcb_pci_address_low;			/*0048 004B*/
672	uint32_t	hcb_pci_address_high;			/*004C 004F*/
673	uint32_t	iop_int_status;				/*0050 0053*/
674	uint32_t	iop_int_mask;				/*0054 0057*/
675	uint32_t	iop_inbound_queue_port;			/*0058 005B*/
676	uint32_t	iop_outbound_queue_port;		/*005C 005F*/
677	uint32_t	inbound_free_list_index;		/*0060 0063*/
678	uint32_t	inbound_post_list_index;		/*0064 0067*/
679	uint32_t	reply_post_producer_index;		/*0068 006B*/
680	uint32_t	reply_post_consumer_index;		/*006C 006F*/
681	uint32_t	inbound_doorbell_clear;			/*0070 0073*/
682	uint32_t	i2o_message_unit_control;		/*0074 0077*/
683	uint32_t	last_used_message_source_address_low;	/*0078 007B*/
684	uint32_t	last_used_message_source_address_high;	/*007C 007F*/
685	uint32_t	pull_mode_data_byte_count[4];		/*0080 008F*/
686	uint32_t	message_dest_address_index;		/*0090 0093*/
687	uint32_t	done_queue_not_empty_int_counter_timer;	/*0094 0097*/
688	uint32_t	utility_A_int_counter_timer;		/*0098 009B*/
689	uint32_t	outbound_doorbell;			/*009C 009F*/
690	uint32_t	outbound_doorbell_clear;		/*00A0 00A3*/
691	uint32_t	message_source_address_index;		/*00A4 00A7*/
692	uint32_t	message_done_queue_index;		/*00A8 00AB*/
693	uint32_t	reserved0;				/*00AC 00AF*/
694	uint32_t	inbound_msgaddr0;			/*00B0 00B3*/
695	uint32_t	inbound_msgaddr1;			/*00B4 00B7*/
696	uint32_t	outbound_msgaddr0;			/*00B8 00BB*/
697	uint32_t	outbound_msgaddr1;			/*00BC 00BF*/
698	uint32_t	inbound_queueport_low;			/*00C0 00C3*/
699	uint32_t	inbound_queueport_high;			/*00C4 00C7*/
700	uint32_t	outbound_queueport_low;			/*00C8 00CB*/
701	uint32_t	outbound_queueport_high;		/*00CC 00CF*/
702	uint32_t	iop_inbound_queue_port_low;		/*00D0 00D3*/
703	uint32_t	iop_inbound_queue_port_high;		/*00D4 00D7*/
704	uint32_t	iop_outbound_queue_port_low;		/*00D8 00DB*/
705	uint32_t	iop_outbound_queue_port_high;		/*00DC 00DF*/
706	uint32_t	message_dest_queue_port_low;		/*00E0 00E3*/
707	uint32_t	message_dest_queue_port_high;		/*00E4 00E7*/
708	uint32_t	last_used_message_dest_address_low;	/*00E8 00EB*/
709	uint32_t	last_used_message_dest_address_high;	/*00EC 00EF*/
710	uint32_t	message_done_queue_base_address_low;	/*00F0 00F3*/
711	uint32_t	message_done_queue_base_address_high;	/*00F4 00F7*/
712	uint32_t	host_diagnostic;			/*00F8 00FB*/
713	uint32_t	write_sequence;				/*00FC 00FF*/
714	uint32_t	reserved1[34];				/*0100 0187*/
715	uint32_t	reserved2[1950];			/*0188 1FFF*/
716	uint32_t	message_wbuffer[32];			/*2000 207F*/
717	uint32_t	reserved3[32];				/*2080 20FF*/
718	uint32_t	message_rbuffer[32];			/*2100 217F*/
719	uint32_t	reserved4[32];				/*2180 21FF*/
720	uint32_t	msgcode_rwbuffer[256];			/*2200 23FF*/
721};
722
723typedef struct deliver_completeQ {
724	uint16_t	cmdFlag;
725	uint16_t	cmdSMID;
726	uint16_t	cmdLMID;        // reserved (0)
727	uint16_t	cmdFlag2;       // reserved (0)
728} DeliverQ, CompletionQ, *pDeliver_Q, *pCompletion_Q;
729/*
730*******************************************************************************
731**                 Adapter Control Block
732*******************************************************************************
733*/
734struct AdapterControlBlock
735{
736	uint32_t		adapter_type;		/* adapter A,B..... */
737#define ACB_ADAPTER_TYPE_A		0x00000000	/* hba I IOP */
738#define ACB_ADAPTER_TYPE_B		0x00000001	/* hbb M IOP */
739#define ACB_ADAPTER_TYPE_C		0x00000002	/* hbc L IOP */
740#define ACB_ADAPTER_TYPE_D		0x00000003	/* hbd M IOP */
741#define ACB_ADAPTER_TYPE_E		0x00000004	/* hba L IOP */
742	u32			ioqueue_size;
743	struct pci_dev *	pdev;
744	struct Scsi_Host *	host;
745	unsigned long		vir2phy_offset;
746	/* Offset is used in making arc cdb physical to virtual calculations */
747	uint32_t		outbound_int_enable;
748	uint32_t		cdb_phyaddr_hi32;
749	uint32_t		reg_mu_acc_handle0;
750	uint64_t		cdb_phyadd_hipart;
751	spinlock_t		eh_lock;
752	spinlock_t		ccblist_lock;
753	spinlock_t		postq_lock;
754	spinlock_t		doneq_lock;
755	spinlock_t		rqbuffer_lock;
756	spinlock_t		wqbuffer_lock;
757	union {
758		struct MessageUnit_A __iomem *pmuA;
759		struct MessageUnit_B 	*pmuB;
760		struct MessageUnit_C __iomem *pmuC;
761		struct MessageUnit_D 	*pmuD;
762		struct MessageUnit_E __iomem *pmuE;
763	};
764	/* message unit ATU inbound base address0 */
765	void __iomem		*mem_base0;
766	void __iomem		*mem_base1;
767	uint32_t		acb_flags;
768	u16			dev_id;
769	uint8_t			adapter_index;
770#define ACB_F_SCSISTOPADAPTER         	0x0001
771#define ACB_F_MSG_STOP_BGRB     	0x0002
772/* stop RAID background rebuild */
773#define ACB_F_MSG_START_BGRB          	0x0004
774/* stop RAID background rebuild */
775#define ACB_F_IOPDATA_OVERFLOW        	0x0008
776/* iop message data rqbuffer overflow */
777#define ACB_F_MESSAGE_WQBUFFER_CLEARED	0x0010
778/* message clear wqbuffer */
779#define ACB_F_MESSAGE_RQBUFFER_CLEARED  0x0020
780/* message clear rqbuffer */
781#define ACB_F_MESSAGE_WQBUFFER_READED   0x0040
782#define ACB_F_BUS_RESET               	0x0080
783
784#define ACB_F_IOP_INITED              	0x0100
785/* iop init */
786#define ACB_F_ABORT			0x0200
787#define ACB_F_FIRMWARE_TRAP           	0x0400
788#define ACB_F_ADAPTER_REMOVED		0x0800
789#define ACB_F_MSG_GET_CONFIG		0x1000
790	struct CommandControlBlock *	pccb_pool[ARCMSR_MAX_FREECCB_NUM];
791	/* used for memory free */
792	struct list_head	ccb_free_list;
793	/* head of free ccb list */
794
795	atomic_t		ccboutstandingcount;
796	/*The present outstanding command number that in the IOP that
797					waiting for being handled by FW*/
798
799	void *			dma_coherent;
800	/* dma_coherent used for memory free */
801	dma_addr_t		dma_coherent_handle;
802	/* dma_coherent_handle used for memory free */
803	dma_addr_t		dma_coherent_handle2;
804	void			*dma_coherent2;
805	unsigned int		uncache_size;
806	uint8_t			rqbuffer[ARCMSR_MAX_QBUFFER];
807	/* data collection buffer for read from 80331 */
808	int32_t			rqbuf_getIndex;
809	/* first of read buffer  */
810	int32_t			rqbuf_putIndex;
811	/* last of read buffer   */
812	uint8_t			wqbuffer[ARCMSR_MAX_QBUFFER];
813	/* data collection buffer for write to 80331  */
814	int32_t			wqbuf_getIndex;
815	/* first of write buffer */
816	int32_t			wqbuf_putIndex;
817	/* last of write buffer  */
818	uint8_t			devstate[ARCMSR_MAX_TARGETID][ARCMSR_MAX_TARGETLUN];
819	/* id0 ..... id15, lun0...lun7 */
820#define ARECA_RAID_GONE			0x55
821#define ARECA_RAID_GOOD			0xaa
822	uint32_t		num_resets;
823	uint32_t		num_aborts;
824	uint32_t		signature;
825	uint32_t		firm_request_len;
826	uint32_t		firm_numbers_queue;
827	uint32_t		firm_sdram_size;
828	uint32_t		firm_hd_channels;
829	uint32_t		firm_cfg_version;
830	char			firm_model[12];
831	char			firm_version[20];
832	char			device_map[20];			/*21,84-99*/
833	struct work_struct 	arcmsr_do_message_isr_bh;
834	struct timer_list	eternal_timer;
835	unsigned short		fw_flag;
836#define	FW_NORMAL			0x0000
837#define	FW_BOG				0x0001
838#define	FW_DEADLOCK			0x0010
839	atomic_t 		rq_map_token;
840	atomic_t		ante_token_value;
841	uint32_t		maxOutstanding;
842	int			vector_count;
843	uint32_t		maxFreeCCB;
844	struct timer_list	refresh_timer;
845	uint32_t		doneq_index;
846	uint32_t		ccbsize;
847	uint32_t		in_doorbell;
848	uint32_t		out_doorbell;
849	uint32_t		completionQ_entry;
850	pCompletion_Q		pCompletionQ;
851};/* HW_DEVICE_EXTENSION */
852/*
853*******************************************************************************
854**                   Command Control Block
855**             this CCB length must be 32 bytes boundary
856*******************************************************************************
857*/
858struct CommandControlBlock{
859	/*x32:sizeof struct_CCB=(64+60)byte, x64:sizeof struct_CCB=(64+60)byte*/
860	struct list_head		list;		/*x32: 8byte, x64: 16byte*/
861	struct scsi_cmnd		*pcmd;		/*8 bytes pointer of linux scsi command */
862	struct AdapterControlBlock	*acb;		/*x32: 4byte, x64: 8byte*/
863	unsigned long			cdb_phyaddr;	/*x32: 4byte, x64: 8byte*/
864	uint32_t			arc_cdb_size;	/*x32:4byte,x64:4byte*/
865	uint16_t			ccb_flags;	/*x32: 2byte, x64: 2byte*/
866#define	CCB_FLAG_READ		0x0000
867#define	CCB_FLAG_WRITE		0x0001
868#define	CCB_FLAG_ERROR		0x0002
869#define	CCB_FLAG_FLUSHCACHE	0x0004
870#define	CCB_FLAG_MASTER_ABORTED	0x0008
871	uint16_t                        startdone;	/*x32:2byte,x32:2byte*/
872#define	ARCMSR_CCB_DONE		0x0000
873#define	ARCMSR_CCB_START	0x55AA
874#define	ARCMSR_CCB_ABORTED	0xAA55
875#define	ARCMSR_CCB_ILLEGAL	0xFFFF
876	uint32_t			smid;
877#if BITS_PER_LONG == 64
878	/*  ======================512+64 bytes========================  */
879		uint32_t		reserved[3];	/*12 byte*/
880#else
881	/*  ======================512+32 bytes========================  */
882		uint32_t		reserved[8];	/*32  byte*/
883#endif
884	/*  =======================================================   */
885	struct ARCMSR_CDB		arcmsr_cdb;
886};
887/*
888*******************************************************************************
889**    ARECA SCSI sense data
890*******************************************************************************
891*/
892struct SENSE_DATA
893{
894	uint8_t				ErrorCode:7;
895#define SCSI_SENSE_CURRENT_ERRORS	0x70
896#define SCSI_SENSE_DEFERRED_ERRORS	0x71
897	uint8_t				Valid:1;
898	uint8_t				SegmentNumber;
899	uint8_t				SenseKey:4;
900	uint8_t				Reserved:1;
901	uint8_t				IncorrectLength:1;
902	uint8_t				EndOfMedia:1;
903	uint8_t				FileMark:1;
904	uint8_t				Information[4];
905	uint8_t				AdditionalSenseLength;
906	uint8_t				CommandSpecificInformation[4];
907	uint8_t				AdditionalSenseCode;
908	uint8_t				AdditionalSenseCodeQualifier;
909	uint8_t				FieldReplaceableUnitCode;
910	uint8_t				SenseKeySpecific[3];
911};
912/*
913*******************************************************************************
914**  Outbound Interrupt Status Register - OISR
915*******************************************************************************
916*/
917#define	ARCMSR_MU_OUTBOUND_INTERRUPT_STATUS_REG	0x30
918#define	ARCMSR_MU_OUTBOUND_PCI_INT		0x10
919#define	ARCMSR_MU_OUTBOUND_POSTQUEUE_INT	0x08
920#define	ARCMSR_MU_OUTBOUND_DOORBELL_INT		0x04
921#define	ARCMSR_MU_OUTBOUND_MESSAGE1_INT		0x02
922#define	ARCMSR_MU_OUTBOUND_MESSAGE0_INT		0x01
923#define	ARCMSR_MU_OUTBOUND_HANDLE_INT                     \
924                    (ARCMSR_MU_OUTBOUND_MESSAGE0_INT      \
925                     |ARCMSR_MU_OUTBOUND_MESSAGE1_INT     \
926                     |ARCMSR_MU_OUTBOUND_DOORBELL_INT     \
927                     |ARCMSR_MU_OUTBOUND_POSTQUEUE_INT    \
928                     |ARCMSR_MU_OUTBOUND_PCI_INT)
929/*
930*******************************************************************************
931**  Outbound Interrupt Mask Register - OIMR
932*******************************************************************************
933*/
934#define	ARCMSR_MU_OUTBOUND_INTERRUPT_MASK_REG		0x34
935#define	ARCMSR_MU_OUTBOUND_PCI_INTMASKENABLE		0x10
936#define	ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE	0x08
937#define	ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE	0x04
938#define	ARCMSR_MU_OUTBOUND_MESSAGE1_INTMASKENABLE	0x02
939#define	ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE	0x01
940#define	ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE		0x1F
941
942extern void arcmsr_write_ioctldata2iop(struct AdapterControlBlock *);
943extern uint32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *,
944	struct QBUFFER __iomem *);
945extern void arcmsr_clear_iop2drv_rqueue_buffer(struct AdapterControlBlock *);
946extern struct QBUFFER __iomem *arcmsr_get_iop_rqbuffer(struct AdapterControlBlock *);
947extern struct device_attribute *arcmsr_host_attrs[];
948extern int arcmsr_alloc_sysfs_attr(struct AdapterControlBlock *);
949void arcmsr_free_sysfs_attr(struct AdapterControlBlock *acb);