/drivers/scsi/aic7xxx/aic79xx_pci.c

http://github.com/mirrors/linux · C · 1006 lines · 733 code · 123 blank · 150 comment · 155 complexity · 57cc25398c60aff86a3d694ba1bd5646 MD5 · raw file

  1. /*
  2. * Product specific probe and attach routines for:
  3. * aic7901 and aic7902 SCSI controllers
  4. *
  5. * Copyright (c) 1994-2001 Justin T. Gibbs.
  6. * Copyright (c) 2000-2002 Adaptec Inc.
  7. * All rights reserved.
  8. *
  9. * Redistribution and use in source and binary forms, with or without
  10. * modification, are permitted provided that the following conditions
  11. * are met:
  12. * 1. Redistributions of source code must retain the above copyright
  13. * notice, this list of conditions, and the following disclaimer,
  14. * without modification.
  15. * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  16. * substantially similar to the "NO WARRANTY" disclaimer below
  17. * ("Disclaimer") and any redistribution must be conditioned upon
  18. * including a substantially similar Disclaimer requirement for further
  19. * binary redistribution.
  20. * 3. Neither the names of the above-listed copyright holders nor the names
  21. * of any contributors may be used to endorse or promote products derived
  22. * from this software without specific prior written permission.
  23. *
  24. * Alternatively, this software may be distributed under the terms of the
  25. * GNU General Public License ("GPL") version 2 as published by the Free
  26. * Software Foundation.
  27. *
  28. * NO WARRANTY
  29. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  32. * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33. * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  34. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  35. * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  36. * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  37. * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  38. * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  39. * POSSIBILITY OF SUCH DAMAGES.
  40. *
  41. * $Id: //depot/aic7xxx/aic7xxx/aic79xx_pci.c#92 $
  42. */
  43. #include "aic79xx_osm.h"
  44. #include "aic79xx_inline.h"
  45. #include "aic79xx_pci.h"
  46. static inline uint64_t
  47. ahd_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor)
  48. {
  49. uint64_t id;
  50. id = subvendor
  51. | (subdevice << 16)
  52. | ((uint64_t)vendor << 32)
  53. | ((uint64_t)device << 48);
  54. return (id);
  55. }
  56. #define ID_AIC7902_PCI_REV_A4 0x3
  57. #define ID_AIC7902_PCI_REV_B0 0x10
  58. #define SUBID_HP 0x0E11
  59. #define DEVID_9005_HOSTRAID(id) ((id) & 0x80)
  60. #define DEVID_9005_TYPE(id) ((id) & 0xF)
  61. #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */
  62. #define DEVID_9005_TYPE_HBA_2EXT 0x1 /* 2 External Ports */
  63. #define DEVID_9005_TYPE_IROC 0x8 /* Raid(0,1,10) Card */
  64. #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */
  65. #define DEVID_9005_MFUNC(id) ((id) & 0x10)
  66. #define DEVID_9005_PACKETIZED(id) ((id) & 0x8000)
  67. #define SUBID_9005_TYPE(id) ((id) & 0xF)
  68. #define SUBID_9005_TYPE_HBA 0x0 /* Standard Card */
  69. #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */
  70. #define SUBID_9005_AUTOTERM(id) (((id) & 0x10) == 0)
  71. #define SUBID_9005_LEGACYCONN_FUNC(id) ((id) & 0x20)
  72. #define SUBID_9005_SEEPTYPE(id) (((id) & 0x0C0) >> 6)
  73. #define SUBID_9005_SEEPTYPE_NONE 0x0
  74. #define SUBID_9005_SEEPTYPE_4K 0x1
  75. static ahd_device_setup_t ahd_aic7901_setup;
  76. static ahd_device_setup_t ahd_aic7901A_setup;
  77. static ahd_device_setup_t ahd_aic7902_setup;
  78. static ahd_device_setup_t ahd_aic790X_setup;
  79. static const struct ahd_pci_identity ahd_pci_ident_table[] =
  80. {
  81. /* aic7901 based controllers */
  82. {
  83. ID_AHA_29320A,
  84. ID_ALL_MASK,
  85. "Adaptec 29320A Ultra320 SCSI adapter",
  86. ahd_aic7901_setup
  87. },
  88. {
  89. ID_AHA_29320ALP,
  90. ID_ALL_MASK,
  91. "Adaptec 29320ALP PCIx Ultra320 SCSI adapter",
  92. ahd_aic7901_setup
  93. },
  94. {
  95. ID_AHA_29320LPE,
  96. ID_ALL_MASK,
  97. "Adaptec 29320LPE PCIe Ultra320 SCSI adapter",
  98. ahd_aic7901_setup
  99. },
  100. /* aic7901A based controllers */
  101. {
  102. ID_AHA_29320LP,
  103. ID_ALL_MASK,
  104. "Adaptec 29320LP Ultra320 SCSI adapter",
  105. ahd_aic7901A_setup
  106. },
  107. /* aic7902 based controllers */
  108. {
  109. ID_AHA_29320,
  110. ID_ALL_MASK,
  111. "Adaptec 29320 Ultra320 SCSI adapter",
  112. ahd_aic7902_setup
  113. },
  114. {
  115. ID_AHA_29320B,
  116. ID_ALL_MASK,
  117. "Adaptec 29320B Ultra320 SCSI adapter",
  118. ahd_aic7902_setup
  119. },
  120. {
  121. ID_AHA_39320,
  122. ID_ALL_MASK,
  123. "Adaptec 39320 Ultra320 SCSI adapter",
  124. ahd_aic7902_setup
  125. },
  126. {
  127. ID_AHA_39320_B,
  128. ID_ALL_MASK,
  129. "Adaptec 39320 Ultra320 SCSI adapter",
  130. ahd_aic7902_setup
  131. },
  132. {
  133. ID_AHA_39320_B_DELL,
  134. ID_ALL_MASK,
  135. "Adaptec (Dell OEM) 39320 Ultra320 SCSI adapter",
  136. ahd_aic7902_setup
  137. },
  138. {
  139. ID_AHA_39320A,
  140. ID_ALL_MASK,
  141. "Adaptec 39320A Ultra320 SCSI adapter",
  142. ahd_aic7902_setup
  143. },
  144. {
  145. ID_AHA_39320D,
  146. ID_ALL_MASK,
  147. "Adaptec 39320D Ultra320 SCSI adapter",
  148. ahd_aic7902_setup
  149. },
  150. {
  151. ID_AHA_39320D_HP,
  152. ID_ALL_MASK,
  153. "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter",
  154. ahd_aic7902_setup
  155. },
  156. {
  157. ID_AHA_39320D_B,
  158. ID_ALL_MASK,
  159. "Adaptec 39320D Ultra320 SCSI adapter",
  160. ahd_aic7902_setup
  161. },
  162. {
  163. ID_AHA_39320D_B_HP,
  164. ID_ALL_MASK,
  165. "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter",
  166. ahd_aic7902_setup
  167. },
  168. /* Generic chip probes for devices we don't know 'exactly' */
  169. {
  170. ID_AIC7901 & ID_9005_GENERIC_MASK,
  171. ID_9005_GENERIC_MASK,
  172. "Adaptec AIC7901 Ultra320 SCSI adapter",
  173. ahd_aic7901_setup
  174. },
  175. {
  176. ID_AIC7901A & ID_DEV_VENDOR_MASK,
  177. ID_DEV_VENDOR_MASK,
  178. "Adaptec AIC7901A Ultra320 SCSI adapter",
  179. ahd_aic7901A_setup
  180. },
  181. {
  182. ID_AIC7902 & ID_9005_GENERIC_MASK,
  183. ID_9005_GENERIC_MASK,
  184. "Adaptec AIC7902 Ultra320 SCSI adapter",
  185. ahd_aic7902_setup
  186. }
  187. };
  188. static const u_int ahd_num_pci_devs = ARRAY_SIZE(ahd_pci_ident_table);
  189. #define DEVCONFIG 0x40
  190. #define PCIXINITPAT 0x0000E000ul
  191. #define PCIXINIT_PCI33_66 0x0000E000ul
  192. #define PCIXINIT_PCIX50_66 0x0000C000ul
  193. #define PCIXINIT_PCIX66_100 0x0000A000ul
  194. #define PCIXINIT_PCIX100_133 0x00008000ul
  195. #define PCI_BUS_MODES_INDEX(devconfig) \
  196. (((devconfig) & PCIXINITPAT) >> 13)
  197. static const char *pci_bus_modes[] =
  198. {
  199. "PCI bus mode unknown",
  200. "PCI bus mode unknown",
  201. "PCI bus mode unknown",
  202. "PCI bus mode unknown",
  203. "PCI-X 101-133MHz",
  204. "PCI-X 67-100MHz",
  205. "PCI-X 50-66MHz",
  206. "PCI 33 or 66MHz"
  207. };
  208. #define TESTMODE 0x00000800ul
  209. #define IRDY_RST 0x00000200ul
  210. #define FRAME_RST 0x00000100ul
  211. #define PCI64BIT 0x00000080ul
  212. #define MRDCEN 0x00000040ul
  213. #define ENDIANSEL 0x00000020ul
  214. #define MIXQWENDIANEN 0x00000008ul
  215. #define DACEN 0x00000004ul
  216. #define STPWLEVEL 0x00000002ul
  217. #define QWENDIANSEL 0x00000001ul
  218. #define DEVCONFIG1 0x44
  219. #define PREQDIS 0x01
  220. #define CSIZE_LATTIME 0x0c
  221. #define CACHESIZE 0x000000fful
  222. #define LATTIME 0x0000ff00ul
  223. static int ahd_check_extport(struct ahd_softc *ahd);
  224. static void ahd_configure_termination(struct ahd_softc *ahd,
  225. u_int adapter_control);
  226. static void ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat);
  227. static void ahd_pci_intr(struct ahd_softc *ahd);
  228. const struct ahd_pci_identity *
  229. ahd_find_pci_device(ahd_dev_softc_t pci)
  230. {
  231. uint64_t full_id;
  232. uint16_t device;
  233. uint16_t vendor;
  234. uint16_t subdevice;
  235. uint16_t subvendor;
  236. const struct ahd_pci_identity *entry;
  237. u_int i;
  238. vendor = ahd_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2);
  239. device = ahd_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2);
  240. subvendor = ahd_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2);
  241. subdevice = ahd_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2);
  242. full_id = ahd_compose_id(device,
  243. vendor,
  244. subdevice,
  245. subvendor);
  246. /*
  247. * Controllers, mask out the IROC/HostRAID bit
  248. */
  249. full_id &= ID_ALL_IROC_MASK;
  250. for (i = 0; i < ahd_num_pci_devs; i++) {
  251. entry = &ahd_pci_ident_table[i];
  252. if (entry->full_id == (full_id & entry->id_mask)) {
  253. /* Honor exclusion entries. */
  254. if (entry->name == NULL)
  255. return (NULL);
  256. return (entry);
  257. }
  258. }
  259. return (NULL);
  260. }
  261. int
  262. ahd_pci_config(struct ahd_softc *ahd, const struct ahd_pci_identity *entry)
  263. {
  264. u_int command;
  265. uint32_t devconfig;
  266. uint16_t subvendor;
  267. int error;
  268. ahd->description = entry->name;
  269. /*
  270. * Record if this is an HP board.
  271. */
  272. subvendor = ahd_pci_read_config(ahd->dev_softc,
  273. PCIR_SUBVEND_0, /*bytes*/2);
  274. if (subvendor == SUBID_HP)
  275. ahd->flags |= AHD_HP_BOARD;
  276. error = entry->setup(ahd);
  277. if (error != 0)
  278. return (error);
  279. devconfig = ahd_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4);
  280. if ((devconfig & PCIXINITPAT) == PCIXINIT_PCI33_66) {
  281. ahd->chip |= AHD_PCI;
  282. /* Disable PCIX workarounds when running in PCI mode. */
  283. ahd->bugs &= ~AHD_PCIX_BUG_MASK;
  284. } else {
  285. ahd->chip |= AHD_PCIX;
  286. }
  287. ahd->bus_description = pci_bus_modes[PCI_BUS_MODES_INDEX(devconfig)];
  288. ahd_power_state_change(ahd, AHD_POWER_STATE_D0);
  289. error = ahd_pci_map_registers(ahd);
  290. if (error != 0)
  291. return (error);
  292. /*
  293. * If we need to support high memory, enable dual
  294. * address cycles. This bit must be set to enable
  295. * high address bit generation even if we are on a
  296. * 64bit bus (PCI64BIT set in devconfig).
  297. */
  298. if ((ahd->flags & (AHD_39BIT_ADDRESSING|AHD_64BIT_ADDRESSING)) != 0) {
  299. if (bootverbose)
  300. printk("%s: Enabling 39Bit Addressing\n",
  301. ahd_name(ahd));
  302. devconfig = ahd_pci_read_config(ahd->dev_softc,
  303. DEVCONFIG, /*bytes*/4);
  304. devconfig |= DACEN;
  305. ahd_pci_write_config(ahd->dev_softc, DEVCONFIG,
  306. devconfig, /*bytes*/4);
  307. }
  308. /* Ensure busmastering is enabled */
  309. command = ahd_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2);
  310. command |= PCIM_CMD_BUSMASTEREN;
  311. ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND, command, /*bytes*/2);
  312. error = ahd_softc_init(ahd);
  313. if (error != 0)
  314. return (error);
  315. ahd->bus_intr = ahd_pci_intr;
  316. error = ahd_reset(ahd, /*reinit*/FALSE);
  317. if (error != 0)
  318. return (ENXIO);
  319. ahd->pci_cachesize =
  320. ahd_pci_read_config(ahd->dev_softc, CSIZE_LATTIME,
  321. /*bytes*/1) & CACHESIZE;
  322. ahd->pci_cachesize *= 4;
  323. ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
  324. /* See if we have a SEEPROM and perform auto-term */
  325. error = ahd_check_extport(ahd);
  326. if (error != 0)
  327. return (error);
  328. /* Core initialization */
  329. error = ahd_init(ahd);
  330. if (error != 0)
  331. return (error);
  332. ahd->init_level++;
  333. /*
  334. * Allow interrupts now that we are completely setup.
  335. */
  336. return ahd_pci_map_int(ahd);
  337. }
  338. #ifdef CONFIG_PM
  339. void
  340. ahd_pci_suspend(struct ahd_softc *ahd)
  341. {
  342. /*
  343. * Save chip register configuration data for chip resets
  344. * that occur during runtime and resume events.
  345. */
  346. ahd->suspend_state.pci_state.devconfig =
  347. ahd_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4);
  348. ahd->suspend_state.pci_state.command =
  349. ahd_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/1);
  350. ahd->suspend_state.pci_state.csize_lattime =
  351. ahd_pci_read_config(ahd->dev_softc, CSIZE_LATTIME, /*bytes*/1);
  352. }
  353. void
  354. ahd_pci_resume(struct ahd_softc *ahd)
  355. {
  356. ahd_pci_write_config(ahd->dev_softc, DEVCONFIG,
  357. ahd->suspend_state.pci_state.devconfig, /*bytes*/4);
  358. ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND,
  359. ahd->suspend_state.pci_state.command, /*bytes*/1);
  360. ahd_pci_write_config(ahd->dev_softc, CSIZE_LATTIME,
  361. ahd->suspend_state.pci_state.csize_lattime, /*bytes*/1);
  362. }
  363. #endif
  364. /*
  365. * Perform some simple tests that should catch situations where
  366. * our registers are invalidly mapped.
  367. */
  368. int
  369. ahd_pci_test_register_access(struct ahd_softc *ahd)
  370. {
  371. uint32_t cmd;
  372. u_int targpcistat;
  373. u_int pci_status1;
  374. int error;
  375. uint8_t hcntrl;
  376. error = EIO;
  377. /*
  378. * Enable PCI error interrupt status, but suppress NMIs
  379. * generated by SERR raised due to target aborts.
  380. */
  381. cmd = ahd_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2);
  382. ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND,
  383. cmd & ~PCIM_CMD_SERRESPEN, /*bytes*/2);
  384. /*
  385. * First a simple test to see if any
  386. * registers can be read. Reading
  387. * HCNTRL has no side effects and has
  388. * at least one bit that is guaranteed to
  389. * be zero so it is a good register to
  390. * use for this test.
  391. */
  392. hcntrl = ahd_inb(ahd, HCNTRL);
  393. if (hcntrl == 0xFF)
  394. goto fail;
  395. /*
  396. * Next create a situation where write combining
  397. * or read prefetching could be initiated by the
  398. * CPU or host bridge. Our device does not support
  399. * either, so look for data corruption and/or flaged
  400. * PCI errors. First pause without causing another
  401. * chip reset.
  402. */
  403. hcntrl &= ~CHIPRST;
  404. ahd_outb(ahd, HCNTRL, hcntrl|PAUSE);
  405. while (ahd_is_paused(ahd) == 0)
  406. ;
  407. /* Clear any PCI errors that occurred before our driver attached. */
  408. ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
  409. targpcistat = ahd_inb(ahd, TARGPCISTAT);
  410. ahd_outb(ahd, TARGPCISTAT, targpcistat);
  411. pci_status1 = ahd_pci_read_config(ahd->dev_softc,
  412. PCIR_STATUS + 1, /*bytes*/1);
  413. ahd_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1,
  414. pci_status1, /*bytes*/1);
  415. ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
  416. ahd_outb(ahd, CLRINT, CLRPCIINT);
  417. ahd_outb(ahd, SEQCTL0, PERRORDIS);
  418. ahd_outl(ahd, SRAM_BASE, 0x5aa555aa);
  419. if (ahd_inl(ahd, SRAM_BASE) != 0x5aa555aa)
  420. goto fail;
  421. if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) {
  422. ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
  423. targpcistat = ahd_inb(ahd, TARGPCISTAT);
  424. if ((targpcistat & STA) != 0)
  425. goto fail;
  426. }
  427. error = 0;
  428. fail:
  429. if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) {
  430. ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
  431. targpcistat = ahd_inb(ahd, TARGPCISTAT);
  432. /* Silently clear any latched errors. */
  433. ahd_outb(ahd, TARGPCISTAT, targpcistat);
  434. pci_status1 = ahd_pci_read_config(ahd->dev_softc,
  435. PCIR_STATUS + 1, /*bytes*/1);
  436. ahd_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1,
  437. pci_status1, /*bytes*/1);
  438. ahd_outb(ahd, CLRINT, CLRPCIINT);
  439. }
  440. ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS);
  441. ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2);
  442. return (error);
  443. }
  444. /*
  445. * Check the external port logic for a serial eeprom
  446. * and termination/cable detection contrls.
  447. */
  448. static int
  449. ahd_check_extport(struct ahd_softc *ahd)
  450. {
  451. struct vpd_config vpd;
  452. struct seeprom_config *sc;
  453. u_int adapter_control;
  454. int have_seeprom;
  455. int error;
  456. sc = ahd->seep_config;
  457. have_seeprom = ahd_acquire_seeprom(ahd);
  458. if (have_seeprom) {
  459. u_int start_addr;
  460. /*
  461. * Fetch VPD for this function and parse it.
  462. */
  463. if (bootverbose)
  464. printk("%s: Reading VPD from SEEPROM...",
  465. ahd_name(ahd));
  466. /* Address is always in units of 16bit words */
  467. start_addr = ((2 * sizeof(*sc))
  468. + (sizeof(vpd) * (ahd->channel - 'A'))) / 2;
  469. error = ahd_read_seeprom(ahd, (uint16_t *)&vpd,
  470. start_addr, sizeof(vpd)/2,
  471. /*bytestream*/TRUE);
  472. if (error == 0)
  473. error = ahd_parse_vpddata(ahd, &vpd);
  474. if (bootverbose)
  475. printk("%s: VPD parsing %s\n",
  476. ahd_name(ahd),
  477. error == 0 ? "successful" : "failed");
  478. if (bootverbose)
  479. printk("%s: Reading SEEPROM...", ahd_name(ahd));
  480. /* Address is always in units of 16bit words */
  481. start_addr = (sizeof(*sc) / 2) * (ahd->channel - 'A');
  482. error = ahd_read_seeprom(ahd, (uint16_t *)sc,
  483. start_addr, sizeof(*sc)/2,
  484. /*bytestream*/FALSE);
  485. if (error != 0) {
  486. printk("Unable to read SEEPROM\n");
  487. have_seeprom = 0;
  488. } else {
  489. have_seeprom = ahd_verify_cksum(sc);
  490. if (bootverbose) {
  491. if (have_seeprom == 0)
  492. printk ("checksum error\n");
  493. else
  494. printk ("done.\n");
  495. }
  496. }
  497. ahd_release_seeprom(ahd);
  498. }
  499. if (!have_seeprom) {
  500. u_int nvram_scb;
  501. /*
  502. * Pull scratch ram settings and treat them as
  503. * if they are the contents of an seeprom if
  504. * the 'ADPT', 'BIOS', or 'ASPI' signature is found
  505. * in SCB 0xFF. We manually compose the data as 16bit
  506. * values to avoid endian issues.
  507. */
  508. ahd_set_scbptr(ahd, 0xFF);
  509. nvram_scb = ahd_inb_scbram(ahd, SCB_BASE + NVRAM_SCB_OFFSET);
  510. if (nvram_scb != 0xFF
  511. && ((ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A'
  512. && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'D'
  513. && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P'
  514. && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'T')
  515. || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'B'
  516. && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'I'
  517. && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'O'
  518. && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'S')
  519. || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A'
  520. && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'S'
  521. && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P'
  522. && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'I'))) {
  523. uint16_t *sc_data;
  524. int i;
  525. ahd_set_scbptr(ahd, nvram_scb);
  526. sc_data = (uint16_t *)sc;
  527. for (i = 0; i < 64; i += 2)
  528. *sc_data++ = ahd_inw_scbram(ahd, SCB_BASE+i);
  529. have_seeprom = ahd_verify_cksum(sc);
  530. if (have_seeprom)
  531. ahd->flags |= AHD_SCB_CONFIG_USED;
  532. }
  533. }
  534. #ifdef AHD_DEBUG
  535. if (have_seeprom != 0
  536. && (ahd_debug & AHD_DUMP_SEEPROM) != 0) {
  537. uint16_t *sc_data;
  538. int i;
  539. printk("%s: Seeprom Contents:", ahd_name(ahd));
  540. sc_data = (uint16_t *)sc;
  541. for (i = 0; i < (sizeof(*sc)); i += 2)
  542. printk("\n\t0x%.4x", sc_data[i]);
  543. printk("\n");
  544. }
  545. #endif
  546. if (!have_seeprom) {
  547. if (bootverbose)
  548. printk("%s: No SEEPROM available.\n", ahd_name(ahd));
  549. ahd->flags |= AHD_USEDEFAULTS;
  550. error = ahd_default_config(ahd);
  551. adapter_control = CFAUTOTERM|CFSEAUTOTERM;
  552. kfree(ahd->seep_config);
  553. ahd->seep_config = NULL;
  554. } else {
  555. error = ahd_parse_cfgdata(ahd, sc);
  556. adapter_control = sc->adapter_control;
  557. }
  558. if (error != 0)
  559. return (error);
  560. ahd_configure_termination(ahd, adapter_control);
  561. return (0);
  562. }
  563. static void
  564. ahd_configure_termination(struct ahd_softc *ahd, u_int adapter_control)
  565. {
  566. int error;
  567. u_int sxfrctl1;
  568. uint8_t termctl;
  569. uint32_t devconfig;
  570. devconfig = ahd_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4);
  571. devconfig &= ~STPWLEVEL;
  572. if ((ahd->flags & AHD_STPWLEVEL_A) != 0)
  573. devconfig |= STPWLEVEL;
  574. if (bootverbose)
  575. printk("%s: STPWLEVEL is %s\n",
  576. ahd_name(ahd), (devconfig & STPWLEVEL) ? "on" : "off");
  577. ahd_pci_write_config(ahd->dev_softc, DEVCONFIG, devconfig, /*bytes*/4);
  578. /* Make sure current sensing is off. */
  579. if ((ahd->flags & AHD_CURRENT_SENSING) != 0) {
  580. (void)ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0);
  581. }
  582. /*
  583. * Read to sense. Write to set.
  584. */
  585. error = ahd_read_flexport(ahd, FLXADDR_TERMCTL, &termctl);
  586. if ((adapter_control & CFAUTOTERM) == 0) {
  587. if (bootverbose)
  588. printk("%s: Manual Primary Termination\n",
  589. ahd_name(ahd));
  590. termctl &= ~(FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH);
  591. if ((adapter_control & CFSTERM) != 0)
  592. termctl |= FLX_TERMCTL_ENPRILOW;
  593. if ((adapter_control & CFWSTERM) != 0)
  594. termctl |= FLX_TERMCTL_ENPRIHIGH;
  595. } else if (error != 0) {
  596. printk("%s: Primary Auto-Term Sensing failed! "
  597. "Using Defaults.\n", ahd_name(ahd));
  598. termctl = FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH;
  599. }
  600. if ((adapter_control & CFSEAUTOTERM) == 0) {
  601. if (bootverbose)
  602. printk("%s: Manual Secondary Termination\n",
  603. ahd_name(ahd));
  604. termctl &= ~(FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH);
  605. if ((adapter_control & CFSELOWTERM) != 0)
  606. termctl |= FLX_TERMCTL_ENSECLOW;
  607. if ((adapter_control & CFSEHIGHTERM) != 0)
  608. termctl |= FLX_TERMCTL_ENSECHIGH;
  609. } else if (error != 0) {
  610. printk("%s: Secondary Auto-Term Sensing failed! "
  611. "Using Defaults.\n", ahd_name(ahd));
  612. termctl |= FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH;
  613. }
  614. /*
  615. * Now set the termination based on what we found.
  616. */
  617. sxfrctl1 = ahd_inb(ahd, SXFRCTL1) & ~STPWEN;
  618. ahd->flags &= ~AHD_TERM_ENB_A;
  619. if ((termctl & FLX_TERMCTL_ENPRILOW) != 0) {
  620. ahd->flags |= AHD_TERM_ENB_A;
  621. sxfrctl1 |= STPWEN;
  622. }
  623. /* Must set the latch once in order to be effective. */
  624. ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN);
  625. ahd_outb(ahd, SXFRCTL1, sxfrctl1);
  626. error = ahd_write_flexport(ahd, FLXADDR_TERMCTL, termctl);
  627. if (error != 0) {
  628. printk("%s: Unable to set termination settings!\n",
  629. ahd_name(ahd));
  630. } else if (bootverbose) {
  631. printk("%s: Primary High byte termination %sabled\n",
  632. ahd_name(ahd),
  633. (termctl & FLX_TERMCTL_ENPRIHIGH) ? "En" : "Dis");
  634. printk("%s: Primary Low byte termination %sabled\n",
  635. ahd_name(ahd),
  636. (termctl & FLX_TERMCTL_ENPRILOW) ? "En" : "Dis");
  637. printk("%s: Secondary High byte termination %sabled\n",
  638. ahd_name(ahd),
  639. (termctl & FLX_TERMCTL_ENSECHIGH) ? "En" : "Dis");
  640. printk("%s: Secondary Low byte termination %sabled\n",
  641. ahd_name(ahd),
  642. (termctl & FLX_TERMCTL_ENSECLOW) ? "En" : "Dis");
  643. }
  644. return;
  645. }
  646. #define DPE 0x80
  647. #define SSE 0x40
  648. #define RMA 0x20
  649. #define RTA 0x10
  650. #define STA 0x08
  651. #define DPR 0x01
  652. static const char *split_status_source[] =
  653. {
  654. "DFF0",
  655. "DFF1",
  656. "OVLY",
  657. "CMC",
  658. };
  659. static const char *pci_status_source[] =
  660. {
  661. "DFF0",
  662. "DFF1",
  663. "SG",
  664. "CMC",
  665. "OVLY",
  666. "NONE",
  667. "MSI",
  668. "TARG"
  669. };
  670. static const char *split_status_strings[] =
  671. {
  672. "%s: Received split response in %s.\n",
  673. "%s: Received split completion error message in %s\n",
  674. "%s: Receive overrun in %s\n",
  675. "%s: Count not complete in %s\n",
  676. "%s: Split completion data bucket in %s\n",
  677. "%s: Split completion address error in %s\n",
  678. "%s: Split completion byte count error in %s\n",
  679. "%s: Signaled Target-abort to early terminate a split in %s\n"
  680. };
  681. static const char *pci_status_strings[] =
  682. {
  683. "%s: Data Parity Error has been reported via PERR# in %s\n",
  684. "%s: Target initial wait state error in %s\n",
  685. "%s: Split completion read data parity error in %s\n",
  686. "%s: Split completion address attribute parity error in %s\n",
  687. "%s: Received a Target Abort in %s\n",
  688. "%s: Received a Master Abort in %s\n",
  689. "%s: Signal System Error Detected in %s\n",
  690. "%s: Address or Write Phase Parity Error Detected in %s.\n"
  691. };
  692. static void
  693. ahd_pci_intr(struct ahd_softc *ahd)
  694. {
  695. uint8_t pci_status[8];
  696. ahd_mode_state saved_modes;
  697. u_int pci_status1;
  698. u_int intstat;
  699. u_int i;
  700. u_int reg;
  701. intstat = ahd_inb(ahd, INTSTAT);
  702. if ((intstat & SPLTINT) != 0)
  703. ahd_pci_split_intr(ahd, intstat);
  704. if ((intstat & PCIINT) == 0)
  705. return;
  706. printk("%s: PCI error Interrupt\n", ahd_name(ahd));
  707. saved_modes = ahd_save_modes(ahd);
  708. ahd_dump_card_state(ahd);
  709. ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
  710. for (i = 0, reg = DF0PCISTAT; i < 8; i++, reg++) {
  711. if (i == 5)
  712. continue;
  713. pci_status[i] = ahd_inb(ahd, reg);
  714. /* Clear latched errors. So our interrupt deasserts. */
  715. ahd_outb(ahd, reg, pci_status[i]);
  716. }
  717. for (i = 0; i < 8; i++) {
  718. u_int bit;
  719. if (i == 5)
  720. continue;
  721. for (bit = 0; bit < 8; bit++) {
  722. if ((pci_status[i] & (0x1 << bit)) != 0) {
  723. const char *s;
  724. s = pci_status_strings[bit];
  725. if (i == 7/*TARG*/ && bit == 3)
  726. s = "%s: Signaled Target Abort\n";
  727. printk(s, ahd_name(ahd), pci_status_source[i]);
  728. }
  729. }
  730. }
  731. pci_status1 = ahd_pci_read_config(ahd->dev_softc,
  732. PCIR_STATUS + 1, /*bytes*/1);
  733. ahd_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1,
  734. pci_status1, /*bytes*/1);
  735. ahd_restore_modes(ahd, saved_modes);
  736. ahd_outb(ahd, CLRINT, CLRPCIINT);
  737. ahd_unpause(ahd);
  738. }
  739. static void
  740. ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat)
  741. {
  742. uint8_t split_status[4];
  743. uint8_t split_status1[4];
  744. uint8_t sg_split_status[2];
  745. uint8_t sg_split_status1[2];
  746. ahd_mode_state saved_modes;
  747. u_int i;
  748. uint16_t pcix_status;
  749. /*
  750. * Check for splits in all modes. Modes 0 and 1
  751. * additionally have SG engine splits to look at.
  752. */
  753. pcix_status = ahd_pci_read_config(ahd->dev_softc, PCIXR_STATUS,
  754. /*bytes*/2);
  755. printk("%s: PCI Split Interrupt - PCI-X status = 0x%x\n",
  756. ahd_name(ahd), pcix_status);
  757. saved_modes = ahd_save_modes(ahd);
  758. for (i = 0; i < 4; i++) {
  759. ahd_set_modes(ahd, i, i);
  760. split_status[i] = ahd_inb(ahd, DCHSPLTSTAT0);
  761. split_status1[i] = ahd_inb(ahd, DCHSPLTSTAT1);
  762. /* Clear latched errors. So our interrupt deasserts. */
  763. ahd_outb(ahd, DCHSPLTSTAT0, split_status[i]);
  764. ahd_outb(ahd, DCHSPLTSTAT1, split_status1[i]);
  765. if (i > 1)
  766. continue;
  767. sg_split_status[i] = ahd_inb(ahd, SGSPLTSTAT0);
  768. sg_split_status1[i] = ahd_inb(ahd, SGSPLTSTAT1);
  769. /* Clear latched errors. So our interrupt deasserts. */
  770. ahd_outb(ahd, SGSPLTSTAT0, sg_split_status[i]);
  771. ahd_outb(ahd, SGSPLTSTAT1, sg_split_status1[i]);
  772. }
  773. for (i = 0; i < 4; i++) {
  774. u_int bit;
  775. for (bit = 0; bit < 8; bit++) {
  776. if ((split_status[i] & (0x1 << bit)) != 0)
  777. printk(split_status_strings[bit], ahd_name(ahd),
  778. split_status_source[i]);
  779. if (i > 1)
  780. continue;
  781. if ((sg_split_status[i] & (0x1 << bit)) != 0)
  782. printk(split_status_strings[bit], ahd_name(ahd), "SG");
  783. }
  784. }
  785. /*
  786. * Clear PCI-X status bits.
  787. */
  788. ahd_pci_write_config(ahd->dev_softc, PCIXR_STATUS,
  789. pcix_status, /*bytes*/2);
  790. ahd_outb(ahd, CLRINT, CLRSPLTINT);
  791. ahd_restore_modes(ahd, saved_modes);
  792. }
  793. static int
  794. ahd_aic7901_setup(struct ahd_softc *ahd)
  795. {
  796. ahd->chip = AHD_AIC7901;
  797. ahd->features = AHD_AIC7901_FE;
  798. return (ahd_aic790X_setup(ahd));
  799. }
  800. static int
  801. ahd_aic7901A_setup(struct ahd_softc *ahd)
  802. {
  803. ahd->chip = AHD_AIC7901A;
  804. ahd->features = AHD_AIC7901A_FE;
  805. return (ahd_aic790X_setup(ahd));
  806. }
  807. static int
  808. ahd_aic7902_setup(struct ahd_softc *ahd)
  809. {
  810. ahd->chip = AHD_AIC7902;
  811. ahd->features = AHD_AIC7902_FE;
  812. return (ahd_aic790X_setup(ahd));
  813. }
  814. static int
  815. ahd_aic790X_setup(struct ahd_softc *ahd)
  816. {
  817. ahd_dev_softc_t pci;
  818. u_int rev;
  819. pci = ahd->dev_softc;
  820. rev = ahd_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
  821. if (rev < ID_AIC7902_PCI_REV_A4) {
  822. printk("%s: Unable to attach to unsupported chip revision %d\n",
  823. ahd_name(ahd), rev);
  824. ahd_pci_write_config(pci, PCIR_COMMAND, 0, /*bytes*/2);
  825. return (ENXIO);
  826. }
  827. ahd->channel = ahd_get_pci_function(pci) + 'A';
  828. if (rev < ID_AIC7902_PCI_REV_B0) {
  829. /*
  830. * Enable A series workarounds.
  831. */
  832. ahd->bugs |= AHD_SENT_SCB_UPDATE_BUG|AHD_ABORT_LQI_BUG
  833. | AHD_PKT_BITBUCKET_BUG|AHD_LONG_SETIMO_BUG
  834. | AHD_NLQICRC_DELAYED_BUG|AHD_SCSIRST_BUG
  835. | AHD_LQO_ATNO_BUG|AHD_AUTOFLUSH_BUG
  836. | AHD_CLRLQO_AUTOCLR_BUG|AHD_PCIX_MMAPIO_BUG
  837. | AHD_PCIX_CHIPRST_BUG|AHD_PCIX_SCBRAM_RD_BUG
  838. | AHD_PKTIZED_STATUS_BUG|AHD_PKT_LUN_BUG
  839. | AHD_MDFF_WSCBPTR_BUG|AHD_REG_SLOW_SETTLE_BUG
  840. | AHD_SET_MODE_BUG|AHD_BUSFREEREV_BUG
  841. | AHD_NONPACKFIFO_BUG|AHD_PACED_NEGTABLE_BUG
  842. | AHD_FAINT_LED_BUG;
  843. /*
  844. * IO Cell parameter setup.
  845. */
  846. AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29);
  847. if ((ahd->flags & AHD_HP_BOARD) == 0)
  848. AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVA);
  849. } else {
  850. /* This is revision B and newer. */
  851. extern uint32_t aic79xx_slowcrc;
  852. u_int devconfig1;
  853. ahd->features |= AHD_RTI|AHD_NEW_IOCELL_OPTS
  854. | AHD_NEW_DFCNTRL_OPTS|AHD_FAST_CDB_DELIVERY
  855. | AHD_BUSFREEREV_BUG;
  856. ahd->bugs |= AHD_LQOOVERRUN_BUG|AHD_EARLY_REQ_BUG;
  857. /* If the user requested that the SLOWCRC bit to be set. */
  858. if (aic79xx_slowcrc)
  859. ahd->features |= AHD_AIC79XXB_SLOWCRC;
  860. /*
  861. * Some issues have been resolved in the 7901B.
  862. */
  863. if ((ahd->features & AHD_MULTI_FUNC) != 0)
  864. ahd->bugs |= AHD_INTCOLLISION_BUG|AHD_ABORT_LQI_BUG;
  865. /*
  866. * IO Cell parameter setup.
  867. */
  868. AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29);
  869. AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVB);
  870. AHD_SET_AMPLITUDE(ahd, AHD_AMPLITUDE_DEF);
  871. /*
  872. * Set the PREQDIS bit for H2B which disables some workaround
  873. * that doesn't work on regular PCI busses.
  874. * XXX - Find out exactly what this does from the hardware
  875. * folks!
  876. */
  877. devconfig1 = ahd_pci_read_config(pci, DEVCONFIG1, /*bytes*/1);
  878. ahd_pci_write_config(pci, DEVCONFIG1,
  879. devconfig1|PREQDIS, /*bytes*/1);
  880. devconfig1 = ahd_pci_read_config(pci, DEVCONFIG1, /*bytes*/1);
  881. }
  882. return (0);
  883. }