/drivers/scsi/aic7xxx/aic7xxx.seq

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  1. /*
  2. * Adaptec 274x/284x/294x device driver firmware for Linux and FreeBSD.
  3. *
  4. * Copyright (c) 1994-2001 Justin T. Gibbs.
  5. * Copyright (c) 2000-2001 Adaptec Inc.
  6. * All rights reserved.
  7. *
  8. * Redistribution and use in source and binary forms, with or without
  9. * modification, are permitted provided that the following conditions
  10. * are met:
  11. * 1. Redistributions of source code must retain the above copyright
  12. * notice, this list of conditions, and the following disclaimer,
  13. * without modification.
  14. * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  15. * substantially similar to the "NO WARRANTY" disclaimer below
  16. * ("Disclaimer") and any redistribution must be conditioned upon
  17. * including a substantially similar Disclaimer requirement for further
  18. * binary redistribution.
  19. * 3. Neither the names of the above-listed copyright holders nor the names
  20. * of any contributors may be used to endorse or promote products derived
  21. * from this software without specific prior written permission.
  22. *
  23. * Alternatively, this software may be distributed under the terms of the
  24. * GNU General Public License ("GPL") version 2 as published by the Free
  25. * Software Foundation.
  26. *
  27. * NO WARRANTY
  28. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  31. * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32. * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  33. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  34. * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  35. * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  36. * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  37. * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  38. * POSSIBILITY OF SUCH DAMAGES.
  39. *
  40. * $FreeBSD$
  41. */
  42. VERSION = "$Id: //depot/aic7xxx/aic7xxx/aic7xxx.seq#58 $"
  43. PATCH_ARG_LIST = "struct ahc_softc *ahc"
  44. PREFIX = "ahc_"
  45. #include "aic7xxx.reg"
  46. #include "scsi_message.h"
  47. /*
  48. * A few words on the waiting SCB list:
  49. * After starting the selection hardware, we check for reconnecting targets
  50. * as well as for our selection to complete just in case the reselection wins
  51. * bus arbitration. The problem with this is that we must keep track of the
  52. * SCB that we've already pulled from the QINFIFO and started the selection
  53. * on just in case the reselection wins so that we can retry the selection at
  54. * a later time. This problem cannot be resolved by holding a single entry
  55. * in scratch ram since a reconnecting target can request sense and this will
  56. * create yet another SCB waiting for selection. The solution used here is to
  57. * use byte 27 of the SCB as a pseudo-next pointer and to thread a list
  58. * of SCBs that are awaiting selection. Since 0-0xfe are valid SCB indexes,
  59. * SCB_LIST_NULL is 0xff which is out of range. An entry is also added to
  60. * this list every time a request sense occurs or after completing a non-tagged
  61. * command for which a second SCB has been queued. The sequencer will
  62. * automatically consume the entries.
  63. */
  64. bus_free_sel:
  65. /*
  66. * Turn off the selection hardware. We need to reset the
  67. * selection request in order to perform a new selection.
  68. */
  69. and SCSISEQ, TEMODE|ENSELI|ENRSELI|ENAUTOATNP;
  70. and SIMODE1, ~ENBUSFREE;
  71. poll_for_work:
  72. call clear_target_state;
  73. and SXFRCTL0, ~SPIOEN;
  74. if ((ahc->features & AHC_ULTRA2) != 0) {
  75. clr SCSIBUSL;
  76. }
  77. test SCSISEQ, ENSELO jnz poll_for_selection;
  78. if ((ahc->features & AHC_TWIN) != 0) {
  79. xor SBLKCTL,SELBUSB; /* Toggle to the other bus */
  80. test SCSISEQ, ENSELO jnz poll_for_selection;
  81. }
  82. cmp WAITING_SCBH,SCB_LIST_NULL jne start_waiting;
  83. poll_for_work_loop:
  84. if ((ahc->features & AHC_TWIN) != 0) {
  85. xor SBLKCTL,SELBUSB; /* Toggle to the other bus */
  86. }
  87. test SSTAT0, SELDO|SELDI jnz selection;
  88. test_queue:
  89. /* Has the driver posted any work for us? */
  90. BEGIN_CRITICAL;
  91. if ((ahc->features & AHC_QUEUE_REGS) != 0) {
  92. test QOFF_CTLSTA, SCB_AVAIL jz poll_for_work_loop;
  93. } else {
  94. mov A, QINPOS;
  95. cmp KERNEL_QINPOS, A je poll_for_work_loop;
  96. }
  97. mov ARG_1, NEXT_QUEUED_SCB;
  98. /*
  99. * We have at least one queued SCB now and we don't have any
  100. * SCBs in the list of SCBs awaiting selection. Allocate a
  101. * card SCB for the host's SCB and get to work on it.
  102. */
  103. if ((ahc->flags & AHC_PAGESCBS) != 0) {
  104. mov ALLZEROS call get_free_or_disc_scb;
  105. } else {
  106. /* In the non-paging case, the SCBID == hardware SCB index */
  107. mov SCBPTR, ARG_1;
  108. }
  109. or SEQ_FLAGS2, SCB_DMA;
  110. END_CRITICAL;
  111. dma_queued_scb:
  112. /*
  113. * DMA the SCB from host ram into the current SCB location.
  114. */
  115. mvi DMAPARAMS, HDMAEN|DIRECTION|FIFORESET;
  116. mov ARG_1 call dma_scb;
  117. /*
  118. * Check one last time to see if this SCB was canceled
  119. * before we completed the DMA operation. If it was,
  120. * the QINFIFO next pointer will not match our saved
  121. * value.
  122. */
  123. mov A, ARG_1;
  124. BEGIN_CRITICAL;
  125. cmp NEXT_QUEUED_SCB, A jne abort_qinscb;
  126. if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) {
  127. cmp SCB_TAG, A je . + 2;
  128. mvi SCB_MISMATCH call set_seqint;
  129. }
  130. mov NEXT_QUEUED_SCB, SCB_NEXT;
  131. mov SCB_NEXT,WAITING_SCBH;
  132. mov WAITING_SCBH, SCBPTR;
  133. if ((ahc->features & AHC_QUEUE_REGS) != 0) {
  134. mov NONE, SNSCB_QOFF;
  135. } else {
  136. inc QINPOS;
  137. }
  138. and SEQ_FLAGS2, ~SCB_DMA;
  139. END_CRITICAL;
  140. start_waiting:
  141. /*
  142. * Start the first entry on the waiting SCB list.
  143. */
  144. mov SCBPTR, WAITING_SCBH;
  145. call start_selection;
  146. poll_for_selection:
  147. /*
  148. * Twin channel devices cannot handle things like SELTO
  149. * interrupts on the "background" channel. So, while
  150. * selecting, keep polling the current channel until
  151. * either a selection or reselection occurs.
  152. */
  153. test SSTAT0, SELDO|SELDI jz poll_for_selection;
  154. selection:
  155. /*
  156. * We aren't expecting a bus free, so interrupt
  157. * the kernel driver if it happens.
  158. */
  159. mvi CLRSINT1,CLRBUSFREE;
  160. if ((ahc->features & AHC_DT) == 0) {
  161. or SIMODE1, ENBUSFREE;
  162. }
  163. /*
  164. * Guard against a bus free after (re)selection
  165. * but prior to enabling the busfree interrupt. SELDI
  166. * and SELDO will be cleared in that case.
  167. */
  168. test SSTAT0, SELDI|SELDO jz bus_free_sel;
  169. test SSTAT0,SELDO jnz select_out;
  170. select_in:
  171. if ((ahc->flags & AHC_TARGETROLE) != 0) {
  172. if ((ahc->flags & AHC_INITIATORROLE) != 0) {
  173. test SSTAT0, TARGET jz initiator_reselect;
  174. }
  175. mvi CLRSINT0, CLRSELDI;
  176. /*
  177. * We've just been selected. Assert BSY and
  178. * setup the phase for receiving messages
  179. * from the target.
  180. */
  181. mvi SCSISIGO, P_MESGOUT|BSYO;
  182. /*
  183. * Setup the DMA for sending the identify and
  184. * command information.
  185. */
  186. mvi SEQ_FLAGS, CMDPHASE_PENDING;
  187. mov A, TQINPOS;
  188. if ((ahc->features & AHC_CMD_CHAN) != 0) {
  189. mvi DINDEX, CCHADDR;
  190. mvi SHARED_DATA_ADDR call set_32byte_addr;
  191. mvi CCSCBCTL, CCSCBRESET;
  192. } else {
  193. mvi DINDEX, HADDR;
  194. mvi SHARED_DATA_ADDR call set_32byte_addr;
  195. mvi DFCNTRL, FIFORESET;
  196. }
  197. /* Initiator that selected us */
  198. and SAVED_SCSIID, SELID_MASK, SELID;
  199. /* The Target ID we were selected at */
  200. if ((ahc->features & AHC_MULTI_TID) != 0) {
  201. and A, OID, TARGIDIN;
  202. } else if ((ahc->features & AHC_ULTRA2) != 0) {
  203. and A, OID, SCSIID_ULTRA2;
  204. } else {
  205. and A, OID, SCSIID;
  206. }
  207. or SAVED_SCSIID, A;
  208. if ((ahc->features & AHC_TWIN) != 0) {
  209. test SBLKCTL, SELBUSB jz . + 2;
  210. or SAVED_SCSIID, TWIN_CHNLB;
  211. }
  212. if ((ahc->features & AHC_CMD_CHAN) != 0) {
  213. mov CCSCBRAM, SAVED_SCSIID;
  214. } else {
  215. mov DFDAT, SAVED_SCSIID;
  216. }
  217. /*
  218. * If ATN isn't asserted, the target isn't interested
  219. * in talking to us. Go directly to bus free.
  220. * XXX SCSI-1 may require us to assume lun 0 if
  221. * ATN is false.
  222. */
  223. test SCSISIGI, ATNI jz target_busfree;
  224. /*
  225. * Watch ATN closely now as we pull in messages from the
  226. * initiator. We follow the guidlines from section 6.5
  227. * of the SCSI-2 spec for what messages are allowed when.
  228. */
  229. call target_inb;
  230. /*
  231. * Our first message must be one of IDENTIFY, ABORT, or
  232. * BUS_DEVICE_RESET.
  233. */
  234. test DINDEX, MSG_IDENTIFYFLAG jz host_target_message_loop;
  235. /* Store for host */
  236. if ((ahc->features & AHC_CMD_CHAN) != 0) {
  237. mov CCSCBRAM, DINDEX;
  238. } else {
  239. mov DFDAT, DINDEX;
  240. }
  241. and SAVED_LUN, MSG_IDENTIFY_LUNMASK, DINDEX;
  242. /* Remember for disconnection decision */
  243. test DINDEX, MSG_IDENTIFY_DISCFLAG jnz . + 2;
  244. /* XXX Honor per target settings too */
  245. or SEQ_FLAGS, NO_DISCONNECT;
  246. test SCSISIGI, ATNI jz ident_messages_done;
  247. call target_inb;
  248. /*
  249. * If this is a tagged request, the tagged message must
  250. * immediately follow the identify. We test for a valid
  251. * tag message by seeing if it is >= MSG_SIMPLE_Q_TAG and
  252. * < MSG_IGN_WIDE_RESIDUE.
  253. */
  254. add A, -MSG_SIMPLE_Q_TAG, DINDEX;
  255. jnc ident_messages_done_msg_pending;
  256. add A, -MSG_IGN_WIDE_RESIDUE, DINDEX;
  257. jc ident_messages_done_msg_pending;
  258. /* Store for host */
  259. if ((ahc->features & AHC_CMD_CHAN) != 0) {
  260. mov CCSCBRAM, DINDEX;
  261. } else {
  262. mov DFDAT, DINDEX;
  263. }
  264. /*
  265. * If the initiator doesn't feel like providing a tag number,
  266. * we've got a failed selection and must transition to bus
  267. * free.
  268. */
  269. test SCSISIGI, ATNI jz target_busfree;
  270. /*
  271. * Store the tag for the host.
  272. */
  273. call target_inb;
  274. if ((ahc->features & AHC_CMD_CHAN) != 0) {
  275. mov CCSCBRAM, DINDEX;
  276. } else {
  277. mov DFDAT, DINDEX;
  278. }
  279. mov INITIATOR_TAG, DINDEX;
  280. or SEQ_FLAGS, TARGET_CMD_IS_TAGGED;
  281. ident_messages_done:
  282. /* Terminate the ident list */
  283. if ((ahc->features & AHC_CMD_CHAN) != 0) {
  284. mvi CCSCBRAM, SCB_LIST_NULL;
  285. } else {
  286. mvi DFDAT, SCB_LIST_NULL;
  287. }
  288. or SEQ_FLAGS, TARG_CMD_PENDING;
  289. test SEQ_FLAGS2, TARGET_MSG_PENDING
  290. jnz target_mesgout_pending;
  291. test SCSISIGI, ATNI jnz target_mesgout_continue;
  292. jmp target_ITloop;
  293. ident_messages_done_msg_pending:
  294. or SEQ_FLAGS2, TARGET_MSG_PENDING;
  295. jmp ident_messages_done;
  296. /*
  297. * Pushed message loop to allow the kernel to
  298. * run it's own target mode message state engine.
  299. */
  300. host_target_message_loop:
  301. mvi HOST_MSG_LOOP call set_seqint;
  302. cmp RETURN_1, EXIT_MSG_LOOP je target_ITloop;
  303. test SSTAT0, SPIORDY jz .;
  304. jmp host_target_message_loop;
  305. }
  306. if ((ahc->flags & AHC_INITIATORROLE) != 0) {
  307. /*
  308. * Reselection has been initiated by a target. Make a note that we've been
  309. * reselected, but haven't seen an IDENTIFY message from the target yet.
  310. */
  311. initiator_reselect:
  312. /* XXX test for and handle ONE BIT condition */
  313. or SXFRCTL0, SPIOEN|CLRSTCNT|CLRCHN;
  314. and SAVED_SCSIID, SELID_MASK, SELID;
  315. if ((ahc->features & AHC_ULTRA2) != 0) {
  316. and A, OID, SCSIID_ULTRA2;
  317. } else {
  318. and A, OID, SCSIID;
  319. }
  320. or SAVED_SCSIID, A;
  321. if ((ahc->features & AHC_TWIN) != 0) {
  322. test SBLKCTL, SELBUSB jz . + 2;
  323. or SAVED_SCSIID, TWIN_CHNLB;
  324. }
  325. mvi CLRSINT0, CLRSELDI;
  326. jmp ITloop;
  327. }
  328. abort_qinscb:
  329. call add_scb_to_free_list;
  330. jmp poll_for_work_loop;
  331. start_selection:
  332. /*
  333. * If bus reset interrupts have been disabled (from a previous
  334. * reset), re-enable them now. Resets are only of interest
  335. * when we have outstanding transactions, so we can safely
  336. * defer re-enabling the interrupt until, as an initiator,
  337. * we start sending out transactions again.
  338. */
  339. test SIMODE1, ENSCSIRST jnz . + 3;
  340. mvi CLRSINT1, CLRSCSIRSTI;
  341. or SIMODE1, ENSCSIRST;
  342. if ((ahc->features & AHC_TWIN) != 0) {
  343. and SINDEX,~SELBUSB,SBLKCTL;/* Clear channel select bit */
  344. test SCB_SCSIID, TWIN_CHNLB jz . + 2;
  345. or SINDEX, SELBUSB;
  346. mov SBLKCTL,SINDEX; /* select channel */
  347. }
  348. initialize_scsiid:
  349. if ((ahc->features & AHC_ULTRA2) != 0) {
  350. mov SCSIID_ULTRA2, SCB_SCSIID;
  351. } else if ((ahc->features & AHC_TWIN) != 0) {
  352. and SCSIID, TWIN_TID|OID, SCB_SCSIID;
  353. } else {
  354. mov SCSIID, SCB_SCSIID;
  355. }
  356. if ((ahc->flags & AHC_TARGETROLE) != 0) {
  357. mov SINDEX, SCSISEQ_TEMPLATE;
  358. test SCB_CONTROL, TARGET_SCB jz . + 2;
  359. or SINDEX, TEMODE;
  360. mov SCSISEQ, SINDEX ret;
  361. } else {
  362. mov SCSISEQ, SCSISEQ_TEMPLATE ret;
  363. }
  364. /*
  365. * Initialize transfer settings with SCB provided settings.
  366. */
  367. set_transfer_settings:
  368. if ((ahc->features & AHC_ULTRA) != 0) {
  369. test SCB_CONTROL, ULTRAENB jz . + 2;
  370. or SXFRCTL0, FAST20;
  371. }
  372. /*
  373. * Initialize SCSIRATE with the appropriate value for this target.
  374. */
  375. if ((ahc->features & AHC_ULTRA2) != 0) {
  376. bmov SCSIRATE, SCB_SCSIRATE, 2 ret;
  377. } else {
  378. mov SCSIRATE, SCB_SCSIRATE ret;
  379. }
  380. if ((ahc->flags & AHC_TARGETROLE) != 0) {
  381. /*
  382. * We carefully toggle SPIOEN to allow us to return the
  383. * message byte we receive so it can be checked prior to
  384. * driving REQ on the bus for the next byte.
  385. */
  386. target_inb:
  387. /*
  388. * Drive REQ on the bus by enabling SCSI PIO.
  389. */
  390. or SXFRCTL0, SPIOEN;
  391. /* Wait for the byte */
  392. test SSTAT0, SPIORDY jz .;
  393. /* Prevent our read from triggering another REQ */
  394. and SXFRCTL0, ~SPIOEN;
  395. /* Save latched contents */
  396. mov DINDEX, SCSIDATL ret;
  397. }
  398. /*
  399. * After the selection, remove this SCB from the "waiting SCB"
  400. * list. This is achieved by simply moving our "next" pointer into
  401. * WAITING_SCBH. Our next pointer will be set to null the next time this
  402. * SCB is used, so don't bother with it now.
  403. */
  404. select_out:
  405. /* Turn off the selection hardware */
  406. and SCSISEQ, TEMODE|ENSELI|ENRSELI|ENAUTOATNP, SCSISEQ;
  407. mov SCBPTR, WAITING_SCBH;
  408. mov WAITING_SCBH,SCB_NEXT;
  409. mov SAVED_SCSIID, SCB_SCSIID;
  410. and SAVED_LUN, LID, SCB_LUN;
  411. call set_transfer_settings;
  412. if ((ahc->flags & AHC_TARGETROLE) != 0) {
  413. test SSTAT0, TARGET jz initiator_select;
  414. or SXFRCTL0, CLRSTCNT|CLRCHN;
  415. /*
  416. * Put tag in connonical location since not
  417. * all connections have an SCB.
  418. */
  419. mov INITIATOR_TAG, SCB_TARGET_ITAG;
  420. /*
  421. * We've just re-selected an initiator.
  422. * Assert BSY and setup the phase for
  423. * sending our identify messages.
  424. */
  425. mvi P_MESGIN|BSYO call change_phase;
  426. mvi CLRSINT0, CLRSELDO;
  427. /*
  428. * Start out with a simple identify message.
  429. */
  430. or SAVED_LUN, MSG_IDENTIFYFLAG call target_outb;
  431. /*
  432. * If we are the result of a tagged command, send
  433. * a simple Q tag and the tag id.
  434. */
  435. test SCB_CONTROL, TAG_ENB jz . + 3;
  436. mvi MSG_SIMPLE_Q_TAG call target_outb;
  437. mov SCB_TARGET_ITAG call target_outb;
  438. target_synccmd:
  439. /*
  440. * Now determine what phases the host wants us
  441. * to go through.
  442. */
  443. mov SEQ_FLAGS, SCB_TARGET_PHASES;
  444. test SCB_CONTROL, MK_MESSAGE jz target_ITloop;
  445. mvi P_MESGIN|BSYO call change_phase;
  446. jmp host_target_message_loop;
  447. target_ITloop:
  448. /*
  449. * Start honoring ATN signals now that
  450. * we properly identified ourselves.
  451. */
  452. test SCSISIGI, ATNI jnz target_mesgout;
  453. test SEQ_FLAGS, CMDPHASE_PENDING jnz target_cmdphase;
  454. test SEQ_FLAGS, DPHASE_PENDING jnz target_dphase;
  455. test SEQ_FLAGS, SPHASE_PENDING jnz target_sphase;
  456. /*
  457. * No more work to do. Either disconnect or not depending
  458. * on the state of NO_DISCONNECT.
  459. */
  460. test SEQ_FLAGS, NO_DISCONNECT jz target_disconnect;
  461. mvi TARG_IMMEDIATE_SCB, SCB_LIST_NULL;
  462. call complete_target_cmd;
  463. if ((ahc->flags & AHC_PAGESCBS) != 0) {
  464. mov ALLZEROS call get_free_or_disc_scb;
  465. }
  466. cmp TARG_IMMEDIATE_SCB, SCB_LIST_NULL je .;
  467. mvi DMAPARAMS, HDMAEN|DIRECTION|FIFORESET;
  468. mov TARG_IMMEDIATE_SCB call dma_scb;
  469. call set_transfer_settings;
  470. or SXFRCTL0, CLRSTCNT|CLRCHN;
  471. jmp target_synccmd;
  472. target_mesgout:
  473. mvi SCSISIGO, P_MESGOUT|BSYO;
  474. target_mesgout_continue:
  475. call target_inb;
  476. target_mesgout_pending:
  477. and SEQ_FLAGS2, ~TARGET_MSG_PENDING;
  478. /* Local Processing goes here... */
  479. jmp host_target_message_loop;
  480. target_disconnect:
  481. mvi P_MESGIN|BSYO call change_phase;
  482. test SEQ_FLAGS, DPHASE jz . + 2;
  483. mvi MSG_SAVEDATAPOINTER call target_outb;
  484. mvi MSG_DISCONNECT call target_outb;
  485. target_busfree_wait:
  486. /* Wait for preceding I/O session to complete. */
  487. test SCSISIGI, ACKI jnz .;
  488. target_busfree:
  489. and SIMODE1, ~ENBUSFREE;
  490. if ((ahc->features & AHC_ULTRA2) != 0) {
  491. clr SCSIBUSL;
  492. }
  493. clr SCSISIGO;
  494. mvi LASTPHASE, P_BUSFREE;
  495. call complete_target_cmd;
  496. jmp poll_for_work;
  497. target_cmdphase:
  498. /*
  499. * The target has dropped ATN (doesn't want to abort or BDR)
  500. * and we believe this selection to be valid. If the ring
  501. * buffer for new commands is full, return busy or queue full.
  502. */
  503. if ((ahc->features & AHC_HS_MAILBOX) != 0) {
  504. and A, HOST_TQINPOS, HS_MAILBOX;
  505. } else {
  506. mov A, KERNEL_TQINPOS;
  507. }
  508. cmp TQINPOS, A jne tqinfifo_has_space;
  509. mvi P_STATUS|BSYO call change_phase;
  510. test SEQ_FLAGS, TARGET_CMD_IS_TAGGED jz . + 3;
  511. mvi STATUS_QUEUE_FULL call target_outb;
  512. jmp target_busfree_wait;
  513. mvi STATUS_BUSY call target_outb;
  514. jmp target_busfree_wait;
  515. tqinfifo_has_space:
  516. mvi P_COMMAND|BSYO call change_phase;
  517. call target_inb;
  518. mov A, DINDEX;
  519. /* Store for host */
  520. if ((ahc->features & AHC_CMD_CHAN) != 0) {
  521. mov CCSCBRAM, A;
  522. } else {
  523. mov DFDAT, A;
  524. }
  525. /*
  526. * Determine the number of bytes to read
  527. * based on the command group code via table lookup.
  528. * We reuse the first 8 bytes of the TARG_SCSIRATE
  529. * BIOS array for this table. Count is one less than
  530. * the total for the command since we've already fetched
  531. * the first byte.
  532. */
  533. shr A, CMD_GROUP_CODE_SHIFT;
  534. add SINDEX, CMDSIZE_TABLE, A;
  535. mov A, SINDIR;
  536. test A, 0xFF jz command_phase_done;
  537. or SXFRCTL0, SPIOEN;
  538. command_loop:
  539. test SSTAT0, SPIORDY jz .;
  540. cmp A, 1 jne . + 2;
  541. and SXFRCTL0, ~SPIOEN; /* Last Byte */
  542. if ((ahc->features & AHC_CMD_CHAN) != 0) {
  543. mov CCSCBRAM, SCSIDATL;
  544. } else {
  545. mov DFDAT, SCSIDATL;
  546. }
  547. dec A;
  548. test A, 0xFF jnz command_loop;
  549. command_phase_done:
  550. and SEQ_FLAGS, ~CMDPHASE_PENDING;
  551. jmp target_ITloop;
  552. target_dphase:
  553. /*
  554. * Data phases on the bus are from the
  555. * perspective of the initiator. The dma
  556. * code looks at LASTPHASE to determine the
  557. * data direction of the DMA. Toggle it for
  558. * target transfers.
  559. */
  560. xor LASTPHASE, IOI, SCB_TARGET_DATA_DIR;
  561. or SCB_TARGET_DATA_DIR, BSYO call change_phase;
  562. jmp p_data;
  563. target_sphase:
  564. mvi P_STATUS|BSYO call change_phase;
  565. mvi LASTPHASE, P_STATUS;
  566. mov SCB_SCSI_STATUS call target_outb;
  567. /* XXX Watch for ATN or parity errors??? */
  568. mvi SCSISIGO, P_MESGIN|BSYO;
  569. /* MSG_CMDCMPLT is 0, but we can't do an immediate of 0 */
  570. mov ALLZEROS call target_outb;
  571. jmp target_busfree_wait;
  572. complete_target_cmd:
  573. test SEQ_FLAGS, TARG_CMD_PENDING jnz . + 2;
  574. mov SCB_TAG jmp complete_post;
  575. if ((ahc->features & AHC_CMD_CHAN) != 0) {
  576. /* Set the valid byte */
  577. mvi CCSCBADDR, 24;
  578. mov CCSCBRAM, ALLONES;
  579. mvi CCHCNT, 28;
  580. or CCSCBCTL, CCSCBEN|CCSCBRESET;
  581. test CCSCBCTL, CCSCBDONE jz .;
  582. clr CCSCBCTL;
  583. } else {
  584. /* Set the valid byte */
  585. or DFCNTRL, FIFORESET;
  586. mvi DFWADDR, 3; /* Third 64bit word or byte 24 */
  587. mov DFDAT, ALLONES;
  588. mvi 28 call set_hcnt;
  589. or DFCNTRL, HDMAEN|FIFOFLUSH;
  590. call dma_finish;
  591. }
  592. inc TQINPOS;
  593. mvi INTSTAT,CMDCMPLT ret;
  594. }
  595. if ((ahc->flags & AHC_INITIATORROLE) != 0) {
  596. initiator_select:
  597. or SXFRCTL0, SPIOEN|CLRSTCNT|CLRCHN;
  598. /*
  599. * As soon as we get a successful selection, the target
  600. * should go into the message out phase since we have ATN
  601. * asserted.
  602. */
  603. mvi MSG_OUT, MSG_IDENTIFYFLAG;
  604. mvi SEQ_FLAGS, NO_CDB_SENT;
  605. mvi CLRSINT0, CLRSELDO;
  606. /*
  607. * Main loop for information transfer phases. Wait for the
  608. * target to assert REQ before checking MSG, C/D and I/O for
  609. * the bus phase.
  610. */
  611. mesgin_phasemis:
  612. ITloop:
  613. call phase_lock;
  614. mov A, LASTPHASE;
  615. test A, ~P_DATAIN jz p_data;
  616. cmp A,P_COMMAND je p_command;
  617. cmp A,P_MESGOUT je p_mesgout;
  618. cmp A,P_STATUS je p_status;
  619. cmp A,P_MESGIN je p_mesgin;
  620. mvi BAD_PHASE call set_seqint;
  621. jmp ITloop; /* Try reading the bus again. */
  622. await_busfree:
  623. and SIMODE1, ~ENBUSFREE;
  624. mov NONE, SCSIDATL; /* Ack the last byte */
  625. if ((ahc->features & AHC_ULTRA2) != 0) {
  626. clr SCSIBUSL; /* Prevent bit leakage durint SELTO */
  627. }
  628. and SXFRCTL0, ~SPIOEN;
  629. mvi SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT;
  630. test SSTAT1,REQINIT|BUSFREE jz .;
  631. test SSTAT1, BUSFREE jnz poll_for_work;
  632. mvi MISSED_BUSFREE call set_seqint;
  633. }
  634. clear_target_state:
  635. /*
  636. * We assume that the kernel driver may reset us
  637. * at any time, even in the middle of a DMA, so
  638. * clear DFCNTRL too.
  639. */
  640. clr DFCNTRL;
  641. or SXFRCTL0, CLRSTCNT|CLRCHN;
  642. /*
  643. * We don't know the target we will connect to,
  644. * so default to narrow transfers to avoid
  645. * parity problems.
  646. */
  647. if ((ahc->features & AHC_ULTRA2) != 0) {
  648. bmov SCSIRATE, ALLZEROS, 2;
  649. } else {
  650. clr SCSIRATE;
  651. if ((ahc->features & AHC_ULTRA) != 0) {
  652. and SXFRCTL0, ~(FAST20);
  653. }
  654. }
  655. mvi LASTPHASE, P_BUSFREE;
  656. /* clear target specific flags */
  657. mvi SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT ret;
  658. sg_advance:
  659. clr A; /* add sizeof(struct scatter) */
  660. add SCB_RESIDUAL_SGPTR[0],SG_SIZEOF;
  661. adc SCB_RESIDUAL_SGPTR[1],A;
  662. adc SCB_RESIDUAL_SGPTR[2],A;
  663. adc SCB_RESIDUAL_SGPTR[3],A ret;
  664. if ((ahc->features & AHC_CMD_CHAN) != 0) {
  665. disable_ccsgen:
  666. test CCSGCTL, CCSGEN jz return;
  667. test CCSGCTL, CCSGDONE jz .;
  668. disable_ccsgen_fetch_done:
  669. clr CCSGCTL;
  670. test CCSGCTL, CCSGEN jnz .;
  671. ret;
  672. idle_loop:
  673. /*
  674. * Do we need any more segments for this transfer?
  675. */
  676. test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jnz return;
  677. /* Did we just finish fetching segs? */
  678. cmp CCSGCTL, CCSGEN|CCSGDONE je idle_sgfetch_complete;
  679. /* Are we actively fetching segments? */
  680. test CCSGCTL, CCSGEN jnz return;
  681. /*
  682. * Do we have any prefetch left???
  683. */
  684. cmp CCSGADDR, SG_PREFETCH_CNT jne idle_sg_avail;
  685. /*
  686. * Need to fetch segments, but we can only do that
  687. * if the command channel is completely idle. Make
  688. * sure we don't have an SCB prefetch going on.
  689. */
  690. test CCSCBCTL, CCSCBEN jnz return;
  691. /*
  692. * We fetch a "cacheline aligned" and sized amount of data
  693. * so we don't end up referencing a non-existent page.
  694. * Cacheline aligned is in quotes because the kernel will
  695. * set the prefetch amount to a reasonable level if the
  696. * cacheline size is unknown.
  697. */
  698. mvi CCHCNT, SG_PREFETCH_CNT;
  699. and CCHADDR[0], SG_PREFETCH_ALIGN_MASK, SCB_RESIDUAL_SGPTR;
  700. bmov CCHADDR[1], SCB_RESIDUAL_SGPTR[1], 3;
  701. mvi CCSGCTL, CCSGEN|CCSGRESET ret;
  702. idle_sgfetch_complete:
  703. call disable_ccsgen_fetch_done;
  704. and CCSGADDR, SG_PREFETCH_ADDR_MASK, SCB_RESIDUAL_SGPTR;
  705. idle_sg_avail:
  706. if ((ahc->features & AHC_ULTRA2) != 0) {
  707. /* Does the hardware have space for another SG entry? */
  708. test DFSTATUS, PRELOAD_AVAIL jz return;
  709. bmov HADDR, CCSGRAM, 7;
  710. bmov SCB_RESIDUAL_DATACNT[3], CCSGRAM, 1;
  711. if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
  712. mov SCB_RESIDUAL_DATACNT[3] call set_hhaddr;
  713. }
  714. call sg_advance;
  715. mov SINDEX, SCB_RESIDUAL_SGPTR[0];
  716. test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jz . + 2;
  717. or SINDEX, LAST_SEG;
  718. mov SG_CACHE_PRE, SINDEX;
  719. /* Load the segment */
  720. or DFCNTRL, PRELOADEN;
  721. }
  722. ret;
  723. }
  724. if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0 && ahc->pci_cachesize != 0) {
  725. /*
  726. * Calculate the trailing portion of this S/G segment that cannot
  727. * be transferred using memory write and invalidate PCI transactions.
  728. * XXX Can we optimize this for PCI writes only???
  729. */
  730. calc_mwi_residual:
  731. /*
  732. * If the ending address is on a cacheline boundary,
  733. * there is no need for an extra segment.
  734. */
  735. mov A, HCNT[0];
  736. add A, A, HADDR[0];
  737. and A, CACHESIZE_MASK;
  738. test A, 0xFF jz return;
  739. /*
  740. * If the transfer is less than a cachline,
  741. * there is no need for an extra segment.
  742. */
  743. test HCNT[1], 0xFF jnz calc_mwi_residual_final;
  744. test HCNT[2], 0xFF jnz calc_mwi_residual_final;
  745. add NONE, INVERTED_CACHESIZE_MASK, HCNT[0];
  746. jnc return;
  747. calc_mwi_residual_final:
  748. mov MWI_RESIDUAL, A;
  749. not A;
  750. inc A;
  751. add HCNT[0], A;
  752. adc HCNT[1], -1;
  753. adc HCNT[2], -1 ret;
  754. }
  755. p_data:
  756. test SEQ_FLAGS,NOT_IDENTIFIED|NO_CDB_SENT jz p_data_allowed;
  757. mvi PROTO_VIOLATION call set_seqint;
  758. p_data_allowed:
  759. if ((ahc->features & AHC_ULTRA2) != 0) {
  760. mvi DMAPARAMS, PRELOADEN|SCSIEN|HDMAEN;
  761. } else {
  762. mvi DMAPARAMS, WIDEODD|SCSIEN|SDMAEN|HDMAEN|FIFORESET;
  763. }
  764. test LASTPHASE, IOI jnz . + 2;
  765. or DMAPARAMS, DIRECTION;
  766. if ((ahc->features & AHC_CMD_CHAN) != 0) {
  767. /* We don't have any valid S/G elements */
  768. mvi CCSGADDR, SG_PREFETCH_CNT;
  769. }
  770. test SEQ_FLAGS, DPHASE jz data_phase_initialize;
  771. /*
  772. * If we re-enter the data phase after going through another
  773. * phase, our transfer location has almost certainly been
  774. * corrupted by the interveining, non-data, transfers. Ask
  775. * the host driver to fix us up based on the transfer residual.
  776. */
  777. mvi PDATA_REINIT call set_seqint;
  778. jmp data_phase_loop;
  779. data_phase_initialize:
  780. /* We have seen a data phase for the first time */
  781. or SEQ_FLAGS, DPHASE;
  782. /*
  783. * Initialize the DMA address and counter from the SCB.
  784. * Also set SCB_RESIDUAL_SGPTR, including the LAST_SEG
  785. * flag in the highest byte of the data count. We cannot
  786. * modify the saved values in the SCB until we see a save
  787. * data pointers message.
  788. */
  789. if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
  790. /* The lowest address byte must be loaded last. */
  791. mov SCB_DATACNT[3] call set_hhaddr;
  792. }
  793. if ((ahc->features & AHC_CMD_CHAN) != 0) {
  794. bmov HADDR, SCB_DATAPTR, 7;
  795. bmov SCB_RESIDUAL_DATACNT[3], SCB_DATACNT[3], 5;
  796. } else {
  797. mvi DINDEX, HADDR;
  798. mvi SCB_DATAPTR call bcopy_7;
  799. mvi DINDEX, SCB_RESIDUAL_DATACNT + 3;
  800. mvi SCB_DATACNT + 3 call bcopy_5;
  801. }
  802. if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0 && ahc->pci_cachesize != 0) {
  803. call calc_mwi_residual;
  804. }
  805. and SCB_RESIDUAL_SGPTR[0], ~SG_FULL_RESID;
  806. if ((ahc->features & AHC_ULTRA2) == 0) {
  807. if ((ahc->features & AHC_CMD_CHAN) != 0) {
  808. bmov STCNT, HCNT, 3;
  809. } else {
  810. call set_stcnt_from_hcnt;
  811. }
  812. }
  813. data_phase_loop:
  814. /* Guard against overruns */
  815. test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jz data_phase_inbounds;
  816. /*
  817. * Turn on `Bit Bucket' mode, wait until the target takes
  818. * us to another phase, and then notify the host.
  819. */
  820. and DMAPARAMS, DIRECTION;
  821. mov DFCNTRL, DMAPARAMS;
  822. or SXFRCTL1,BITBUCKET;
  823. if ((ahc->features & AHC_DT) == 0) {
  824. test SSTAT1,PHASEMIS jz .;
  825. } else {
  826. test SCSIPHASE, DATA_PHASE_MASK jnz .;
  827. }
  828. and SXFRCTL1, ~BITBUCKET;
  829. mvi DATA_OVERRUN call set_seqint;
  830. jmp ITloop;
  831. data_phase_inbounds:
  832. if ((ahc->features & AHC_ULTRA2) != 0) {
  833. mov SINDEX, SCB_RESIDUAL_SGPTR[0];
  834. test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jz . + 2;
  835. or SINDEX, LAST_SEG;
  836. mov SG_CACHE_PRE, SINDEX;
  837. mov DFCNTRL, DMAPARAMS;
  838. ultra2_dma_loop:
  839. call idle_loop;
  840. /*
  841. * The transfer is complete if either the last segment
  842. * completes or the target changes phase.
  843. */
  844. test SG_CACHE_SHADOW, LAST_SEG_DONE jnz ultra2_dmafinish;
  845. if ((ahc->features & AHC_DT) == 0) {
  846. if ((ahc->flags & AHC_TARGETROLE) != 0) {
  847. /*
  848. * As a target, we control the phases,
  849. * so ignore PHASEMIS.
  850. */
  851. test SSTAT0, TARGET jnz ultra2_dma_loop;
  852. }
  853. if ((ahc->flags & AHC_INITIATORROLE) != 0) {
  854. test SSTAT1,PHASEMIS jz ultra2_dma_loop;
  855. }
  856. } else {
  857. test DFCNTRL, SCSIEN jnz ultra2_dma_loop;
  858. }
  859. ultra2_dmafinish:
  860. /*
  861. * The transfer has terminated either due to a phase
  862. * change, and/or the completion of the last segment.
  863. * We have two goals here. Do as much other work
  864. * as possible while the data fifo drains on a read
  865. * and respond as quickly as possible to the standard
  866. * messages (save data pointers/disconnect and command
  867. * complete) that usually follow a data phase.
  868. */
  869. if ((ahc->bugs & AHC_AUTOFLUSH_BUG) != 0) {
  870. /*
  871. * On chips with broken auto-flush, start
  872. * the flushing process now. We'll poke
  873. * the chip from time to time to keep the
  874. * flush process going as we complete the
  875. * data phase.
  876. */
  877. or DFCNTRL, FIFOFLUSH;
  878. }
  879. /*
  880. * We assume that, even though data may still be
  881. * transferring to the host, that the SCSI side of
  882. * the DMA engine is now in a static state. This
  883. * allows us to update our notion of where we are
  884. * in this transfer.
  885. *
  886. * If, by chance, we stopped before being able
  887. * to fetch additional segments for this transfer,
  888. * yet the last S/G was completely exhausted,
  889. * call our idle loop until it is able to load
  890. * another segment. This will allow us to immediately
  891. * pickup on the next segment on the next data phase.
  892. *
  893. * If we happened to stop on the last segment, then
  894. * our residual information is still correct from
  895. * the idle loop and there is no need to perform
  896. * any fixups.
  897. */
  898. ultra2_ensure_sg:
  899. test SG_CACHE_SHADOW, LAST_SEG jz ultra2_shvalid;
  900. /* Record if we've consumed all S/G entries */
  901. test SSTAT2, SHVALID jnz residuals_correct;
  902. or SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL;
  903. jmp residuals_correct;
  904. ultra2_shvalid:
  905. test SSTAT2, SHVALID jnz sgptr_fixup;
  906. call idle_loop;
  907. jmp ultra2_ensure_sg;
  908. sgptr_fixup:
  909. /*
  910. * Fixup the residual next S/G pointer. The S/G preload
  911. * feature of the chip allows us to load two elements
  912. * in addition to the currently active element. We
  913. * store the bottom byte of the next S/G pointer in
  914. * the SG_CACEPTR register so we can restore the
  915. * correct value when the DMA completes. If the next
  916. * sg ptr value has advanced to the point where higher
  917. * bytes in the address have been affected, fix them
  918. * too.
  919. */
  920. test SG_CACHE_SHADOW, 0x80 jz sgptr_fixup_done;
  921. test SCB_RESIDUAL_SGPTR[0], 0x80 jnz sgptr_fixup_done;
  922. add SCB_RESIDUAL_SGPTR[1], -1;
  923. adc SCB_RESIDUAL_SGPTR[2], -1;
  924. adc SCB_RESIDUAL_SGPTR[3], -1;
  925. sgptr_fixup_done:
  926. and SCB_RESIDUAL_SGPTR[0], SG_ADDR_MASK, SG_CACHE_SHADOW;
  927. /* We are not the last seg */
  928. and SCB_RESIDUAL_DATACNT[3], ~SG_LAST_SEG;
  929. residuals_correct:
  930. /*
  931. * Go ahead and shut down the DMA engine now.
  932. * In the future, we'll want to handle end of
  933. * transfer messages prior to doing this, but this
  934. * requires similar restructuring for pre-ULTRA2
  935. * controllers.
  936. */
  937. test DMAPARAMS, DIRECTION jnz ultra2_fifoempty;
  938. ultra2_fifoflush:
  939. if ((ahc->features & AHC_DT) == 0) {
  940. if ((ahc->bugs & AHC_AUTOFLUSH_BUG) != 0) {
  941. /*
  942. * On Rev A of the aic7890, the autoflush
  943. * feature doesn't function correctly.
  944. * Perform an explicit manual flush. During
  945. * a manual flush, the FIFOEMP bit becomes
  946. * true every time the PCI FIFO empties
  947. * regardless of the state of the SCSI FIFO.
  948. * It can take up to 4 clock cycles for the
  949. * SCSI FIFO to get data into the PCI FIFO
  950. * and for FIFOEMP to de-assert. Here we
  951. * guard against this condition by making
  952. * sure the FIFOEMP bit stays on for 5 full
  953. * clock cycles.
  954. */
  955. or DFCNTRL, FIFOFLUSH;
  956. test DFSTATUS, FIFOEMP jz ultra2_fifoflush;
  957. test DFSTATUS, FIFOEMP jz ultra2_fifoflush;
  958. test DFSTATUS, FIFOEMP jz ultra2_fifoflush;
  959. test DFSTATUS, FIFOEMP jz ultra2_fifoflush;
  960. }
  961. test DFSTATUS, FIFOEMP jz ultra2_fifoflush;
  962. } else {
  963. /*
  964. * We enable the auto-ack feature on DT capable
  965. * controllers. This means that the controller may
  966. * have already transferred some overrun bytes into
  967. * the data FIFO and acked them on the bus. The only
  968. * way to detect this situation is to wait for
  969. * LAST_SEG_DONE to come true on a completed transfer
  970. * and then test to see if the data FIFO is non-empty.
  971. */
  972. test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL
  973. jz ultra2_wait_fifoemp;
  974. test SG_CACHE_SHADOW, LAST_SEG_DONE jz .;
  975. /*
  976. * FIFOEMP can lag LAST_SEG_DONE. Wait a few
  977. * clocks before calling this an overrun.
  978. */
  979. test DFSTATUS, FIFOEMP jnz ultra2_fifoempty;
  980. test DFSTATUS, FIFOEMP jnz ultra2_fifoempty;
  981. test DFSTATUS, FIFOEMP jnz ultra2_fifoempty;
  982. /* Overrun */
  983. jmp data_phase_loop;
  984. ultra2_wait_fifoemp:
  985. test DFSTATUS, FIFOEMP jz .;
  986. }
  987. ultra2_fifoempty:
  988. /* Don't clobber an inprogress host data transfer */
  989. test DFSTATUS, MREQPEND jnz ultra2_fifoempty;
  990. ultra2_dmahalt:
  991. and DFCNTRL, ~(SCSIEN|HDMAEN);
  992. test DFCNTRL, SCSIEN|HDMAEN jnz .;
  993. if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
  994. /*
  995. * Keep HHADDR cleared for future, 32bit addressed
  996. * only, DMA operations.
  997. *
  998. * Due to bayonette style S/G handling, our residual
  999. * data must be "fixed up" once the transfer is halted.
  1000. * Here we fixup the HSHADDR stored in the high byte
  1001. * of the residual data cnt. By postponing the fixup,
  1002. * we can batch the clearing of HADDR with the fixup.
  1003. * If we halted on the last segment, the residual is
  1004. * already correct. If we are not on the last
  1005. * segment, copy the high address directly from HSHADDR.
  1006. * We don't need to worry about maintaining the
  1007. * SG_LAST_SEG flag as it will always be false in the
  1008. * case where an update is required.
  1009. */
  1010. or DSCOMMAND1, HADDLDSEL0;
  1011. test SG_CACHE_SHADOW, LAST_SEG jnz . + 2;
  1012. mov SCB_RESIDUAL_DATACNT[3], SHADDR;
  1013. clr HADDR;
  1014. and DSCOMMAND1, ~HADDLDSEL0;
  1015. }
  1016. } else {
  1017. /* If we are the last SG block, tell the hardware. */
  1018. if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0
  1019. && ahc->pci_cachesize != 0) {
  1020. test MWI_RESIDUAL, 0xFF jnz dma_mid_sg;
  1021. }
  1022. test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jz dma_mid_sg;
  1023. if ((ahc->flags & AHC_TARGETROLE) != 0) {
  1024. test SSTAT0, TARGET jz dma_last_sg;
  1025. if ((ahc->bugs & AHC_TMODE_WIDEODD_BUG) != 0) {
  1026. test DMAPARAMS, DIRECTION jz dma_mid_sg;
  1027. }
  1028. }
  1029. dma_last_sg:
  1030. and DMAPARAMS, ~WIDEODD;
  1031. dma_mid_sg:
  1032. /* Start DMA data transfer. */
  1033. mov DFCNTRL, DMAPARAMS;
  1034. dma_loop:
  1035. if ((ahc->features & AHC_CMD_CHAN) != 0) {
  1036. call idle_loop;
  1037. }
  1038. test SSTAT0,DMADONE jnz dma_dmadone;
  1039. test SSTAT1,PHASEMIS jz dma_loop; /* ie. underrun */
  1040. dma_phasemis:
  1041. /*
  1042. * We will be "done" DMAing when the transfer count goes to
  1043. * zero, or the target changes the phase (in light of this,
  1044. * it makes sense that the DMA circuitry doesn't ACK when
  1045. * PHASEMIS is active). If we are doing a SCSI->Host transfer,
  1046. * the data FIFO should be flushed auto-magically on STCNT=0
  1047. * or a phase change, so just wait for FIFO empty status.
  1048. */
  1049. dma_checkfifo:
  1050. test DFCNTRL,DIRECTION jnz dma_fifoempty;
  1051. dma_fifoflush:
  1052. test DFSTATUS,FIFOEMP jz dma_fifoflush;
  1053. dma_fifoempty:
  1054. /* Don't clobber an inprogress host data transfer */
  1055. test DFSTATUS, MREQPEND jnz dma_fifoempty;
  1056. /*
  1057. * Now shut off the DMA and make sure that the DMA
  1058. * hardware has actually stopped. Touching the DMA
  1059. * counters, etc. while a DMA is active will result
  1060. * in an ILLSADDR exception.
  1061. */
  1062. dma_dmadone:
  1063. and DFCNTRL, ~(SCSIEN|SDMAEN|HDMAEN);
  1064. dma_halt:
  1065. /*
  1066. * Some revisions of the aic78XX have a problem where, if the
  1067. * data fifo is full, but the PCI input latch is not empty,
  1068. * HDMAEN cannot be cleared. The fix used here is to drain
  1069. * the prefetched but unused data from the data fifo until
  1070. * there is space for the input latch to drain.
  1071. */
  1072. if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0) {
  1073. mov NONE, DFDAT;
  1074. }
  1075. test DFCNTRL, (SCSIEN|SDMAEN|HDMAEN) jnz dma_halt;
  1076. /* See if we have completed this last segment */
  1077. test STCNT[0], 0xff jnz data_phase_finish;
  1078. test STCNT[1], 0xff jnz data_phase_finish;
  1079. test STCNT[2], 0xff jnz data_phase_finish;
  1080. /*
  1081. * Advance the scatter-gather pointers if needed
  1082. */
  1083. if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0
  1084. && ahc->pci_cachesize != 0) {
  1085. test MWI_RESIDUAL, 0xFF jz no_mwi_resid;
  1086. /*
  1087. * Reload HADDR from SHADDR and setup the
  1088. * count to be the size of our residual.
  1089. */
  1090. if ((ahc->features & AHC_CMD_CHAN) != 0) {
  1091. bmov HADDR, SHADDR, 4;
  1092. mov HCNT, MWI_RESIDUAL;
  1093. bmov HCNT[1], ALLZEROS, 2;
  1094. } else {
  1095. mvi DINDEX, HADDR;
  1096. mvi SHADDR call bcopy_4;
  1097. mov MWI_RESIDUAL call set_hcnt;
  1098. }
  1099. clr MWI_RESIDUAL;
  1100. jmp sg_load_done;
  1101. no_mwi_resid:
  1102. }
  1103. test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jz sg_load;
  1104. or SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL;
  1105. jmp data_phase_finish;
  1106. sg_load:
  1107. /*
  1108. * Load the next SG element's data address and length
  1109. * into the DMA engine. If we don't have hardware
  1110. * to perform a prefetch, we'll have to fetch the
  1111. * segment from host memory first.
  1112. */
  1113. if ((ahc->features & AHC_CMD_CHAN) != 0) {
  1114. /* Wait for the idle loop to complete */
  1115. test CCSGCTL, CCSGEN jz . + 3;
  1116. call idle_loop;
  1117. test CCSGCTL, CCSGEN jnz . - 1;
  1118. bmov HADDR, CCSGRAM, 7;
  1119. /*
  1120. * Workaround for flaky external SCB RAM
  1121. * on certain aic7895 setups. It seems
  1122. * unable to handle direct transfers from
  1123. * S/G ram to certain SCB locations.
  1124. */
  1125. mov SINDEX, CCSGRAM;
  1126. mov SCB_RESIDUAL_DATACNT[3], SINDEX;
  1127. } else {
  1128. if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
  1129. mov ALLZEROS call set_hhaddr;
  1130. }
  1131. mvi DINDEX, HADDR;
  1132. mvi SCB_RESIDUAL_SGPTR call bcopy_4;
  1133. mvi SG_SIZEOF call set_hcnt;
  1134. or DFCNTRL, HDMAEN|DIRECTION|FIFORESET;
  1135. call dma_finish;
  1136. mvi DINDEX, HADDR;
  1137. call dfdat_in_7;
  1138. mov SCB_RESIDUAL_DATACNT[3], DFDAT;
  1139. }
  1140. if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
  1141. mov SCB_RESIDUAL_DATACNT[3] call set_hhaddr;
  1142. /*
  1143. * The lowest address byte must be loaded
  1144. * last as it triggers the computation of
  1145. * some items in the PCI block. The ULTRA2
  1146. * chips do this on PRELOAD.
  1147. */
  1148. mov HADDR, HADDR;
  1149. }
  1150. if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0
  1151. && ahc->pci_cachesize != 0) {
  1152. call calc_mwi_residual;
  1153. }
  1154. /* Point to the new next sg in memory */
  1155. call sg_advance;
  1156. sg_load_done:
  1157. if ((ahc->features & AHC_CMD_CHAN) != 0) {
  1158. bmov STCNT, HCNT, 3;
  1159. } else {
  1160. call set_stcnt_from_hcnt;
  1161. }
  1162. if ((ahc->flags & AHC_TARGETROLE) != 0) {
  1163. test SSTAT0, TARGET jnz data_phase_loop;
  1164. }
  1165. }
  1166. data_phase_finish:
  1167. /*
  1168. * If the target has left us in data phase, loop through
  1169. * the dma code again. In the case of ULTRA2 adapters,
  1170. * we should only loop if there is a data overrun. For
  1171. * all other adapters, we'll loop after each S/G element
  1172. * is loaded as well as if there is an overrun.
  1173. */
  1174. if ((ahc->flags & AHC_TARGETROLE) != 0) {
  1175. test SSTAT0, TARGET jnz data_phase_done;
  1176. }
  1177. if ((ahc->flags & AHC_INITIATORROLE) != 0) {
  1178. test SSTAT1, REQINIT jz .;
  1179. if ((ahc->features & AHC_DT) == 0) {
  1180. test SSTAT1,PHASEMIS jz data_phase_loop;
  1181. } else {
  1182. test SCSIPHASE, DATA_PHASE_MASK jnz data_phase_loop;
  1183. }
  1184. }
  1185. data_phase_done:
  1186. /*
  1187. * After a DMA finishes, save the SG and STCNT residuals back into
  1188. * the SCB. We use STCNT instead of HCNT, since it's a reflection
  1189. * of how many bytes were transferred on the SCSI (as opposed to the
  1190. * host) bus.
  1191. */
  1192. if ((ahc->features & AHC_CMD_CHAN) != 0) {
  1193. /* Kill off any pending prefetch */
  1194. call disable_ccsgen;
  1195. }
  1196. if ((ahc->features & AHC_ULTRA2) == 0) {
  1197. /*
  1198. * Clear the high address byte so that all other DMA
  1199. * operations, which use 32bit addressing, can assume
  1200. * HHADDR is 0.
  1201. */
  1202. if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
  1203. mov ALLZEROS call set_hhaddr;
  1204. }
  1205. }
  1206. /*
  1207. * Update our residual information before the information is
  1208. * lost by some other type of SCSI I/O (e.g. PIO). If we have
  1209. * transferred all data, no update is needed.
  1210. *
  1211. */
  1212. test SCB_RESIDUAL_SGPTR, SG_LIST_NULL jnz residual_update_done;
  1213. if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0
  1214. && ahc->pci_cachesize != 0) {
  1215. if ((ahc->features & AHC_CMD_CHAN) != 0) {
  1216. test MWI_RESIDUAL, 0xFF jz bmov_resid;
  1217. }
  1218. mov A, MWI_RESIDUAL;
  1219. add SCB_RESIDUAL_DATACNT[0], A, STCNT[0];
  1220. clr A;
  1221. adc SCB_RESIDUAL_DATACNT[1], A, STCNT[1];
  1222. adc SCB_RESIDUAL_DATACNT[2], A, STCNT[2];
  1223. clr MWI_RESIDUAL;
  1224. if ((ahc->features & AHC_CMD_CHAN) != 0) {
  1225. jmp . + 2;
  1226. bmov_resid:
  1227. bmov SCB_RESIDUAL_DATACNT, STCNT, 3;
  1228. }
  1229. } else if ((ahc->features & AHC_CMD_CHAN) != 0) {
  1230. bmov SCB_RESIDUAL_DATACNT, STCNT, 3;
  1231. } else {
  1232. mov SCB_RESIDUAL_DATACNT[0], STCNT[0];
  1233. mov SCB_RESIDUAL_DATACNT[1], STCNT[1];
  1234. mov SCB_RESIDUAL_DATACNT[2], STCNT[2];
  1235. }
  1236. residual_update_done:
  1237. /*
  1238. * Since we've been through a data phase, the SCB_RESID* fields
  1239. * are now initialized. Clear the full residual flag.
  1240. */
  1241. and SCB_SGPTR[0], ~SG_FULL_RESID;
  1242. if ((ahc->features & AHC_ULTRA2) != 0) {
  1243. /* Clear the channel in case we return to data phase later */
  1244. or SXFRCTL0, CLRSTCNT|CLRCHN;
  1245. or SXFRCTL0, CLRSTCNT|CLRCHN;
  1246. }
  1247. if ((ahc->flags & AHC_TARGETROLE) != 0) {
  1248. test SEQ_FLAGS, DPHASE_PENDING jz ITloop;
  1249. and SEQ_FLAGS, ~DPHASE_PENDING;
  1250. /*
  1251. * For data-in phases, wait for any pending acks from the
  1252. * initiator before changing phase. We only need to
  1253. * send Ignore Wide Residue messages for data-in phases.
  1254. */
  1255. test DFCNTRL, DIRECTION jz target_ITloop;
  1256. test SSTAT1, REQINIT jnz .;
  1257. test SCB_LUN, SCB_XFERLEN_ODD jz target_ITloop;
  1258. test SCSIRATE, WIDEXFER jz target_ITloop;
  1259. /*
  1260. * Issue an Ignore Wide Residue Message.
  1261. */
  1262. mvi P_MESGIN|BSYO call change_phase;
  1263. mvi MSG_IGN_WIDE_RESIDUE call target_outb;
  1264. mvi 1 call target_outb;
  1265. jmp target_ITloop;
  1266. } else {
  1267. jmp ITloop;
  1268. }
  1269. if ((ahc->flags & AHC_INITIATORROLE) != 0) {
  1270. /*
  1271. * Command phase. Set up the DMA registers and let 'er rip.
  1272. */
  1273. p_command:
  1274. test SEQ_FLAGS, NOT_IDENTIFIED jz p_command_okay;
  1275. mvi PROTO_VIOLATION call set_seqint;
  1276. p_command_okay:
  1277. if ((ahc->features & AHC_ULTRA2) != 0) {
  1278. bmov HCNT[0], SCB_CDB_LEN, 1;
  1279. bmov HCNT[1], ALLZEROS, 2;
  1280. mvi SG_CACHE_PRE, LAST_SEG;
  1281. } else if ((ahc->features & AHC_CMD_CHAN) != 0) {
  1282. bmov STCNT[0], SCB_CDB_LEN, 1;
  1283. bmov STCNT[1], ALLZEROS, 2;
  1284. } else {
  1285. mov STCNT[0], SCB_CDB_LEN;
  1286. clr STCNT[1];
  1287. clr STCNT[2];
  1288. }
  1289. add NONE, -13, SCB_CDB_LEN;
  1290. mvi SCB_CDB_STORE jnc p_command_embedded;
  1291. p_command_from_host:
  1292. if ((ahc->features & AHC_ULTRA2) != 0) {
  1293. bmov HADDR[0], SCB_CDB_PTR, 4;
  1294. mvi DFCNTRL, (PRELOADEN|SCSIEN|HDMAEN|DIRECTION);
  1295. } else {
  1296. if ((ahc->features & AHC_CMD_CHAN) != 0) {
  1297. bmov HADDR[0], SCB_CDB_PTR, 4;
  1298. bmov HCNT, STCNT, 3;
  1299. } else {
  1300. mvi DINDEX, HADDR;
  1301. mvi SCB_CDB_PTR call bcopy_4;
  1302. mov SCB_CDB_LEN call set_hcnt;
  1303. }
  1304. mvi DFCNTRL, (SCSIEN|SDMAEN|HDMAEN|DIRECTION|FIFORESET);
  1305. }
  1306. jmp p_command_xfer;
  1307. p_command_embedded:
  1308. /*
  1309. * The data fifo seems to require 4 byte aligned
  1310. * transfers from the sequencer. Force this to
  1311. * be the case by clearing HADDR[0] even though
  1312. * we aren't going to touch host memory.
  1313. */
  1314. clr HADDR[0];
  1315. if ((ahc->features & AHC_ULTRA2) != 0) {
  1316. mvi DFCNTRL, (PRELOADEN|SCSIEN|DIRECTION);
  1317. bmov DFDAT, SCB_CDB_STORE, 12;
  1318. } else if ((ahc->features & AHC_CMD_CHAN) != 0) {
  1319. if ((ahc->flags & AHC_SCB_BTT) != 0) {
  1320. /*
  1321. * On the 7895 the data FIFO will
  1322. * get corrupted if you try to dump
  1323. * data from external SCB memory into
  1324. * the FIFO while it is enabled. So,
  1325. * fill the fifo and then enable SCSI
  1326. * transfers.
  1327. */
  1328. mvi DFCNTRL, (DIRECTION|FIFORESET);
  1329. } else {
  1330. mvi DFCNTRL, (SCSIEN|SDMAEN|DIRECTION|FIFORESET);
  1331. }
  1332. bmov DFDAT, SCB_CDB_STORE, 12;
  1333. if ((ahc->flags & AHC_SCB_BTT) != 0) {
  1334. mvi DFCNTRL, (SCSIEN|SDMAEN|DIRECTION|FIFOFLUSH);
  1335. } else {
  1336. or DFCNTRL, FIFOFLUSH;
  1337. }
  1338. } else {
  1339. mvi DFCNTRL, (SCSIEN|SDMAEN|DIRECTION|FIFORESET);
  1340. call copy_to_fifo_6;
  1341. call copy_to_fifo_6;
  1342. or DFCNTRL, FIFOFLUSH;
  1343. }
  1344. p_command_xfer:
  1345. and SEQ_FLAGS, ~NO_CDB_SENT;
  1346. if ((ahc->features & AHC_DT) == 0) {
  1347. test SSTAT0, SDONE jnz . + 2;
  1348. test SSTAT1, PHASEMIS jz . - 1;
  1349. /*
  1350. * Wait for our ACK to go-away on it's own
  1351. * instead of being killed by SCSIEN getting cleared.
  1352. */
  1353. test SCSISIGI, ACKI jnz .;
  1354. } else {
  1355. test DFCNTRL, SCSIEN jnz .;
  1356. }
  1357. test SSTAT0, SDONE jnz p_command_successful;
  1358. /*
  1359. * Don't allow a data phase if the command
  1360. * was not fully transferred.
  1361. */
  1362. or SEQ_FLAGS, NO_CDB_SENT;
  1363. p_command_successful:
  1364. and DFCNTRL, ~(SCSIEN|SDMAEN|HDMAEN);
  1365. test DFCNTRL, (SCSIEN|SDMAEN|HDMAEN) jnz .;
  1366. jmp ITloop;
  1367. /*
  1368. * Status phase. Wait for the data byte to appear, then read it
  1369. * and store it into the SCB.
  1370. */
  1371. p_status:
  1372. test SEQ_FLAGS, NOT_IDENTIFIED jnz mesgin_proto_violation;
  1373. p_status_okay:
  1374. mov SCB_SCSI_STATUS, SCSIDATL;
  1375. or SCB_CONTROL, STATUS_RCVD;
  1376. jmp ITloop;
  1377. /*
  1378. * Message out phase. If MSG_OUT is MSG_IDENTIFYFLAG, build a full
  1379. * indentify message sequence and send it to the target. The host may
  1380. * override this behavior by setting the MK_MESSAGE bit in the SCB
  1381. * control byte. This will cause us to interrupt the host and allow
  1382. * it to handle the message phase completely on its own. If the bit
  1383. * associated with this target is set, we will also interrupt the host,
  1384. * thereby allowing it to send a message on the next selection regardless
  1385. * of the transaction being sent.
  1386. *
  1387. * If MSG_OUT is == HOST_MSG, also interrupt the host and take a message.
  1388. * This is done to allow the host to send messages outside of an identify
  1389. * sequence while protecting the seqencer from testing the MK_MESSAGE bit
  1390. * on an SCB that might not be for the current nexus. (For example, a
  1391. * BDR message in response to a bad reselection would leave us pointed to
  1392. * an SCB that doesn't have anything to do with the current target).
  1393. *
  1394. * Otherwise, treat MSG_OUT as a 1 byte message to send (abort, abort tag,
  1395. * bus device reset).
  1396. *
  1397. * When there are no messages to send, MSG_OUT should be set to MSG_NOOP,
  1398. * in case the target decides to put us in this phase for some strange
  1399. * reason.
  1400. */
  1401. p_mesgout_retry:
  1402. /* Turn on ATN for the retry */
  1403. if ((ahc->features & AHC_DT) == 0) {
  1404. or SCSISIGO, ATNO, LASTPHASE;
  1405. } else {
  1406. mvi SCSISIGO, ATNO;
  1407. }
  1408. p_mesgout:
  1409. mov SINDEX, MSG_OUT;
  1410. cmp SINDEX, MSG_IDENTIFYFLAG jne p_mesgout_from_host;
  1411. test SCB_CONTROL,MK_MESSAGE jnz host_message_loop;
  1412. p_mesgout_identify:
  1413. or SINDEX, MSG_IDENTIFYFLAG|DISCENB, SAVED_LUN;
  1414. test SCB_CONTROL, DISCENB jnz . + 2;
  1415. and SINDEX, ~DISCENB;
  1416. /*
  1417. * Send a tag message if TAG_ENB is set in the SCB control block.
  1418. * Use SCB_TAG (the position in the kernel's SCB array) as the tag value.
  1419. */
  1420. p_mesgout_tag:
  1421. test SCB_CONTROL,TAG_ENB jz p_mesgout_onebyte;
  1422. mov SCSIDATL, SINDEX; /* Send the identify message */
  1423. call phase_lock;
  1424. cmp LASTPHASE, P_MESGOUT jne p_mesgout_done;
  1425. and SCSIDATL,TAG_ENB|SCB_TAG_TYPE,SCB_CONTROL;
  1426. call phase_lock;
  1427. cmp LASTPHASE, P_MESGOUT jne p_mesgout_done;
  1428. mov SCB_TAG jmp p_mesgout_onebyte;
  1429. /*
  1430. * Interrupt the driver, and allow it to handle this message
  1431. * phase and any required retries.
  1432. */
  1433. p_mesgout_from_host:
  1434. cmp SINDEX, HOST_MSG jne p_mesgout_onebyte;
  1435. jmp host_message_loop;
  1436. p_mesgout_onebyte:
  1437. mvi CLRSINT1, CLRATNO;
  1438. mov SCSIDATL, SINDEX;
  1439. /*
  1440. * If the next bus phase after ATN drops is message out, it means
  1441. * that the target is requesting that the last message(s) be resent.
  1442. */
  1443. call phase_lock;
  1444. cmp LASTPHASE, P_MESGOUT je p_mesgout_retry;
  1445. p_mesgout_done:
  1446. mvi CLRSINT1,CLRATNO; /* Be sure to turn ATNO off */
  1447. mov LAST_MSG, MSG_OUT;
  1448. mvi MSG_OUT, MSG_NOOP; /* No message left */
  1449. jmp ITloop;
  1450. /*
  1451. * Message in phase. Bytes are read using Automatic PIO mode.
  1452. */
  1453. p_mesgin:
  1454. mvi ACCUM call inb_first; /* read the 1st message byte */
  1455. test A,MSG_IDENTIFYFLAG jnz mesgin_identify;
  1456. cmp A,MSG_DISCONNECT je mesgin_disconnect;
  1457. cmp A,MSG_SAVEDATAPOINTER je mesgin_sdptrs;
  1458. cmp ALLZEROS,A je mesgin_complete;
  1459. cmp A,MSG_RESTOREPOINTERS je mesgin_rdptrs;
  1460. cmp A,MSG_IGN_WIDE_RESIDUE je mesgin_ign_wide_residue;
  1461. cmp A,MSG_NOOP je mesgin_done;
  1462. /*
  1463. * Pushed message loop to allow the kernel to
  1464. * run it's own message state engine. To avoid an
  1465. * extra nop instruction after signaling the kernel,
  1466. * we perform the phase_lock before checking to see
  1467. * if we should exit the loop and skip the phase_lock
  1468. * in the ITloop. Performing back to back phase_locks
  1469. * shouldn't hurt, but why do it twice...
  1470. */
  1471. host_message_loop:
  1472. mvi HOST_MSG_LOOP call set_seqint;
  1473. call phase_lock;
  1474. cmp RETURN_1, EXIT_MSG_LOOP je ITloop + 1;
  1475. jmp host_message_loop;
  1476. mesgin_ign_wide_residue:
  1477. if ((ahc->features & AHC_WIDE) != 0) {
  1478. test SCSIRATE, WIDEXFER jz mesgin_reject;
  1479. /* Pull the residue byte */
  1480. mvi ARG_1 call inb_next;
  1481. cmp ARG_1, 0x01 jne mesgin_reject;
  1482. test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jz . + 2;
  1483. test SCB_LUN, SCB_XFERLEN_ODD jnz mesgin_done;
  1484. mvi IGN_WIDE_RES call set_seqint;
  1485. jmp mesgin_done;
  1486. }
  1487. mesgin_proto_violation:
  1488. mvi PROTO_VIOLATION call set_seqint;
  1489. jmp mesgin_done;
  1490. mesgin_reject:
  1491. mvi MSG_MESSAGE_REJECT call mk_mesg;
  1492. mesgin_done:
  1493. mov NONE,SCSIDATL; /*dummy read from latch to ACK*/
  1494. jmp ITloop;
  1495. /*
  1496. * We received a "command complete" message. Put the SCB_TAG into the QOUTFIFO,
  1497. * and trigger a completion interrupt. Before doing so, check to see if there
  1498. * is a residual or the status byte is something other than STATUS_GOOD (0).
  1499. * In either of these conditions, we upload the SCB back to the host so it can
  1500. * process this information. In the case of a non zero status byte, we
  1501. * additionally interrupt the kernel driver synchronously, allowing it to
  1502. * decide if sense should be retrieved. If the kernel driver wishes to request
  1503. * sense, it will fill the kernel SCB with a request sense command, requeue
  1504. * it to the QINFIFO and tell us not to post to the QOUTFIFO by setting
  1505. * RETURN_1 to SEND_SENSE.
  1506. */
  1507. mesgin_complete:
  1508. /*
  1509. * If ATN is raised, we still want to give the target a message.
  1510. * Perhaps there was a parity error on this last message byte.
  1511. * Either way, the target should take us to message out phase
  1512. * and then attempt to complete the command again. We should use a
  1513. * critical section here to guard against a timeout triggering
  1514. * for this command and setting ATN while we are still processing
  1515. * the completion.
  1516. test SCSISIGI, ATNI jnz mesgin_done;
  1517. */
  1518. /*
  1519. * If we are identified and have successfully sent the CDB,
  1520. * any status will do. Optimize this fast path.
  1521. */
  1522. test SCB_CONTROL, STATUS_RCVD jz mesgin_proto_violation;
  1523. test SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT jz complete_accepted;
  1524. /*
  1525. * If the target never sent an identify message but instead went
  1526. * to mesgin to give an invalid message, let the host abort us.
  1527. */
  1528. test SEQ_FLAGS, NOT_IDENTIFIED jnz mesgin_proto_violation;
  1529. /*
  1530. * If we recevied good status but never successfully sent the
  1531. * cdb, abort the command.
  1532. */
  1533. test SCB_SCSI_STATUS,0xff jnz complete_accepted;
  1534. test SEQ_FLAGS, NO_CDB_SENT jnz mesgin_proto_violation;
  1535. complete_accepted:
  1536. /*
  1537. * See if we attempted to deliver a message but the target ingnored us.
  1538. */
  1539. test SCB_CONTROL, MK_MESSAGE jz . + 2;
  1540. mvi MKMSG_FAILED call set_seqint;
  1541. /*
  1542. * Check for residuals
  1543. */
  1544. test SCB_SGPTR, SG_LIST_NULL jnz check_status;/* No xfer */
  1545. test SCB_SGPTR, SG_FULL_RESID jnz upload_scb;/* Never xfered */
  1546. test SC