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/drivers/scsi/qla2xxx/qla_nx.c

http://github.com/mirrors/linux
C | 4531 lines | 3642 code | 547 blank | 342 comment | 553 complexity | 8078b80f2ba2d20db6e51aba3912ce64 MD5 | raw file

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   1/*
   2 * QLogic Fibre Channel HBA Driver
   3 * Copyright (c)  2003-2014 QLogic Corporation
   4 *
   5 * See LICENSE.qla2xxx for copyright and licensing details.
   6 */
   7#include "qla_def.h"
   8#include <linux/delay.h>
   9#include <linux/io-64-nonatomic-lo-hi.h>
  10#include <linux/pci.h>
  11#include <linux/ratelimit.h>
  12#include <linux/vmalloc.h>
  13#include <scsi/scsi_tcq.h>
  14
  15#define MASK(n)			((1ULL<<(n))-1)
  16#define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | \
  17	((addr >> 25) & 0x3ff))
  18#define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | \
  19	((addr >> 25) & 0x3ff))
  20#define MS_WIN(addr) (addr & 0x0ffc0000)
  21#define QLA82XX_PCI_MN_2M   (0)
  22#define QLA82XX_PCI_MS_2M   (0x80000)
  23#define QLA82XX_PCI_OCM0_2M (0xc0000)
  24#define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800)
  25#define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
  26#define BLOCK_PROTECT_BITS 0x0F
  27
  28/* CRB window related */
  29#define CRB_BLK(off)	((off >> 20) & 0x3f)
  30#define CRB_SUBBLK(off)	((off >> 16) & 0xf)
  31#define CRB_WINDOW_2M	(0x130060)
  32#define QLA82XX_PCI_CAMQM_2M_END	(0x04800800UL)
  33#define CRB_HI(off)	((qla82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \
  34			((off) & 0xf0000))
  35#define QLA82XX_PCI_CAMQM_2M_BASE	(0x000ff800UL)
  36#define CRB_INDIRECT_2M	(0x1e0000UL)
  37
  38#define MAX_CRB_XFORM 60
  39static unsigned long crb_addr_xform[MAX_CRB_XFORM];
  40static int qla82xx_crb_table_initialized;
  41
  42#define qla82xx_crb_addr_transform(name) \
  43	(crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \
  44	QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20)
  45
  46const int MD_MIU_TEST_AGT_RDDATA[] = {
  47	0x410000A8, 0x410000AC,
  48	0x410000B8, 0x410000BC
  49};
  50
  51static void qla82xx_crb_addr_transform_setup(void)
  52{
  53	qla82xx_crb_addr_transform(XDMA);
  54	qla82xx_crb_addr_transform(TIMR);
  55	qla82xx_crb_addr_transform(SRE);
  56	qla82xx_crb_addr_transform(SQN3);
  57	qla82xx_crb_addr_transform(SQN2);
  58	qla82xx_crb_addr_transform(SQN1);
  59	qla82xx_crb_addr_transform(SQN0);
  60	qla82xx_crb_addr_transform(SQS3);
  61	qla82xx_crb_addr_transform(SQS2);
  62	qla82xx_crb_addr_transform(SQS1);
  63	qla82xx_crb_addr_transform(SQS0);
  64	qla82xx_crb_addr_transform(RPMX7);
  65	qla82xx_crb_addr_transform(RPMX6);
  66	qla82xx_crb_addr_transform(RPMX5);
  67	qla82xx_crb_addr_transform(RPMX4);
  68	qla82xx_crb_addr_transform(RPMX3);
  69	qla82xx_crb_addr_transform(RPMX2);
  70	qla82xx_crb_addr_transform(RPMX1);
  71	qla82xx_crb_addr_transform(RPMX0);
  72	qla82xx_crb_addr_transform(ROMUSB);
  73	qla82xx_crb_addr_transform(SN);
  74	qla82xx_crb_addr_transform(QMN);
  75	qla82xx_crb_addr_transform(QMS);
  76	qla82xx_crb_addr_transform(PGNI);
  77	qla82xx_crb_addr_transform(PGND);
  78	qla82xx_crb_addr_transform(PGN3);
  79	qla82xx_crb_addr_transform(PGN2);
  80	qla82xx_crb_addr_transform(PGN1);
  81	qla82xx_crb_addr_transform(PGN0);
  82	qla82xx_crb_addr_transform(PGSI);
  83	qla82xx_crb_addr_transform(PGSD);
  84	qla82xx_crb_addr_transform(PGS3);
  85	qla82xx_crb_addr_transform(PGS2);
  86	qla82xx_crb_addr_transform(PGS1);
  87	qla82xx_crb_addr_transform(PGS0);
  88	qla82xx_crb_addr_transform(PS);
  89	qla82xx_crb_addr_transform(PH);
  90	qla82xx_crb_addr_transform(NIU);
  91	qla82xx_crb_addr_transform(I2Q);
  92	qla82xx_crb_addr_transform(EG);
  93	qla82xx_crb_addr_transform(MN);
  94	qla82xx_crb_addr_transform(MS);
  95	qla82xx_crb_addr_transform(CAS2);
  96	qla82xx_crb_addr_transform(CAS1);
  97	qla82xx_crb_addr_transform(CAS0);
  98	qla82xx_crb_addr_transform(CAM);
  99	qla82xx_crb_addr_transform(C2C1);
 100	qla82xx_crb_addr_transform(C2C0);
 101	qla82xx_crb_addr_transform(SMB);
 102	qla82xx_crb_addr_transform(OCM0);
 103	/*
 104	 * Used only in P3 just define it for P2 also.
 105	 */
 106	qla82xx_crb_addr_transform(I2C0);
 107
 108	qla82xx_crb_table_initialized = 1;
 109}
 110
 111static struct crb_128M_2M_block_map crb_128M_2M_map[64] = {
 112	{{{0, 0,         0,         0} } },
 113	{{{1, 0x0100000, 0x0102000, 0x120000},
 114	{1, 0x0110000, 0x0120000, 0x130000},
 115	{1, 0x0120000, 0x0122000, 0x124000},
 116	{1, 0x0130000, 0x0132000, 0x126000},
 117	{1, 0x0140000, 0x0142000, 0x128000},
 118	{1, 0x0150000, 0x0152000, 0x12a000},
 119	{1, 0x0160000, 0x0170000, 0x110000},
 120	{1, 0x0170000, 0x0172000, 0x12e000},
 121	{0, 0x0000000, 0x0000000, 0x000000},
 122	{0, 0x0000000, 0x0000000, 0x000000},
 123	{0, 0x0000000, 0x0000000, 0x000000},
 124	{0, 0x0000000, 0x0000000, 0x000000},
 125	{0, 0x0000000, 0x0000000, 0x000000},
 126	{0, 0x0000000, 0x0000000, 0x000000},
 127	{1, 0x01e0000, 0x01e0800, 0x122000},
 128	{0, 0x0000000, 0x0000000, 0x000000} } } ,
 129	{{{1, 0x0200000, 0x0210000, 0x180000} } },
 130	{{{0, 0,         0,         0} } },
 131	{{{1, 0x0400000, 0x0401000, 0x169000} } },
 132	{{{1, 0x0500000, 0x0510000, 0x140000} } },
 133	{{{1, 0x0600000, 0x0610000, 0x1c0000} } },
 134	{{{1, 0x0700000, 0x0704000, 0x1b8000} } },
 135	{{{1, 0x0800000, 0x0802000, 0x170000},
 136	{0, 0x0000000, 0x0000000, 0x000000},
 137	{0, 0x0000000, 0x0000000, 0x000000},
 138	{0, 0x0000000, 0x0000000, 0x000000},
 139	{0, 0x0000000, 0x0000000, 0x000000},
 140	{0, 0x0000000, 0x0000000, 0x000000},
 141	{0, 0x0000000, 0x0000000, 0x000000},
 142	{0, 0x0000000, 0x0000000, 0x000000},
 143	{0, 0x0000000, 0x0000000, 0x000000},
 144	{0, 0x0000000, 0x0000000, 0x000000},
 145	{0, 0x0000000, 0x0000000, 0x000000},
 146	{0, 0x0000000, 0x0000000, 0x000000},
 147	{0, 0x0000000, 0x0000000, 0x000000},
 148	{0, 0x0000000, 0x0000000, 0x000000},
 149	{0, 0x0000000, 0x0000000, 0x000000},
 150	{1, 0x08f0000, 0x08f2000, 0x172000} } },
 151	{{{1, 0x0900000, 0x0902000, 0x174000},
 152	{0, 0x0000000, 0x0000000, 0x000000},
 153	{0, 0x0000000, 0x0000000, 0x000000},
 154	{0, 0x0000000, 0x0000000, 0x000000},
 155	{0, 0x0000000, 0x0000000, 0x000000},
 156	{0, 0x0000000, 0x0000000, 0x000000},
 157	{0, 0x0000000, 0x0000000, 0x000000},
 158	{0, 0x0000000, 0x0000000, 0x000000},
 159	{0, 0x0000000, 0x0000000, 0x000000},
 160	{0, 0x0000000, 0x0000000, 0x000000},
 161	{0, 0x0000000, 0x0000000, 0x000000},
 162	{0, 0x0000000, 0x0000000, 0x000000},
 163	{0, 0x0000000, 0x0000000, 0x000000},
 164	{0, 0x0000000, 0x0000000, 0x000000},
 165	{0, 0x0000000, 0x0000000, 0x000000},
 166	{1, 0x09f0000, 0x09f2000, 0x176000} } },
 167	{{{0, 0x0a00000, 0x0a02000, 0x178000},
 168	{0, 0x0000000, 0x0000000, 0x000000},
 169	{0, 0x0000000, 0x0000000, 0x000000},
 170	{0, 0x0000000, 0x0000000, 0x000000},
 171	{0, 0x0000000, 0x0000000, 0x000000},
 172	{0, 0x0000000, 0x0000000, 0x000000},
 173	{0, 0x0000000, 0x0000000, 0x000000},
 174	{0, 0x0000000, 0x0000000, 0x000000},
 175	{0, 0x0000000, 0x0000000, 0x000000},
 176	{0, 0x0000000, 0x0000000, 0x000000},
 177	{0, 0x0000000, 0x0000000, 0x000000},
 178	{0, 0x0000000, 0x0000000, 0x000000},
 179	{0, 0x0000000, 0x0000000, 0x000000},
 180	{0, 0x0000000, 0x0000000, 0x000000},
 181	{0, 0x0000000, 0x0000000, 0x000000},
 182	{1, 0x0af0000, 0x0af2000, 0x17a000} } },
 183	{{{0, 0x0b00000, 0x0b02000, 0x17c000},
 184	{0, 0x0000000, 0x0000000, 0x000000},
 185	{0, 0x0000000, 0x0000000, 0x000000},
 186	{0, 0x0000000, 0x0000000, 0x000000},
 187	{0, 0x0000000, 0x0000000, 0x000000},
 188	{0, 0x0000000, 0x0000000, 0x000000},
 189	{0, 0x0000000, 0x0000000, 0x000000},
 190	{0, 0x0000000, 0x0000000, 0x000000},
 191	{0, 0x0000000, 0x0000000, 0x000000},
 192	{0, 0x0000000, 0x0000000, 0x000000},
 193	{0, 0x0000000, 0x0000000, 0x000000},
 194	{0, 0x0000000, 0x0000000, 0x000000},
 195	{0, 0x0000000, 0x0000000, 0x000000},
 196	{0, 0x0000000, 0x0000000, 0x000000},
 197	{0, 0x0000000, 0x0000000, 0x000000},
 198	{1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
 199	{{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },
 200	{{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },
 201	{{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },
 202	{{{1, 0x0f00000, 0x0f01000, 0x164000} } },
 203	{{{0, 0x1000000, 0x1004000, 0x1a8000} } },
 204	{{{1, 0x1100000, 0x1101000, 0x160000} } },
 205	{{{1, 0x1200000, 0x1201000, 0x161000} } },
 206	{{{1, 0x1300000, 0x1301000, 0x162000} } },
 207	{{{1, 0x1400000, 0x1401000, 0x163000} } },
 208	{{{1, 0x1500000, 0x1501000, 0x165000} } },
 209	{{{1, 0x1600000, 0x1601000, 0x166000} } },
 210	{{{0, 0,         0,         0} } },
 211	{{{0, 0,         0,         0} } },
 212	{{{0, 0,         0,         0} } },
 213	{{{0, 0,         0,         0} } },
 214	{{{0, 0,         0,         0} } },
 215	{{{0, 0,         0,         0} } },
 216	{{{1, 0x1d00000, 0x1d10000, 0x190000} } },
 217	{{{1, 0x1e00000, 0x1e01000, 0x16a000} } },
 218	{{{1, 0x1f00000, 0x1f10000, 0x150000} } },
 219	{{{0} } },
 220	{{{1, 0x2100000, 0x2102000, 0x120000},
 221	{1, 0x2110000, 0x2120000, 0x130000},
 222	{1, 0x2120000, 0x2122000, 0x124000},
 223	{1, 0x2130000, 0x2132000, 0x126000},
 224	{1, 0x2140000, 0x2142000, 0x128000},
 225	{1, 0x2150000, 0x2152000, 0x12a000},
 226	{1, 0x2160000, 0x2170000, 0x110000},
 227	{1, 0x2170000, 0x2172000, 0x12e000},
 228	{0, 0x0000000, 0x0000000, 0x000000},
 229	{0, 0x0000000, 0x0000000, 0x000000},
 230	{0, 0x0000000, 0x0000000, 0x000000},
 231	{0, 0x0000000, 0x0000000, 0x000000},
 232	{0, 0x0000000, 0x0000000, 0x000000},
 233	{0, 0x0000000, 0x0000000, 0x000000},
 234	{0, 0x0000000, 0x0000000, 0x000000},
 235	{0, 0x0000000, 0x0000000, 0x000000} } },
 236	{{{1, 0x2200000, 0x2204000, 0x1b0000} } },
 237	{{{0} } },
 238	{{{0} } },
 239	{{{0} } },
 240	{{{0} } },
 241	{{{0} } },
 242	{{{1, 0x2800000, 0x2804000, 0x1a4000} } },
 243	{{{1, 0x2900000, 0x2901000, 0x16b000} } },
 244	{{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },
 245	{{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },
 246	{{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },
 247	{{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },
 248	{{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },
 249	{{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },
 250	{{{1, 0x3000000, 0x3000400, 0x1adc00} } },
 251	{{{0, 0x3100000, 0x3104000, 0x1a8000} } },
 252	{{{1, 0x3200000, 0x3204000, 0x1d4000} } },
 253	{{{1, 0x3300000, 0x3304000, 0x1a0000} } },
 254	{{{0} } },
 255	{{{1, 0x3500000, 0x3500400, 0x1ac000} } },
 256	{{{1, 0x3600000, 0x3600400, 0x1ae000} } },
 257	{{{1, 0x3700000, 0x3700400, 0x1ae400} } },
 258	{{{1, 0x3800000, 0x3804000, 0x1d0000} } },
 259	{{{1, 0x3900000, 0x3904000, 0x1b4000} } },
 260	{{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },
 261	{{{0} } },
 262	{{{0} } },
 263	{{{1, 0x3d00000, 0x3d04000, 0x1dc000} } },
 264	{{{1, 0x3e00000, 0x3e01000, 0x167000} } },
 265	{{{1, 0x3f00000, 0x3f01000, 0x168000} } }
 266};
 267
 268/*
 269 * top 12 bits of crb internal address (hub, agent)
 270 */
 271static unsigned qla82xx_crb_hub_agt[64] = {
 272	0,
 273	QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
 274	QLA82XX_HW_CRB_HUB_AGT_ADR_MN,
 275	QLA82XX_HW_CRB_HUB_AGT_ADR_MS,
 276	0,
 277	QLA82XX_HW_CRB_HUB_AGT_ADR_SRE,
 278	QLA82XX_HW_CRB_HUB_AGT_ADR_NIU,
 279	QLA82XX_HW_CRB_HUB_AGT_ADR_QMN,
 280	QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0,
 281	QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1,
 282	QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2,
 283	QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3,
 284	QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
 285	QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
 286	QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
 287	QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4,
 288	QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
 289	QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0,
 290	QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1,
 291	QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2,
 292	QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3,
 293	QLA82XX_HW_CRB_HUB_AGT_ADR_PGND,
 294	QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI,
 295	QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0,
 296	QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1,
 297	QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2,
 298	QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3,
 299	0,
 300	QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI,
 301	QLA82XX_HW_CRB_HUB_AGT_ADR_SN,
 302	0,
 303	QLA82XX_HW_CRB_HUB_AGT_ADR_EG,
 304	0,
 305	QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
 306	QLA82XX_HW_CRB_HUB_AGT_ADR_CAM,
 307	0,
 308	0,
 309	0,
 310	0,
 311	0,
 312	QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
 313	0,
 314	QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1,
 315	QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2,
 316	QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3,
 317	QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4,
 318	QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5,
 319	QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6,
 320	QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7,
 321	QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
 322	QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
 323	QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
 324	0,
 325	QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0,
 326	QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8,
 327	QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9,
 328	QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0,
 329	0,
 330	QLA82XX_HW_CRB_HUB_AGT_ADR_SMB,
 331	QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0,
 332	QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1,
 333	0,
 334	QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC,
 335	0,
 336};
 337
 338/* Device states */
 339static char *q_dev_state[] = {
 340	 "Unknown",
 341	"Cold",
 342	"Initializing",
 343	"Ready",
 344	"Need Reset",
 345	"Need Quiescent",
 346	"Failed",
 347	"Quiescent",
 348};
 349
 350char *qdev_state(uint32_t dev_state)
 351{
 352	return q_dev_state[dev_state];
 353}
 354
 355/*
 356 * In: 'off_in' is offset from CRB space in 128M pci map
 357 * Out: 'off_out' is 2M pci map addr
 358 * side effect: lock crb window
 359 */
 360static void
 361qla82xx_pci_set_crbwindow_2M(struct qla_hw_data *ha, ulong off_in,
 362			     void __iomem **off_out)
 363{
 364	u32 win_read;
 365	scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 366
 367	ha->crb_win = CRB_HI(off_in);
 368	writel(ha->crb_win, CRB_WINDOW_2M + ha->nx_pcibase);
 369
 370	/* Read back value to make sure write has gone through before trying
 371	 * to use it.
 372	 */
 373	win_read = RD_REG_DWORD(CRB_WINDOW_2M + ha->nx_pcibase);
 374	if (win_read != ha->crb_win) {
 375		ql_dbg(ql_dbg_p3p, vha, 0xb000,
 376		    "%s: Written crbwin (0x%x) "
 377		    "!= Read crbwin (0x%x), off=0x%lx.\n",
 378		    __func__, ha->crb_win, win_read, off_in);
 379	}
 380	*off_out = (off_in & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase;
 381}
 382
 383static inline unsigned long
 384qla82xx_pci_set_crbwindow(struct qla_hw_data *ha, u64 off)
 385{
 386	scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 387	/* See if we are currently pointing to the region we want to use next */
 388	if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_DDR_NET)) {
 389		/* No need to change window. PCIX and PCIEregs are in both
 390		 * regs are in both windows.
 391		 */
 392		return off;
 393	}
 394
 395	if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_PCIX_HOST2)) {
 396		/* We are in first CRB window */
 397		if (ha->curr_window != 0)
 398			WARN_ON(1);
 399		return off;
 400	}
 401
 402	if ((off > QLA82XX_CRB_PCIX_HOST2) && (off < QLA82XX_CRB_MAX)) {
 403		/* We are in second CRB window */
 404		off = off - QLA82XX_CRB_PCIX_HOST2 + QLA82XX_CRB_PCIX_HOST;
 405
 406		if (ha->curr_window != 1)
 407			return off;
 408
 409		/* We are in the QM or direct access
 410		 * register region - do nothing
 411		 */
 412		if ((off >= QLA82XX_PCI_DIRECT_CRB) &&
 413			(off < QLA82XX_PCI_CAMQM_MAX))
 414			return off;
 415	}
 416	/* strange address given */
 417	ql_dbg(ql_dbg_p3p, vha, 0xb001,
 418	    "%s: Warning: unm_nic_pci_set_crbwindow "
 419	    "called with an unknown address(%llx).\n",
 420	    QLA2XXX_DRIVER_NAME, off);
 421	return off;
 422}
 423
 424static int
 425qla82xx_pci_get_crb_addr_2M(struct qla_hw_data *ha, ulong off_in,
 426			    void __iomem **off_out)
 427{
 428	struct crb_128M_2M_sub_block_map *m;
 429
 430	if (off_in >= QLA82XX_CRB_MAX)
 431		return -1;
 432
 433	if (off_in >= QLA82XX_PCI_CAMQM && off_in < QLA82XX_PCI_CAMQM_2M_END) {
 434		*off_out = (off_in - QLA82XX_PCI_CAMQM) +
 435		    QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase;
 436		return 0;
 437	}
 438
 439	if (off_in < QLA82XX_PCI_CRBSPACE)
 440		return -1;
 441
 442	off_in -= QLA82XX_PCI_CRBSPACE;
 443
 444	/* Try direct map */
 445	m = &crb_128M_2M_map[CRB_BLK(off_in)].sub_block[CRB_SUBBLK(off_in)];
 446
 447	if (m->valid && (m->start_128M <= off_in) && (m->end_128M > off_in)) {
 448		*off_out = off_in + m->start_2M - m->start_128M + ha->nx_pcibase;
 449		return 0;
 450	}
 451	/* Not in direct map, use crb window */
 452	*off_out = (void __iomem *)off_in;
 453	return 1;
 454}
 455
 456#define CRB_WIN_LOCK_TIMEOUT 100000000
 457static int qla82xx_crb_win_lock(struct qla_hw_data *ha)
 458{
 459	int done = 0, timeout = 0;
 460
 461	while (!done) {
 462		/* acquire semaphore3 from PCI HW block */
 463		done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK));
 464		if (done == 1)
 465			break;
 466		if (timeout >= CRB_WIN_LOCK_TIMEOUT)
 467			return -1;
 468		timeout++;
 469	}
 470	qla82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->portnum);
 471	return 0;
 472}
 473
 474int
 475qla82xx_wr_32(struct qla_hw_data *ha, ulong off_in, u32 data)
 476{
 477	void __iomem *off;
 478	unsigned long flags = 0;
 479	int rv;
 480
 481	rv = qla82xx_pci_get_crb_addr_2M(ha, off_in, &off);
 482
 483	BUG_ON(rv == -1);
 484
 485	if (rv == 1) {
 486#ifndef __CHECKER__
 487		write_lock_irqsave(&ha->hw_lock, flags);
 488#endif
 489		qla82xx_crb_win_lock(ha);
 490		qla82xx_pci_set_crbwindow_2M(ha, off_in, &off);
 491	}
 492
 493	writel(data, (void __iomem *)off);
 494
 495	if (rv == 1) {
 496		qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK));
 497#ifndef __CHECKER__
 498		write_unlock_irqrestore(&ha->hw_lock, flags);
 499#endif
 500	}
 501	return 0;
 502}
 503
 504int
 505qla82xx_rd_32(struct qla_hw_data *ha, ulong off_in)
 506{
 507	void __iomem *off;
 508	unsigned long flags = 0;
 509	int rv;
 510	u32 data;
 511
 512	rv = qla82xx_pci_get_crb_addr_2M(ha, off_in, &off);
 513
 514	BUG_ON(rv == -1);
 515
 516	if (rv == 1) {
 517#ifndef __CHECKER__
 518		write_lock_irqsave(&ha->hw_lock, flags);
 519#endif
 520		qla82xx_crb_win_lock(ha);
 521		qla82xx_pci_set_crbwindow_2M(ha, off_in, &off);
 522	}
 523	data = RD_REG_DWORD(off);
 524
 525	if (rv == 1) {
 526		qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK));
 527#ifndef __CHECKER__
 528		write_unlock_irqrestore(&ha->hw_lock, flags);
 529#endif
 530	}
 531	return data;
 532}
 533
 534#define IDC_LOCK_TIMEOUT 100000000
 535int qla82xx_idc_lock(struct qla_hw_data *ha)
 536{
 537	int i;
 538	int done = 0, timeout = 0;
 539
 540	while (!done) {
 541		/* acquire semaphore5 from PCI HW block */
 542		done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK));
 543		if (done == 1)
 544			break;
 545		if (timeout >= IDC_LOCK_TIMEOUT)
 546			return -1;
 547
 548		timeout++;
 549
 550		/* Yield CPU */
 551		if (!in_interrupt())
 552			schedule();
 553		else {
 554			for (i = 0; i < 20; i++)
 555				cpu_relax();
 556		}
 557	}
 558
 559	return 0;
 560}
 561
 562void qla82xx_idc_unlock(struct qla_hw_data *ha)
 563{
 564	qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK));
 565}
 566
 567/*
 568 * check memory access boundary.
 569 * used by test agent. support ddr access only for now
 570 */
 571static unsigned long
 572qla82xx_pci_mem_bound_check(struct qla_hw_data *ha,
 573	unsigned long long addr, int size)
 574{
 575	if (!addr_in_range(addr, QLA82XX_ADDR_DDR_NET,
 576		QLA82XX_ADDR_DDR_NET_MAX) ||
 577		!addr_in_range(addr + size - 1, QLA82XX_ADDR_DDR_NET,
 578		QLA82XX_ADDR_DDR_NET_MAX) ||
 579		((size != 1) && (size != 2) && (size != 4) && (size != 8)))
 580			return 0;
 581	else
 582		return 1;
 583}
 584
 585static int qla82xx_pci_set_window_warning_count;
 586
 587static unsigned long
 588qla82xx_pci_set_window(struct qla_hw_data *ha, unsigned long long addr)
 589{
 590	int window;
 591	u32 win_read;
 592	scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 593
 594	if (addr_in_range(addr, QLA82XX_ADDR_DDR_NET,
 595		QLA82XX_ADDR_DDR_NET_MAX)) {
 596		/* DDR network side */
 597		window = MN_WIN(addr);
 598		ha->ddr_mn_window = window;
 599		qla82xx_wr_32(ha,
 600			ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window);
 601		win_read = qla82xx_rd_32(ha,
 602			ha->mn_win_crb | QLA82XX_PCI_CRBSPACE);
 603		if ((win_read << 17) != window) {
 604			ql_dbg(ql_dbg_p3p, vha, 0xb003,
 605			    "%s: Written MNwin (0x%x) != Read MNwin (0x%x).\n",
 606			    __func__, window, win_read);
 607		}
 608		addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET;
 609	} else if (addr_in_range(addr, QLA82XX_ADDR_OCM0,
 610		QLA82XX_ADDR_OCM0_MAX)) {
 611		unsigned int temp1;
 612
 613		if ((addr & 0x00ff800) == 0xff800) {
 614			ql_log(ql_log_warn, vha, 0xb004,
 615			    "%s: QM access not handled.\n", __func__);
 616			addr = -1UL;
 617		}
 618		window = OCM_WIN(addr);
 619		ha->ddr_mn_window = window;
 620		qla82xx_wr_32(ha,
 621			ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window);
 622		win_read = qla82xx_rd_32(ha,
 623			ha->mn_win_crb | QLA82XX_PCI_CRBSPACE);
 624		temp1 = ((window & 0x1FF) << 7) |
 625		    ((window & 0x0FFFE0000) >> 17);
 626		if (win_read != temp1) {
 627			ql_log(ql_log_warn, vha, 0xb005,
 628			    "%s: Written OCMwin (0x%x) != Read OCMwin (0x%x).\n",
 629			    __func__, temp1, win_read);
 630		}
 631		addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M;
 632
 633	} else if (addr_in_range(addr, QLA82XX_ADDR_QDR_NET,
 634		QLA82XX_P3_ADDR_QDR_NET_MAX)) {
 635		/* QDR network side */
 636		window = MS_WIN(addr);
 637		ha->qdr_sn_window = window;
 638		qla82xx_wr_32(ha,
 639			ha->ms_win_crb | QLA82XX_PCI_CRBSPACE, window);
 640		win_read = qla82xx_rd_32(ha,
 641			ha->ms_win_crb | QLA82XX_PCI_CRBSPACE);
 642		if (win_read != window) {
 643			ql_log(ql_log_warn, vha, 0xb006,
 644			    "%s: Written MSwin (0x%x) != Read MSwin (0x%x).\n",
 645			    __func__, window, win_read);
 646		}
 647		addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET;
 648	} else {
 649		/*
 650		 * peg gdb frequently accesses memory that doesn't exist,
 651		 * this limits the chit chat so debugging isn't slowed down.
 652		 */
 653		if ((qla82xx_pci_set_window_warning_count++ < 8) ||
 654		    (qla82xx_pci_set_window_warning_count%64 == 0)) {
 655			ql_log(ql_log_warn, vha, 0xb007,
 656			    "%s: Warning:%s Unknown address range!.\n",
 657			    __func__, QLA2XXX_DRIVER_NAME);
 658		}
 659		addr = -1UL;
 660	}
 661	return addr;
 662}
 663
 664/* check if address is in the same windows as the previous access */
 665static int qla82xx_pci_is_same_window(struct qla_hw_data *ha,
 666	unsigned long long addr)
 667{
 668	int			window;
 669	unsigned long long	qdr_max;
 670
 671	qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX;
 672
 673	/* DDR network side */
 674	if (addr_in_range(addr, QLA82XX_ADDR_DDR_NET,
 675		QLA82XX_ADDR_DDR_NET_MAX))
 676		BUG();
 677	else if (addr_in_range(addr, QLA82XX_ADDR_OCM0,
 678		QLA82XX_ADDR_OCM0_MAX))
 679		return 1;
 680	else if (addr_in_range(addr, QLA82XX_ADDR_OCM1,
 681		QLA82XX_ADDR_OCM1_MAX))
 682		return 1;
 683	else if (addr_in_range(addr, QLA82XX_ADDR_QDR_NET, qdr_max)) {
 684		/* QDR network side */
 685		window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f;
 686		if (ha->qdr_sn_window == window)
 687			return 1;
 688	}
 689	return 0;
 690}
 691
 692static int qla82xx_pci_mem_read_direct(struct qla_hw_data *ha,
 693	u64 off, void *data, int size)
 694{
 695	unsigned long   flags;
 696	void __iomem *addr = NULL;
 697	int             ret = 0;
 698	u64             start;
 699	uint8_t __iomem  *mem_ptr = NULL;
 700	unsigned long   mem_base;
 701	unsigned long   mem_page;
 702	scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 703
 704	write_lock_irqsave(&ha->hw_lock, flags);
 705
 706	/*
 707	 * If attempting to access unknown address or straddle hw windows,
 708	 * do not access.
 709	 */
 710	start = qla82xx_pci_set_window(ha, off);
 711	if ((start == -1UL) ||
 712		(qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
 713		write_unlock_irqrestore(&ha->hw_lock, flags);
 714		ql_log(ql_log_fatal, vha, 0xb008,
 715		    "%s out of bound pci memory "
 716		    "access, offset is 0x%llx.\n",
 717		    QLA2XXX_DRIVER_NAME, off);
 718		return -1;
 719	}
 720
 721	write_unlock_irqrestore(&ha->hw_lock, flags);
 722	mem_base = pci_resource_start(ha->pdev, 0);
 723	mem_page = start & PAGE_MASK;
 724	/* Map two pages whenever user tries to access addresses in two
 725	* consecutive pages.
 726	*/
 727	if (mem_page != ((start + size - 1) & PAGE_MASK))
 728		mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
 729	else
 730		mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
 731	if (mem_ptr == NULL) {
 732		*(u8  *)data = 0;
 733		return -1;
 734	}
 735	addr = mem_ptr;
 736	addr += start & (PAGE_SIZE - 1);
 737	write_lock_irqsave(&ha->hw_lock, flags);
 738
 739	switch (size) {
 740	case 1:
 741		*(u8  *)data = readb(addr);
 742		break;
 743	case 2:
 744		*(u16 *)data = readw(addr);
 745		break;
 746	case 4:
 747		*(u32 *)data = readl(addr);
 748		break;
 749	case 8:
 750		*(u64 *)data = readq(addr);
 751		break;
 752	default:
 753		ret = -1;
 754		break;
 755	}
 756	write_unlock_irqrestore(&ha->hw_lock, flags);
 757
 758	if (mem_ptr)
 759		iounmap(mem_ptr);
 760	return ret;
 761}
 762
 763static int
 764qla82xx_pci_mem_write_direct(struct qla_hw_data *ha,
 765	u64 off, void *data, int size)
 766{
 767	unsigned long   flags;
 768	void  __iomem *addr = NULL;
 769	int             ret = 0;
 770	u64             start;
 771	uint8_t __iomem *mem_ptr = NULL;
 772	unsigned long   mem_base;
 773	unsigned long   mem_page;
 774	scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 775
 776	write_lock_irqsave(&ha->hw_lock, flags);
 777
 778	/*
 779	 * If attempting to access unknown address or straddle hw windows,
 780	 * do not access.
 781	 */
 782	start = qla82xx_pci_set_window(ha, off);
 783	if ((start == -1UL) ||
 784		(qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
 785		write_unlock_irqrestore(&ha->hw_lock, flags);
 786		ql_log(ql_log_fatal, vha, 0xb009,
 787		    "%s out of bound memory "
 788		    "access, offset is 0x%llx.\n",
 789		    QLA2XXX_DRIVER_NAME, off);
 790		return -1;
 791	}
 792
 793	write_unlock_irqrestore(&ha->hw_lock, flags);
 794	mem_base = pci_resource_start(ha->pdev, 0);
 795	mem_page = start & PAGE_MASK;
 796	/* Map two pages whenever user tries to access addresses in two
 797	 * consecutive pages.
 798	 */
 799	if (mem_page != ((start + size - 1) & PAGE_MASK))
 800		mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2);
 801	else
 802		mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
 803	if (mem_ptr == NULL)
 804		return -1;
 805
 806	addr = mem_ptr;
 807	addr += start & (PAGE_SIZE - 1);
 808	write_lock_irqsave(&ha->hw_lock, flags);
 809
 810	switch (size) {
 811	case 1:
 812		writeb(*(u8  *)data, addr);
 813		break;
 814	case 2:
 815		writew(*(u16 *)data, addr);
 816		break;
 817	case 4:
 818		writel(*(u32 *)data, addr);
 819		break;
 820	case 8:
 821		writeq(*(u64 *)data, addr);
 822		break;
 823	default:
 824		ret = -1;
 825		break;
 826	}
 827	write_unlock_irqrestore(&ha->hw_lock, flags);
 828	if (mem_ptr)
 829		iounmap(mem_ptr);
 830	return ret;
 831}
 832
 833#define MTU_FUDGE_FACTOR 100
 834static unsigned long
 835qla82xx_decode_crb_addr(unsigned long addr)
 836{
 837	int i;
 838	unsigned long base_addr, offset, pci_base;
 839
 840	if (!qla82xx_crb_table_initialized)
 841		qla82xx_crb_addr_transform_setup();
 842
 843	pci_base = ADDR_ERROR;
 844	base_addr = addr & 0xfff00000;
 845	offset = addr & 0x000fffff;
 846
 847	for (i = 0; i < MAX_CRB_XFORM; i++) {
 848		if (crb_addr_xform[i] == base_addr) {
 849			pci_base = i << 20;
 850			break;
 851		}
 852	}
 853	if (pci_base == ADDR_ERROR)
 854		return pci_base;
 855	return pci_base + offset;
 856}
 857
 858static long rom_max_timeout = 100;
 859static long qla82xx_rom_lock_timeout = 100;
 860
 861static int
 862qla82xx_rom_lock(struct qla_hw_data *ha)
 863{
 864	int done = 0, timeout = 0;
 865	uint32_t lock_owner = 0;
 866	scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 867
 868	while (!done) {
 869		/* acquire semaphore2 from PCI HW block */
 870		done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK));
 871		if (done == 1)
 872			break;
 873		if (timeout >= qla82xx_rom_lock_timeout) {
 874			lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID);
 875			ql_dbg(ql_dbg_p3p, vha, 0xb157,
 876			    "%s: Simultaneous flash access by following ports, active port = %d: accessing port = %d",
 877			    __func__, ha->portnum, lock_owner);
 878			return -1;
 879		}
 880		timeout++;
 881	}
 882	qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ha->portnum);
 883	return 0;
 884}
 885
 886static void
 887qla82xx_rom_unlock(struct qla_hw_data *ha)
 888{
 889	qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, 0xffffffff);
 890	qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK));
 891}
 892
 893static int
 894qla82xx_wait_rom_busy(struct qla_hw_data *ha)
 895{
 896	long timeout = 0;
 897	long done = 0 ;
 898	scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 899
 900	while (done == 0) {
 901		done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS);
 902		done &= 4;
 903		timeout++;
 904		if (timeout >= rom_max_timeout) {
 905			ql_dbg(ql_dbg_p3p, vha, 0xb00a,
 906			    "%s: Timeout reached waiting for rom busy.\n",
 907			    QLA2XXX_DRIVER_NAME);
 908			return -1;
 909		}
 910	}
 911	return 0;
 912}
 913
 914static int
 915qla82xx_wait_rom_done(struct qla_hw_data *ha)
 916{
 917	long timeout = 0;
 918	long done = 0 ;
 919	scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 920
 921	while (done == 0) {
 922		done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS);
 923		done &= 2;
 924		timeout++;
 925		if (timeout >= rom_max_timeout) {
 926			ql_dbg(ql_dbg_p3p, vha, 0xb00b,
 927			    "%s: Timeout reached waiting for rom done.\n",
 928			    QLA2XXX_DRIVER_NAME);
 929			return -1;
 930		}
 931	}
 932	return 0;
 933}
 934
 935static int
 936qla82xx_md_rw_32(struct qla_hw_data *ha, uint32_t off, u32 data, uint8_t flag)
 937{
 938	uint32_t  off_value, rval = 0;
 939
 940	WRT_REG_DWORD(CRB_WINDOW_2M + ha->nx_pcibase, off & 0xFFFF0000);
 941
 942	/* Read back value to make sure write has gone through */
 943	RD_REG_DWORD(CRB_WINDOW_2M + ha->nx_pcibase);
 944	off_value  = (off & 0x0000FFFF);
 945
 946	if (flag)
 947		WRT_REG_DWORD(off_value + CRB_INDIRECT_2M + ha->nx_pcibase,
 948			      data);
 949	else
 950		rval = RD_REG_DWORD(off_value + CRB_INDIRECT_2M +
 951				    ha->nx_pcibase);
 952
 953	return rval;
 954}
 955
 956static int
 957qla82xx_do_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp)
 958{
 959	/* Dword reads to flash. */
 960	qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW, (addr & 0xFFFF0000), 1);
 961	*valp = qla82xx_md_rw_32(ha, MD_DIRECT_ROM_READ_BASE +
 962	    (addr & 0x0000FFFF), 0, 0);
 963
 964	return 0;
 965}
 966
 967static int
 968qla82xx_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp)
 969{
 970	int ret, loops = 0;
 971	uint32_t lock_owner = 0;
 972	scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 973
 974	while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) {
 975		udelay(100);
 976		schedule();
 977		loops++;
 978	}
 979	if (loops >= 50000) {
 980		lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID);
 981		ql_log(ql_log_fatal, vha, 0x00b9,
 982		    "Failed to acquire SEM2 lock, Lock Owner %u.\n",
 983		    lock_owner);
 984		return -1;
 985	}
 986	ret = qla82xx_do_rom_fast_read(ha, addr, valp);
 987	qla82xx_rom_unlock(ha);
 988	return ret;
 989}
 990
 991static int
 992qla82xx_read_status_reg(struct qla_hw_data *ha, uint32_t *val)
 993{
 994	scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 995
 996	qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_RDSR);
 997	qla82xx_wait_rom_busy(ha);
 998	if (qla82xx_wait_rom_done(ha)) {
 999		ql_log(ql_log_warn, vha, 0xb00c,
1000		    "Error waiting for rom done.\n");
1001		return -1;
1002	}
1003	*val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA);
1004	return 0;
1005}
1006
1007static int
1008qla82xx_flash_wait_write_finish(struct qla_hw_data *ha)
1009{
1010	long timeout = 0;
1011	uint32_t done = 1 ;
1012	uint32_t val;
1013	int ret = 0;
1014	scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1015
1016	qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
1017	while ((done != 0) && (ret == 0)) {
1018		ret = qla82xx_read_status_reg(ha, &val);
1019		done = val & 1;
1020		timeout++;
1021		udelay(10);
1022		cond_resched();
1023		if (timeout >= 50000) {
1024			ql_log(ql_log_warn, vha, 0xb00d,
1025			    "Timeout reached waiting for write finish.\n");
1026			return -1;
1027		}
1028	}
1029	return ret;
1030}
1031
1032static int
1033qla82xx_flash_set_write_enable(struct qla_hw_data *ha)
1034{
1035	uint32_t val;
1036
1037	qla82xx_wait_rom_busy(ha);
1038	qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
1039	qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WREN);
1040	qla82xx_wait_rom_busy(ha);
1041	if (qla82xx_wait_rom_done(ha))
1042		return -1;
1043	if (qla82xx_read_status_reg(ha, &val) != 0)
1044		return -1;
1045	if ((val & 2) != 2)
1046		return -1;
1047	return 0;
1048}
1049
1050static int
1051qla82xx_write_status_reg(struct qla_hw_data *ha, uint32_t val)
1052{
1053	scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1054
1055	if (qla82xx_flash_set_write_enable(ha))
1056		return -1;
1057	qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, val);
1058	qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0x1);
1059	if (qla82xx_wait_rom_done(ha)) {
1060		ql_log(ql_log_warn, vha, 0xb00e,
1061		    "Error waiting for rom done.\n");
1062		return -1;
1063	}
1064	return qla82xx_flash_wait_write_finish(ha);
1065}
1066
1067static int
1068qla82xx_write_disable_flash(struct qla_hw_data *ha)
1069{
1070	scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1071
1072	qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WRDI);
1073	if (qla82xx_wait_rom_done(ha)) {
1074		ql_log(ql_log_warn, vha, 0xb00f,
1075		    "Error waiting for rom done.\n");
1076		return -1;
1077	}
1078	return 0;
1079}
1080
1081static int
1082ql82xx_rom_lock_d(struct qla_hw_data *ha)
1083{
1084	int loops = 0;
1085	uint32_t lock_owner = 0;
1086	scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1087
1088	while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) {
1089		udelay(100);
1090		cond_resched();
1091		loops++;
1092	}
1093	if (loops >= 50000) {
1094		lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID);
1095		ql_log(ql_log_warn, vha, 0xb010,
1096		    "ROM lock failed, Lock Owner %u.\n", lock_owner);
1097		return -1;
1098	}
1099	return 0;
1100}
1101
1102static int
1103qla82xx_write_flash_dword(struct qla_hw_data *ha, uint32_t flashaddr,
1104	uint32_t data)
1105{
1106	int ret = 0;
1107	scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1108
1109	ret = ql82xx_rom_lock_d(ha);
1110	if (ret < 0) {
1111		ql_log(ql_log_warn, vha, 0xb011,
1112		    "ROM lock failed.\n");
1113		return ret;
1114	}
1115
1116	if (qla82xx_flash_set_write_enable(ha))
1117		goto done_write;
1118
1119	qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, data);
1120	qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, flashaddr);
1121	qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3);
1122	qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_PP);
1123	qla82xx_wait_rom_busy(ha);
1124	if (qla82xx_wait_rom_done(ha)) {
1125		ql_log(ql_log_warn, vha, 0xb012,
1126		    "Error waiting for rom done.\n");
1127		ret = -1;
1128		goto done_write;
1129	}
1130
1131	ret = qla82xx_flash_wait_write_finish(ha);
1132
1133done_write:
1134	qla82xx_rom_unlock(ha);
1135	return ret;
1136}
1137
1138/* This routine does CRB initialize sequence
1139 *  to put the ISP into operational state
1140 */
1141static int
1142qla82xx_pinit_from_rom(scsi_qla_host_t *vha)
1143{
1144	int addr, val;
1145	int i ;
1146	struct crb_addr_pair *buf;
1147	unsigned long off;
1148	unsigned offset, n;
1149	struct qla_hw_data *ha = vha->hw;
1150
1151	struct crb_addr_pair {
1152		long addr;
1153		long data;
1154	};
1155
1156	/* Halt all the individual PEGs and other blocks of the ISP */
1157	qla82xx_rom_lock(ha);
1158
1159	/* disable all I2Q */
1160	qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0);
1161	qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0);
1162	qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0);
1163	qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0);
1164	qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0);
1165	qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0);
1166
1167	/* disable all niu interrupts */
1168	qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff);
1169	/* disable xge rx/tx */
1170	qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00);
1171	/* disable xg1 rx/tx */
1172	qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00);
1173	/* disable sideband mac */
1174	qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00);
1175	/* disable ap0 mac */
1176	qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00);
1177	/* disable ap1 mac */
1178	qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00);
1179
1180	/* halt sre */
1181	val = qla82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000);
1182	qla82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1)));
1183
1184	/* halt epg */
1185	qla82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1);
1186
1187	/* halt timers */
1188	qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0);
1189	qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0);
1190	qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0);
1191	qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0);
1192	qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0);
1193	qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0);
1194
1195	/* halt pegs */
1196	qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1);
1197	qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1);
1198	qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1);
1199	qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1);
1200	qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1);
1201	msleep(20);
1202
1203	/* big hammer */
1204	if (test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))
1205		/* don't reset CAM block on reset */
1206		qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff);
1207	else
1208		qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff);
1209	qla82xx_rom_unlock(ha);
1210
1211	/* Read the signature value from the flash.
1212	 * Offset 0: Contain signature (0xcafecafe)
1213	 * Offset 4: Offset and number of addr/value pairs
1214	 * that present in CRB initialize sequence
1215	 */
1216	if (qla82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL ||
1217	    qla82xx_rom_fast_read(ha, 4, &n) != 0) {
1218		ql_log(ql_log_fatal, vha, 0x006e,
1219		    "Error Reading crb_init area: n: %08x.\n", n);
1220		return -1;
1221	}
1222
1223	/* Offset in flash = lower 16 bits
1224	 * Number of entries = upper 16 bits
1225	 */
1226	offset = n & 0xffffU;
1227	n = (n >> 16) & 0xffffU;
1228
1229	/* number of addr/value pair should not exceed 1024 entries */
1230	if (n  >= 1024) {
1231		ql_log(ql_log_fatal, vha, 0x0071,
1232		    "Card flash not initialized:n=0x%x.\n", n);
1233		return -1;
1234	}
1235
1236	ql_log(ql_log_info, vha, 0x0072,
1237	    "%d CRB init values found in ROM.\n", n);
1238
1239	buf = kmalloc_array(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
1240	if (buf == NULL) {
1241		ql_log(ql_log_fatal, vha, 0x010c,
1242		    "Unable to allocate memory.\n");
1243		return -ENOMEM;
1244	}
1245
1246	for (i = 0; i < n; i++) {
1247		if (qla82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 ||
1248		    qla82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) != 0) {
1249			kfree(buf);
1250			return -1;
1251		}
1252
1253		buf[i].addr = addr;
1254		buf[i].data = val;
1255	}
1256
1257	for (i = 0; i < n; i++) {
1258		/* Translate internal CRB initialization
1259		 * address to PCI bus address
1260		 */
1261		off = qla82xx_decode_crb_addr((unsigned long)buf[i].addr) +
1262		    QLA82XX_PCI_CRBSPACE;
1263		/* Not all CRB  addr/value pair to be written,
1264		 * some of them are skipped
1265		 */
1266
1267		/* skipping cold reboot MAGIC */
1268		if (off == QLA82XX_CAM_RAM(0x1fc))
1269			continue;
1270
1271		/* do not reset PCI */
1272		if (off == (ROMUSB_GLB + 0xbc))
1273			continue;
1274
1275		/* skip core clock, so that firmware can increase the clock */
1276		if (off == (ROMUSB_GLB + 0xc8))
1277			continue;
1278
1279		/* skip the function enable register */
1280		if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION))
1281			continue;
1282
1283		if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2))
1284			continue;
1285
1286		if ((off & 0x0ff00000) == QLA82XX_CRB_SMB)
1287			continue;
1288
1289		if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET)
1290			continue;
1291
1292		if (off == ADDR_ERROR) {
1293			ql_log(ql_log_fatal, vha, 0x0116,
1294			    "Unknown addr: 0x%08lx.\n", buf[i].addr);
1295			continue;
1296		}
1297
1298		qla82xx_wr_32(ha, off, buf[i].data);
1299
1300		/* ISP requires much bigger delay to settle down,
1301		 * else crb_window returns 0xffffffff
1302		 */
1303		if (off == QLA82XX_ROMUSB_GLB_SW_RESET)
1304			msleep(1000);
1305
1306		/* ISP requires millisec delay between
1307		 * successive CRB register updation
1308		 */
1309		msleep(1);
1310	}
1311
1312	kfree(buf);
1313
1314	/* Resetting the data and instruction cache */
1315	qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e);
1316	qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8);
1317	qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8);
1318
1319	/* Clear all protocol processing engines */
1320	qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0);
1321	qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0);
1322	qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0);
1323	qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0);
1324	qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0);
1325	qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0);
1326	qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0);
1327	qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0);
1328	return 0;
1329}
1330
1331static int
1332qla82xx_pci_mem_write_2M(struct qla_hw_data *ha,
1333		u64 off, void *data, int size)
1334{
1335	int i, j, ret = 0, loop, sz[2], off0;
1336	int scale, shift_amount, startword;
1337	uint32_t temp;
1338	uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
1339
1340	/*
1341	 * If not MN, go check for MS or invalid.
1342	 */
1343	if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1344		mem_crb = QLA82XX_CRB_QDR_NET;
1345	else {
1346		mem_crb = QLA82XX_CRB_DDR_NET;
1347		if (qla82xx_pci_mem_bound_check(ha, off, size) == 0)
1348			return qla82xx_pci_mem_write_direct(ha,
1349			    off, data, size);
1350	}
1351
1352	off0 = off & 0x7;
1353	sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1354	sz[1] = size - sz[0];
1355
1356	off8 = off & 0xfffffff0;
1357	loop = (((off & 0xf) + size - 1) >> 4) + 1;
1358	shift_amount = 4;
1359	scale = 2;
1360	startword = (off & 0xf)/8;
1361
1362	for (i = 0; i < loop; i++) {
1363		if (qla82xx_pci_mem_read_2M(ha, off8 +
1364		    (i << shift_amount), &word[i * scale], 8))
1365			return -1;
1366	}
1367
1368	switch (size) {
1369	case 1:
1370		tmpw = *((uint8_t *)data);
1371		break;
1372	case 2:
1373		tmpw = *((uint16_t *)data);
1374		break;
1375	case 4:
1376		tmpw = *((uint32_t *)data);
1377		break;
1378	case 8:
1379	default:
1380		tmpw = *((uint64_t *)data);
1381		break;
1382	}
1383
1384	if (sz[0] == 8) {
1385		word[startword] = tmpw;
1386	} else {
1387		word[startword] &=
1388			~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1389		word[startword] |= tmpw << (off0 * 8);
1390	}
1391	if (sz[1] != 0) {
1392		word[startword+1] &= ~(~0ULL << (sz[1] * 8));
1393		word[startword+1] |= tmpw >> (sz[0] * 8);
1394	}
1395
1396	for (i = 0; i < loop; i++) {
1397		temp = off8 + (i << shift_amount);
1398		qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp);
1399		temp = 0;
1400		qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp);
1401		temp = word[i * scale] & 0xffffffff;
1402		qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);
1403		temp = (word[i * scale] >> 32) & 0xffffffff;
1404		qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);
1405		temp = word[i*scale + 1] & 0xffffffff;
1406		qla82xx_wr_32(ha, mem_crb +
1407		    MIU_TEST_AGT_WRDATA_UPPER_LO, temp);
1408		temp = (word[i*scale + 1] >> 32) & 0xffffffff;
1409		qla82xx_wr_32(ha, mem_crb +
1410		    MIU_TEST_AGT_WRDATA_UPPER_HI, temp);
1411
1412		temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1413		qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1414		temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1415		qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1416
1417		for (j = 0; j < MAX_CTL_CHECK; j++) {
1418			temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1419			if ((temp & MIU_TA_CTL_BUSY) == 0)
1420				break;
1421		}
1422
1423		if (j >= MAX_CTL_CHECK) {
1424			if (printk_ratelimit())
1425				dev_err(&ha->pdev->dev,
1426				    "failed to write through agent.\n");
1427			ret = -1;
1428			break;
1429		}
1430	}
1431
1432	return ret;
1433}
1434
1435static int
1436qla82xx_fw_load_from_flash(struct qla_hw_data *ha)
1437{
1438	int  i;
1439	long size = 0;
1440	long flashaddr = ha->flt_region_bootload << 2;
1441	long memaddr = BOOTLD_START;
1442	u64 data;
1443	u32 high, low;
1444
1445	size = (IMAGE_START - BOOTLD_START) / 8;
1446
1447	for (i = 0; i < size; i++) {
1448		if ((qla82xx_rom_fast_read(ha, flashaddr, (int *)&low)) ||
1449		    (qla82xx_rom_fast_read(ha, flashaddr + 4, (int *)&high))) {
1450			return -1;
1451		}
1452		data = ((u64)high << 32) | low ;
1453		qla82xx_pci_mem_write_2M(ha, memaddr, &data, 8);
1454		flashaddr += 8;
1455		memaddr += 8;
1456
1457		if (i % 0x1000 == 0)
1458			msleep(1);
1459	}
1460	udelay(100);
1461	read_lock(&ha->hw_lock);
1462	qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020);
1463	qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e);
1464	read_unlock(&ha->hw_lock);
1465	return 0;
1466}
1467
1468int
1469qla82xx_pci_mem_read_2M(struct qla_hw_data *ha,
1470		u64 off, void *data, int size)
1471{
1472	int i, j = 0, k, start, end, loop, sz[2], off0[2];
1473	int	      shift_amount;
1474	uint32_t      temp;
1475	uint64_t      off8, val, mem_crb, word[2] = {0, 0};
1476
1477	/*
1478	 * If not MN, go check for MS or invalid.
1479	 */
1480
1481	if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1482		mem_crb = QLA82XX_CRB_QDR_NET;
1483	else {
1484		mem_crb = QLA82XX_CRB_DDR_NET;
1485		if (qla82xx_pci_mem_bound_check(ha, off, size) == 0)
1486			return qla82xx_pci_mem_read_direct(ha,
1487			    off, data, size);
1488	}
1489
1490	off8 = off & 0xfffffff0;
1491	off0[0] = off & 0xf;
1492	sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]);
1493	shift_amount = 4;
1494	loop = ((off0[0] + size - 1) >> shift_amount) + 1;
1495	off0[1] = 0;
1496	sz[1] = size - sz[0];
1497
1498	for (i = 0; i < loop; i++) {
1499		temp = off8 + (i << shift_amount);
1500		qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp);
1501		temp = 0;
1502		qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp);
1503		temp = MIU_TA_CTL_ENABLE;
1504		qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1505		temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
1506		qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1507
1508		for (j = 0; j < MAX_CTL_CHECK; j++) {
1509			temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1510			if ((temp & MIU_TA_CTL_BUSY) == 0)
1511				break;
1512		}
1513
1514		if (j >= MAX_CTL_CHECK) {
1515			if (printk_ratelimit())
1516				dev_err(&ha->pdev->dev,
1517				    "failed to read through agent.\n");
1518			break;
1519		}
1520
1521		start = off0[i] >> 2;
1522		end   = (off0[i] + sz[i] - 1) >> 2;
1523		for (k = start; k <= end; k++) {
1524			temp = qla82xx_rd_32(ha,
1525					mem_crb + MIU_TEST_AGT_RDDATA(k));
1526			word[i] |= ((uint64_t)temp << (32 * (k & 1)));
1527		}
1528	}
1529
1530	if (j >= MAX_CTL_CHECK)
1531		return -1;
1532
1533	if ((off0[0] & 7) == 0) {
1534		val = word[0];
1535	} else {
1536		val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1537			((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1538	}
1539
1540	switch (size) {
1541	case 1:
1542		*(uint8_t  *)data = val;
1543		break;
1544	case 2:
1545		*(uint16_t *)data = val;
1546		break;
1547	case 4:
1548		*(uint32_t *)data = val;
1549		break;
1550	case 8:
1551		*(uint64_t *)data = val;
1552		break;
1553	}
1554	return 0;
1555}
1556
1557
1558static struct qla82xx_uri_table_desc *
1559qla82xx_get_table_desc(const u8 *unirom, int section)
1560{
1561	uint32_t i;
1562	struct qla82xx_uri_table_desc *directory =
1563		(struct qla82xx_uri_table_desc *)&unirom[0];
1564	__le32 offset;
1565	__le32 tab_type;
1566	__le32 entries = cpu_to_le32(directory->num_entries);
1567
1568	for (i = 0; i < entries; i++) {
1569		offset = cpu_to_le32(directory->findex) +
1570		    (i * cpu_to_le32(directory->entry_size));
1571		tab_type = cpu_to_le32(*((u32 *)&unirom[offset] + 8));
1572
1573		if (tab_type == section)
1574			return (struct qla82xx_uri_table_desc *)&unirom[offset];
1575	}
1576
1577	return NULL;
1578}
1579
1580static struct qla82xx_uri_data_desc *
1581qla82xx_get_data_desc(struct qla_hw_data *ha,
1582	u32 section, u32 idx_offset)
1583{
1584	const u8 *unirom = ha->hablob->fw->data;
1585	int idx = cpu_to_le32(*((int *)&unirom[ha->file_prd_off] + idx_offset));
1586	struct qla82xx_uri_table_desc *tab_desc = NULL;
1587	__le32 offset;
1588
1589	tab_desc = qla82xx_get_table_desc(unirom, section);
1590	if (!tab_desc)
1591		return NULL;
1592
1593	offset = cpu_to_le32(tab_desc->findex) +
1594	    (cpu_to_le32(tab_desc->entry_size) * idx);
1595
1596	return (struct qla82xx_uri_data_desc *)&unirom[offset];
1597}
1598
1599static u8 *
1600qla82xx_get_bootld_offset(struct qla_hw_data *ha)
1601{
1602	u32 offset = BOOTLD_START;
1603	struct qla82xx_uri_data_desc *uri_desc = NULL;
1604
1605	if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1606		uri_desc = qla82xx_get_data_desc(ha,
1607		    QLA82XX_URI_DIR_SECT_BOOTLD, QLA82XX_URI_BOOTLD_IDX_OFF);
1608		if (uri_desc)
1609			offset = cpu_to_le32(uri_desc->findex);
1610	}
1611
1612	return (u8 *)&ha->hablob->fw->data[offset];
1613}
1614
1615static u32 qla82xx_get_fw_size(struct qla_hw_data *ha)
1616{
1617	struct qla82xx_uri_data_desc *uri_desc = NULL;
1618
1619	if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1620		uri_desc =  qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW,
1621		    QLA82XX_URI_FIRMWARE_IDX_OFF);
1622		if (uri_desc)
1623			return cpu_to_le32(uri_desc->size);
1624	}
1625
1626	return get_unaligned_le32(&ha->hablob->fw->data[FW_SIZE_OFFSET]);
1627}
1628
1629static u8 *
1630qla82xx_get_fw_offs(struct qla_hw_data *ha)
1631{
1632	u32 offset = IMAGE_START;
1633	struct qla82xx_uri_data_desc *uri_desc = NULL;
1634
1635	if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1636		uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW,
1637			QLA82XX_URI_FIRMWARE_IDX_OFF);
1638		if (uri_desc)
1639			offset = cpu_to_le32(uri_desc->findex);
1640	}
1641
1642	return (u8 *)&ha->hablob->fw->data[offset];
1643}
1644
1645/* PCI related functions */
1646int qla82xx_pci_region_offset(struct pci_dev *pdev, int region)
1647{
1648	unsigned long val = 0;
1649	u32 control;
1650
1651	switch (region) {
1652	case 0:
1653		val = 0;
1654		break;
1655	case 1:
1656		pci_read_config_dword(pdev, QLA82XX_PCI_REG_MSIX_TBL, &control);
1657		val = control + QLA82XX_MSIX_TBL_SPACE;
1658		break;
1659	}
1660	return val;
1661}
1662
1663
1664int
1665qla82xx_iospace_config(struct qla_hw_data *ha)
1666{
1667	uint32_t len = 0;
1668
1669	if (pci_request_regions(ha->pdev, QLA2XXX_DRIVER_NAME)) {
1670		ql_log_pci(ql_log_fatal, ha->pdev, 0x000c,
1671		    "Failed to reserver selected regions.\n");
1672		goto iospace_error_exit;
1673	}
1674
1675	/* Use MMIO operations for all accesses. */
1676	if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
1677		ql_log_pci(ql_log_fatal, ha->pdev, 0x000d,
1678		    "Region #0 not an MMIO resource, aborting.\n");
1679		goto iospace_error_exit;
1680	}
1681
1682	len = pci_resource_len(ha->pdev, 0);
1683	ha->nx_pcibase = ioremap(pci_resource_start(ha->pdev, 0), len);
1684	if (!ha->nx_pcibase) {
1685		ql_log_pci(ql_log_fatal, ha->pdev, 0x000e,
1686		    "Cannot remap pcibase MMIO, aborting.\n");
1687		goto iospace_error_exit;
1688	}
1689
1690	/* Mapping of IO base pointer */
1691	if (IS_QLA8044(ha)) {
1692		ha->iobase = ha->nx_pcibase;
1693	} else if (IS_QLA82XX(ha)) {
1694		ha->iobase = ha->nx_pcibase + 0xbc000 + (ha->pdev->devfn << 11);
1695	}
1696
1697	if (!ql2xdbwr) {
1698		ha->nxdb_wr_ptr = ioremap((pci_resource_start(ha->pdev, 4) +
1699		    (ha->pdev->devfn << 12)), 4);
1700		if (!ha->nxdb_wr_ptr) {
1701			ql_log_pci(ql_log_fatal, ha->pdev, 0x000f,
1702			    "Cannot remap MMIO, aborting.\n");
1703			goto iospace_error_exit;
1704		}
1705
1706		/* Mapping of IO base pointer,
1707		 * door bell read and write pointer
1708		 */
1709		ha->nxdb_rd_ptr = ha->nx_pcibase + (512 * 1024) +
1710		    (ha->pdev->devfn * 8);
1711	} else {
1712		ha->nxdb_wr_ptr = (void __iomem *)(ha->pdev->devfn == 6 ?
1713			QLA82XX_CAMRAM_DB1 :
1714			QLA82XX_CAMRAM_DB2);
1715	}
1716
1717	ha->max_req_queues = ha->max_rsp_queues = 1;
1718	ha->msix_count = ha->max_rsp_queues + 1;
1719	ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc006,
1720	    "nx_pci_base=%p iobase=%p "
1721	    "max_req_queues=%d msix_count=%d.\n",
1722	    ha->nx_pcibase, ha->iobase,
1723	    ha->max_req_queues, ha->msix_count);
1724	ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0010,
1725	    "nx_pci_base=%p iobase=%p "
1726	    "max_req_queues=%d msix_count=%d.\n",
1727	    ha->nx_pcibase, ha->iobase,
1728	    ha->max_req_queues, ha->msix_count);
1729	return 0;
1730
1731iospace_error_exit:
1732	return -ENOMEM;
1733}
1734
1735/* GS related functions */
1736
1737/* Initialization related functions */
1738
1739/**
1740 * qla82xx_pci_config() - Setup ISP82xx PCI configuration registers.
1741 * @vha: HA context
1742 *
1743 * Returns 0 on success.
1744*/
1745int
1746qla82xx_pci_config(scsi_qla_host_t *vha)
1747{
1748	struct qla_hw_data *ha = vha->hw;
1749	int ret;
1750
1751	pci_set_master(ha->pdev);
1752	ret = pci_set_mwi(ha->pdev);
1753	ha->chip_revision = ha->pdev->revision;
1754	ql_dbg(ql_dbg_init, vha, 0x0043,
1755	    "Chip revision:%d; pci_set_mwi() returned %d.\n",
1756	    ha->chip_revision, ret);
1757	return 0;
1758}
1759
1760/**
1761 * qla82xx_reset_chip() - Setup ISP82xx PCI configuration registers.
1762 * @vha: HA context
1763 *
1764 * Returns 0 on success.
1765 */
1766int
1767qla82xx_reset_chip(scsi_qla_host_t *vha)
1768{
1769	struct qla_hw_data *ha = vha->hw;
1770
1771	ha->isp_ops->disable_intrs(ha);
1772
1773	return QLA_SUCCESS;
1774}
1775
1776void qla82xx_config_rings(struct scsi_qla_host *vha)
1777{
1778	struct qla_hw_data *ha = vha->hw;
1779	struct device_reg_82xx __iomem *reg = &ha->iobase->isp82;
1780	struct init_cb_81xx *icb;
1781	struct req_que *req = ha->req_q_map[0];
1782	struct rsp_que *rsp = ha->rsp_q_map[0];
1783
1784	/* Setup ring parameters in initialization control block. */
1785	icb = (struct init_cb_81xx *)ha->init_cb;
1786	icb->request_q_outpointer = cpu_to_le16(0);
1787	icb->response_q_inpointer = cpu_to_le16(0);
1788	icb->request_q_length = cpu_to_le16(req->length);
1789	icb->response_q_length = cpu_to_le16(rsp->length);
1790	put_unaligned_le64(req->dma, &icb->request_q_address);
1791	put_unaligned_le64(rsp->dma, &icb->response_q_address);
1792
1793	WRT_REG_DWORD(&reg->req_q_out[0], 0);
1794	WRT_REG_DWORD(&reg->rsp_q_in[0], 0);
1795	WRT_REG_DWORD(&reg->rsp_q_out[0], 0);
1796}
1797
1798static int
1799qla82xx_fw_load_from_blob(struct qla_hw_data *ha)
1800{
1801	u64 *ptr64;
1802	u32 i, flashaddr, size;
1803	__le64 data;
1804
1805	size = (IMAGE_START - BOOTLD_START) / 8;
1806
1807	ptr64 = (u64 *)qla82xx_get_bootld_offset(ha);
1808	flashaddr = BOOTLD_START;
1809
1810	for (i = 0; i < size; i++) {
1811		data = cpu_to_le64(ptr64[i]);
1812		if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8))
1813			return -EIO;
1814		flashaddr += 8;
1815	}
1816
1817	flashaddr = FLASH_ADDR_START;
1818	size = qla82xx_get_fw_size(ha) / 8;
1819	ptr64 = (u64 *)qla82xx_get_fw_offs(ha);
1820
1821	for (i = 0; i < size; i++) {
1822		data = cpu_to_le64(ptr64[i]);
1823
1824		if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8))
1825			return -EIO;
1826		flashaddr += 8;
1827	}
1828	udelay(100);
1829
1830	/* Write a magic value to CAMRAM register
1831	 * at a specified offset to indicate
1832	 * that all data is written and
1833	 * ready for firmware to initialize.
1834	 */
1835	qla82xx_wr_32(ha, QLA82XX_CAM_RAM(0x1fc), QLA82XX_BDINFO_MAGIC);
1836
1837	read_lock(&ha->hw_lock);
1838	qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020);
1839	qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e);
1840	read_unlock(&ha->hw_lock);
1841	return 0;
1842}
1843
1844static int
1845qla82xx_set_product_offset(struct qla_hw_data *ha)
1846{
1847	struct qla82xx_uri_table_desc *ptab_desc = NULL;
1848	const uint8_t *unirom = ha->hablob->fw->data;
1849	uint32_t i;
1850	__le32 entries;
1851	__le32 flags, file_chiprev, offset;
1852	uint8_t chiprev = ha->chip_revision;
1853	/* Hardcoding mn_present flag for P3P */
1854	int mn_present = 0;
1855	uint32_t flagbit;
1856
1857	ptab_desc = qla82xx_get_table_desc(unirom,
1858		 QLA82XX_URI_DIR_SECT_PRODUCT_TBL);
1859	if (!ptab_desc)
1860		return -1;
1861
1862	entries = cpu_to_le32(ptab_desc->num_entries);
1863
1864	for (i = 0; i < entries; i++) {
1865		offset = cpu_to_le32(ptab_desc->findex) +
1866			(i * cpu_to_le32(ptab_desc->entry_size));
1867		flags = cpu_to_le32(*((int *)&unirom[offset] +
1868			QLA82XX_URI_FLAGS_OFF));
1869		file_chiprev = cpu_to_le32(*((int *)&unirom[offset] +
1870			QLA82XX_URI_CHIP_REV_OFF));
1871
1872		flagbit = mn_present ? 1 : 2;
1873
1874		if ((chiprev == file_chiprev) && ((1ULL << flagbit) & flags)) {
1875			ha->file_prd_off = offset;
1876			return 0;
1877		}
1878	}
1879	return -1;
1880}
1881
1882static int
1883qla82xx_validate_firmware_blob(scsi_qla_host_t *vha, uint8_t fw_type)
1884{
1885	uint32_t val;
1886	uint32_t min_size;
1887	struct qla_hw_data *ha = vha->hw;
1888	const struct firmware *fw = ha->hablob->fw;
1889
1890	ha->fw_

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