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/drivers/idle/intel_idle.c

http://github.com/mirrors/linux
C | 1695 lines | 1331 code | 178 blank | 186 comment | 80 complexity | 7418e14309f87367c81f21d4387d3d8a MD5 | raw file
   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * intel_idle.c - native hardware idle loop for modern Intel processors
   4 *
   5 * Copyright (c) 2013 - 2020, Intel Corporation.
   6 * Len Brown <len.brown@intel.com>
   7 * Rafael J. Wysocki <rafael.j.wysocki@intel.com>
   8 */
   9
  10/*
  11 * intel_idle is a cpuidle driver that loads on specific Intel processors
  12 * in lieu of the legacy ACPI processor_idle driver.  The intent is to
  13 * make Linux more efficient on these processors, as intel_idle knows
  14 * more than ACPI, as well as make Linux more immune to ACPI BIOS bugs.
  15 */
  16
  17/*
  18 * Design Assumptions
  19 *
  20 * All CPUs have same idle states as boot CPU
  21 *
  22 * Chipset BM_STS (bus master status) bit is a NOP
  23 *	for preventing entry into deep C-stats
  24 */
  25
  26/*
  27 * Known limitations
  28 *
  29 * ACPI has a .suspend hack to turn off deep c-statees during suspend
  30 * to avoid complications with the lapic timer workaround.
  31 * Have not seen issues with suspend, but may need same workaround here.
  32 *
  33 */
  34
  35/* un-comment DEBUG to enable pr_debug() statements */
  36#define DEBUG
  37
  38#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  39
  40#include <linux/acpi.h>
  41#include <linux/kernel.h>
  42#include <linux/cpuidle.h>
  43#include <linux/tick.h>
  44#include <trace/events/power.h>
  45#include <linux/sched.h>
  46#include <linux/notifier.h>
  47#include <linux/cpu.h>
  48#include <linux/moduleparam.h>
  49#include <asm/cpu_device_id.h>
  50#include <asm/intel-family.h>
  51#include <asm/mwait.h>
  52#include <asm/msr.h>
  53
  54#define INTEL_IDLE_VERSION "0.5.1"
  55
  56static struct cpuidle_driver intel_idle_driver = {
  57	.name = "intel_idle",
  58	.owner = THIS_MODULE,
  59};
  60/* intel_idle.max_cstate=0 disables driver */
  61static int max_cstate = CPUIDLE_STATE_MAX - 1;
  62static unsigned int disabled_states_mask;
  63
  64static struct cpuidle_device __percpu *intel_idle_cpuidle_devices;
  65
  66static unsigned long auto_demotion_disable_flags;
  67static bool disable_promotion_to_c1e;
  68
  69static bool lapic_timer_always_reliable;
  70
  71struct idle_cpu {
  72	struct cpuidle_state *state_table;
  73
  74	/*
  75	 * Hardware C-state auto-demotion may not always be optimal.
  76	 * Indicate which enable bits to clear here.
  77	 */
  78	unsigned long auto_demotion_disable_flags;
  79	bool byt_auto_demotion_disable_flag;
  80	bool disable_promotion_to_c1e;
  81	bool use_acpi;
  82};
  83
  84static const struct idle_cpu *icpu __initdata;
  85static struct cpuidle_state *cpuidle_state_table __initdata;
  86
  87static unsigned int mwait_substates __initdata;
  88
  89/*
  90 * Enable this state by default even if the ACPI _CST does not list it.
  91 */
  92#define CPUIDLE_FLAG_ALWAYS_ENABLE	BIT(15)
  93
  94/*
  95 * Set this flag for states where the HW flushes the TLB for us
  96 * and so we don't need cross-calls to keep it consistent.
  97 * If this flag is set, SW flushes the TLB, so even if the
  98 * HW doesn't do the flushing, this flag is safe to use.
  99 */
 100#define CPUIDLE_FLAG_TLB_FLUSHED	BIT(16)
 101
 102/*
 103 * MWAIT takes an 8-bit "hint" in EAX "suggesting"
 104 * the C-state (top nibble) and sub-state (bottom nibble)
 105 * 0x00 means "MWAIT(C1)", 0x10 means "MWAIT(C2)" etc.
 106 *
 107 * We store the hint at the top of our "flags" for each state.
 108 */
 109#define flg2MWAIT(flags) (((flags) >> 24) & 0xFF)
 110#define MWAIT2flg(eax) ((eax & 0xFF) << 24)
 111
 112/**
 113 * intel_idle - Ask the processor to enter the given idle state.
 114 * @dev: cpuidle device of the target CPU.
 115 * @drv: cpuidle driver (assumed to point to intel_idle_driver).
 116 * @index: Target idle state index.
 117 *
 118 * Use the MWAIT instruction to notify the processor that the CPU represented by
 119 * @dev is idle and it can try to enter the idle state corresponding to @index.
 120 *
 121 * If the local APIC timer is not known to be reliable in the target idle state,
 122 * enable one-shot tick broadcasting for the target CPU before executing MWAIT.
 123 *
 124 * Optionally call leave_mm() for the target CPU upfront to avoid wakeups due to
 125 * flushing user TLBs.
 126 *
 127 * Must be called under local_irq_disable().
 128 */
 129static __cpuidle int intel_idle(struct cpuidle_device *dev,
 130				struct cpuidle_driver *drv, int index)
 131{
 132	struct cpuidle_state *state = &drv->states[index];
 133	unsigned long eax = flg2MWAIT(state->flags);
 134	unsigned long ecx = 1; /* break on interrupt flag */
 135	bool uninitialized_var(tick);
 136	int cpu = smp_processor_id();
 137
 138	/*
 139	 * leave_mm() to avoid costly and often unnecessary wakeups
 140	 * for flushing the user TLB's associated with the active mm.
 141	 */
 142	if (state->flags & CPUIDLE_FLAG_TLB_FLUSHED)
 143		leave_mm(cpu);
 144
 145	if (!static_cpu_has(X86_FEATURE_ARAT) && !lapic_timer_always_reliable) {
 146		/*
 147		 * Switch over to one-shot tick broadcast if the target C-state
 148		 * is deeper than C1.
 149		 */
 150		if ((eax >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK) {
 151			tick = true;
 152			tick_broadcast_enter();
 153		} else {
 154			tick = false;
 155		}
 156	}
 157
 158	mwait_idle_with_hints(eax, ecx);
 159
 160	if (!static_cpu_has(X86_FEATURE_ARAT) && tick)
 161		tick_broadcast_exit();
 162
 163	return index;
 164}
 165
 166/**
 167 * intel_idle_s2idle - Ask the processor to enter the given idle state.
 168 * @dev: cpuidle device of the target CPU.
 169 * @drv: cpuidle driver (assumed to point to intel_idle_driver).
 170 * @index: Target idle state index.
 171 *
 172 * Use the MWAIT instruction to notify the processor that the CPU represented by
 173 * @dev is idle and it can try to enter the idle state corresponding to @index.
 174 *
 175 * Invoked as a suspend-to-idle callback routine with frozen user space, frozen
 176 * scheduler tick and suspended scheduler clock on the target CPU.
 177 */
 178static __cpuidle void intel_idle_s2idle(struct cpuidle_device *dev,
 179					struct cpuidle_driver *drv, int index)
 180{
 181	unsigned long eax = flg2MWAIT(drv->states[index].flags);
 182	unsigned long ecx = 1; /* break on interrupt flag */
 183
 184	mwait_idle_with_hints(eax, ecx);
 185}
 186
 187/*
 188 * States are indexed by the cstate number,
 189 * which is also the index into the MWAIT hint array.
 190 * Thus C0 is a dummy.
 191 */
 192static struct cpuidle_state nehalem_cstates[] __initdata = {
 193	{
 194		.name = "C1",
 195		.desc = "MWAIT 0x00",
 196		.flags = MWAIT2flg(0x00),
 197		.exit_latency = 3,
 198		.target_residency = 6,
 199		.enter = &intel_idle,
 200		.enter_s2idle = intel_idle_s2idle, },
 201	{
 202		.name = "C1E",
 203		.desc = "MWAIT 0x01",
 204		.flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
 205		.exit_latency = 10,
 206		.target_residency = 20,
 207		.enter = &intel_idle,
 208		.enter_s2idle = intel_idle_s2idle, },
 209	{
 210		.name = "C3",
 211		.desc = "MWAIT 0x10",
 212		.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
 213		.exit_latency = 20,
 214		.target_residency = 80,
 215		.enter = &intel_idle,
 216		.enter_s2idle = intel_idle_s2idle, },
 217	{
 218		.name = "C6",
 219		.desc = "MWAIT 0x20",
 220		.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
 221		.exit_latency = 200,
 222		.target_residency = 800,
 223		.enter = &intel_idle,
 224		.enter_s2idle = intel_idle_s2idle, },
 225	{
 226		.enter = NULL }
 227};
 228
 229static struct cpuidle_state snb_cstates[] __initdata = {
 230	{
 231		.name = "C1",
 232		.desc = "MWAIT 0x00",
 233		.flags = MWAIT2flg(0x00),
 234		.exit_latency = 2,
 235		.target_residency = 2,
 236		.enter = &intel_idle,
 237		.enter_s2idle = intel_idle_s2idle, },
 238	{
 239		.name = "C1E",
 240		.desc = "MWAIT 0x01",
 241		.flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
 242		.exit_latency = 10,
 243		.target_residency = 20,
 244		.enter = &intel_idle,
 245		.enter_s2idle = intel_idle_s2idle, },
 246	{
 247		.name = "C3",
 248		.desc = "MWAIT 0x10",
 249		.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
 250		.exit_latency = 80,
 251		.target_residency = 211,
 252		.enter = &intel_idle,
 253		.enter_s2idle = intel_idle_s2idle, },
 254	{
 255		.name = "C6",
 256		.desc = "MWAIT 0x20",
 257		.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
 258		.exit_latency = 104,
 259		.target_residency = 345,
 260		.enter = &intel_idle,
 261		.enter_s2idle = intel_idle_s2idle, },
 262	{
 263		.name = "C7",
 264		.desc = "MWAIT 0x30",
 265		.flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
 266		.exit_latency = 109,
 267		.target_residency = 345,
 268		.enter = &intel_idle,
 269		.enter_s2idle = intel_idle_s2idle, },
 270	{
 271		.enter = NULL }
 272};
 273
 274static struct cpuidle_state byt_cstates[] __initdata = {
 275	{
 276		.name = "C1",
 277		.desc = "MWAIT 0x00",
 278		.flags = MWAIT2flg(0x00),
 279		.exit_latency = 1,
 280		.target_residency = 1,
 281		.enter = &intel_idle,
 282		.enter_s2idle = intel_idle_s2idle, },
 283	{
 284		.name = "C6N",
 285		.desc = "MWAIT 0x58",
 286		.flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED,
 287		.exit_latency = 300,
 288		.target_residency = 275,
 289		.enter = &intel_idle,
 290		.enter_s2idle = intel_idle_s2idle, },
 291	{
 292		.name = "C6S",
 293		.desc = "MWAIT 0x52",
 294		.flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
 295		.exit_latency = 500,
 296		.target_residency = 560,
 297		.enter = &intel_idle,
 298		.enter_s2idle = intel_idle_s2idle, },
 299	{
 300		.name = "C7",
 301		.desc = "MWAIT 0x60",
 302		.flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
 303		.exit_latency = 1200,
 304		.target_residency = 4000,
 305		.enter = &intel_idle,
 306		.enter_s2idle = intel_idle_s2idle, },
 307	{
 308		.name = "C7S",
 309		.desc = "MWAIT 0x64",
 310		.flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED,
 311		.exit_latency = 10000,
 312		.target_residency = 20000,
 313		.enter = &intel_idle,
 314		.enter_s2idle = intel_idle_s2idle, },
 315	{
 316		.enter = NULL }
 317};
 318
 319static struct cpuidle_state cht_cstates[] __initdata = {
 320	{
 321		.name = "C1",
 322		.desc = "MWAIT 0x00",
 323		.flags = MWAIT2flg(0x00),
 324		.exit_latency = 1,
 325		.target_residency = 1,
 326		.enter = &intel_idle,
 327		.enter_s2idle = intel_idle_s2idle, },
 328	{
 329		.name = "C6N",
 330		.desc = "MWAIT 0x58",
 331		.flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED,
 332		.exit_latency = 80,
 333		.target_residency = 275,
 334		.enter = &intel_idle,
 335		.enter_s2idle = intel_idle_s2idle, },
 336	{
 337		.name = "C6S",
 338		.desc = "MWAIT 0x52",
 339		.flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
 340		.exit_latency = 200,
 341		.target_residency = 560,
 342		.enter = &intel_idle,
 343		.enter_s2idle = intel_idle_s2idle, },
 344	{
 345		.name = "C7",
 346		.desc = "MWAIT 0x60",
 347		.flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
 348		.exit_latency = 1200,
 349		.target_residency = 4000,
 350		.enter = &intel_idle,
 351		.enter_s2idle = intel_idle_s2idle, },
 352	{
 353		.name = "C7S",
 354		.desc = "MWAIT 0x64",
 355		.flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED,
 356		.exit_latency = 10000,
 357		.target_residency = 20000,
 358		.enter = &intel_idle,
 359		.enter_s2idle = intel_idle_s2idle, },
 360	{
 361		.enter = NULL }
 362};
 363
 364static struct cpuidle_state ivb_cstates[] __initdata = {
 365	{
 366		.name = "C1",
 367		.desc = "MWAIT 0x00",
 368		.flags = MWAIT2flg(0x00),
 369		.exit_latency = 1,
 370		.target_residency = 1,
 371		.enter = &intel_idle,
 372		.enter_s2idle = intel_idle_s2idle, },
 373	{
 374		.name = "C1E",
 375		.desc = "MWAIT 0x01",
 376		.flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
 377		.exit_latency = 10,
 378		.target_residency = 20,
 379		.enter = &intel_idle,
 380		.enter_s2idle = intel_idle_s2idle, },
 381	{
 382		.name = "C3",
 383		.desc = "MWAIT 0x10",
 384		.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
 385		.exit_latency = 59,
 386		.target_residency = 156,
 387		.enter = &intel_idle,
 388		.enter_s2idle = intel_idle_s2idle, },
 389	{
 390		.name = "C6",
 391		.desc = "MWAIT 0x20",
 392		.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
 393		.exit_latency = 80,
 394		.target_residency = 300,
 395		.enter = &intel_idle,
 396		.enter_s2idle = intel_idle_s2idle, },
 397	{
 398		.name = "C7",
 399		.desc = "MWAIT 0x30",
 400		.flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
 401		.exit_latency = 87,
 402		.target_residency = 300,
 403		.enter = &intel_idle,
 404		.enter_s2idle = intel_idle_s2idle, },
 405	{
 406		.enter = NULL }
 407};
 408
 409static struct cpuidle_state ivt_cstates[] __initdata = {
 410	{
 411		.name = "C1",
 412		.desc = "MWAIT 0x00",
 413		.flags = MWAIT2flg(0x00),
 414		.exit_latency = 1,
 415		.target_residency = 1,
 416		.enter = &intel_idle,
 417		.enter_s2idle = intel_idle_s2idle, },
 418	{
 419		.name = "C1E",
 420		.desc = "MWAIT 0x01",
 421		.flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
 422		.exit_latency = 10,
 423		.target_residency = 80,
 424		.enter = &intel_idle,
 425		.enter_s2idle = intel_idle_s2idle, },
 426	{
 427		.name = "C3",
 428		.desc = "MWAIT 0x10",
 429		.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
 430		.exit_latency = 59,
 431		.target_residency = 156,
 432		.enter = &intel_idle,
 433		.enter_s2idle = intel_idle_s2idle, },
 434	{
 435		.name = "C6",
 436		.desc = "MWAIT 0x20",
 437		.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
 438		.exit_latency = 82,
 439		.target_residency = 300,
 440		.enter = &intel_idle,
 441		.enter_s2idle = intel_idle_s2idle, },
 442	{
 443		.enter = NULL }
 444};
 445
 446static struct cpuidle_state ivt_cstates_4s[] __initdata = {
 447	{
 448		.name = "C1",
 449		.desc = "MWAIT 0x00",
 450		.flags = MWAIT2flg(0x00),
 451		.exit_latency = 1,
 452		.target_residency = 1,
 453		.enter = &intel_idle,
 454		.enter_s2idle = intel_idle_s2idle, },
 455	{
 456		.name = "C1E",
 457		.desc = "MWAIT 0x01",
 458		.flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
 459		.exit_latency = 10,
 460		.target_residency = 250,
 461		.enter = &intel_idle,
 462		.enter_s2idle = intel_idle_s2idle, },
 463	{
 464		.name = "C3",
 465		.desc = "MWAIT 0x10",
 466		.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
 467		.exit_latency = 59,
 468		.target_residency = 300,
 469		.enter = &intel_idle,
 470		.enter_s2idle = intel_idle_s2idle, },
 471	{
 472		.name = "C6",
 473		.desc = "MWAIT 0x20",
 474		.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
 475		.exit_latency = 84,
 476		.target_residency = 400,
 477		.enter = &intel_idle,
 478		.enter_s2idle = intel_idle_s2idle, },
 479	{
 480		.enter = NULL }
 481};
 482
 483static struct cpuidle_state ivt_cstates_8s[] __initdata = {
 484	{
 485		.name = "C1",
 486		.desc = "MWAIT 0x00",
 487		.flags = MWAIT2flg(0x00),
 488		.exit_latency = 1,
 489		.target_residency = 1,
 490		.enter = &intel_idle,
 491		.enter_s2idle = intel_idle_s2idle, },
 492	{
 493		.name = "C1E",
 494		.desc = "MWAIT 0x01",
 495		.flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
 496		.exit_latency = 10,
 497		.target_residency = 500,
 498		.enter = &intel_idle,
 499		.enter_s2idle = intel_idle_s2idle, },
 500	{
 501		.name = "C3",
 502		.desc = "MWAIT 0x10",
 503		.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
 504		.exit_latency = 59,
 505		.target_residency = 600,
 506		.enter = &intel_idle,
 507		.enter_s2idle = intel_idle_s2idle, },
 508	{
 509		.name = "C6",
 510		.desc = "MWAIT 0x20",
 511		.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
 512		.exit_latency = 88,
 513		.target_residency = 700,
 514		.enter = &intel_idle,
 515		.enter_s2idle = intel_idle_s2idle, },
 516	{
 517		.enter = NULL }
 518};
 519
 520static struct cpuidle_state hsw_cstates[] __initdata = {
 521	{
 522		.name = "C1",
 523		.desc = "MWAIT 0x00",
 524		.flags = MWAIT2flg(0x00),
 525		.exit_latency = 2,
 526		.target_residency = 2,
 527		.enter = &intel_idle,
 528		.enter_s2idle = intel_idle_s2idle, },
 529	{
 530		.name = "C1E",
 531		.desc = "MWAIT 0x01",
 532		.flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
 533		.exit_latency = 10,
 534		.target_residency = 20,
 535		.enter = &intel_idle,
 536		.enter_s2idle = intel_idle_s2idle, },
 537	{
 538		.name = "C3",
 539		.desc = "MWAIT 0x10",
 540		.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
 541		.exit_latency = 33,
 542		.target_residency = 100,
 543		.enter = &intel_idle,
 544		.enter_s2idle = intel_idle_s2idle, },
 545	{
 546		.name = "C6",
 547		.desc = "MWAIT 0x20",
 548		.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
 549		.exit_latency = 133,
 550		.target_residency = 400,
 551		.enter = &intel_idle,
 552		.enter_s2idle = intel_idle_s2idle, },
 553	{
 554		.name = "C7s",
 555		.desc = "MWAIT 0x32",
 556		.flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED,
 557		.exit_latency = 166,
 558		.target_residency = 500,
 559		.enter = &intel_idle,
 560		.enter_s2idle = intel_idle_s2idle, },
 561	{
 562		.name = "C8",
 563		.desc = "MWAIT 0x40",
 564		.flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
 565		.exit_latency = 300,
 566		.target_residency = 900,
 567		.enter = &intel_idle,
 568		.enter_s2idle = intel_idle_s2idle, },
 569	{
 570		.name = "C9",
 571		.desc = "MWAIT 0x50",
 572		.flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
 573		.exit_latency = 600,
 574		.target_residency = 1800,
 575		.enter = &intel_idle,
 576		.enter_s2idle = intel_idle_s2idle, },
 577	{
 578		.name = "C10",
 579		.desc = "MWAIT 0x60",
 580		.flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
 581		.exit_latency = 2600,
 582		.target_residency = 7700,
 583		.enter = &intel_idle,
 584		.enter_s2idle = intel_idle_s2idle, },
 585	{
 586		.enter = NULL }
 587};
 588static struct cpuidle_state bdw_cstates[] __initdata = {
 589	{
 590		.name = "C1",
 591		.desc = "MWAIT 0x00",
 592		.flags = MWAIT2flg(0x00),
 593		.exit_latency = 2,
 594		.target_residency = 2,
 595		.enter = &intel_idle,
 596		.enter_s2idle = intel_idle_s2idle, },
 597	{
 598		.name = "C1E",
 599		.desc = "MWAIT 0x01",
 600		.flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
 601		.exit_latency = 10,
 602		.target_residency = 20,
 603		.enter = &intel_idle,
 604		.enter_s2idle = intel_idle_s2idle, },
 605	{
 606		.name = "C3",
 607		.desc = "MWAIT 0x10",
 608		.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
 609		.exit_latency = 40,
 610		.target_residency = 100,
 611		.enter = &intel_idle,
 612		.enter_s2idle = intel_idle_s2idle, },
 613	{
 614		.name = "C6",
 615		.desc = "MWAIT 0x20",
 616		.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
 617		.exit_latency = 133,
 618		.target_residency = 400,
 619		.enter = &intel_idle,
 620		.enter_s2idle = intel_idle_s2idle, },
 621	{
 622		.name = "C7s",
 623		.desc = "MWAIT 0x32",
 624		.flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED,
 625		.exit_latency = 166,
 626		.target_residency = 500,
 627		.enter = &intel_idle,
 628		.enter_s2idle = intel_idle_s2idle, },
 629	{
 630		.name = "C8",
 631		.desc = "MWAIT 0x40",
 632		.flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
 633		.exit_latency = 300,
 634		.target_residency = 900,
 635		.enter = &intel_idle,
 636		.enter_s2idle = intel_idle_s2idle, },
 637	{
 638		.name = "C9",
 639		.desc = "MWAIT 0x50",
 640		.flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
 641		.exit_latency = 600,
 642		.target_residency = 1800,
 643		.enter = &intel_idle,
 644		.enter_s2idle = intel_idle_s2idle, },
 645	{
 646		.name = "C10",
 647		.desc = "MWAIT 0x60",
 648		.flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
 649		.exit_latency = 2600,
 650		.target_residency = 7700,
 651		.enter = &intel_idle,
 652		.enter_s2idle = intel_idle_s2idle, },
 653	{
 654		.enter = NULL }
 655};
 656
 657static struct cpuidle_state skl_cstates[] __initdata = {
 658	{
 659		.name = "C1",
 660		.desc = "MWAIT 0x00",
 661		.flags = MWAIT2flg(0x00),
 662		.exit_latency = 2,
 663		.target_residency = 2,
 664		.enter = &intel_idle,
 665		.enter_s2idle = intel_idle_s2idle, },
 666	{
 667		.name = "C1E",
 668		.desc = "MWAIT 0x01",
 669		.flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
 670		.exit_latency = 10,
 671		.target_residency = 20,
 672		.enter = &intel_idle,
 673		.enter_s2idle = intel_idle_s2idle, },
 674	{
 675		.name = "C3",
 676		.desc = "MWAIT 0x10",
 677		.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
 678		.exit_latency = 70,
 679		.target_residency = 100,
 680		.enter = &intel_idle,
 681		.enter_s2idle = intel_idle_s2idle, },
 682	{
 683		.name = "C6",
 684		.desc = "MWAIT 0x20",
 685		.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
 686		.exit_latency = 85,
 687		.target_residency = 200,
 688		.enter = &intel_idle,
 689		.enter_s2idle = intel_idle_s2idle, },
 690	{
 691		.name = "C7s",
 692		.desc = "MWAIT 0x33",
 693		.flags = MWAIT2flg(0x33) | CPUIDLE_FLAG_TLB_FLUSHED,
 694		.exit_latency = 124,
 695		.target_residency = 800,
 696		.enter = &intel_idle,
 697		.enter_s2idle = intel_idle_s2idle, },
 698	{
 699		.name = "C8",
 700		.desc = "MWAIT 0x40",
 701		.flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
 702		.exit_latency = 200,
 703		.target_residency = 800,
 704		.enter = &intel_idle,
 705		.enter_s2idle = intel_idle_s2idle, },
 706	{
 707		.name = "C9",
 708		.desc = "MWAIT 0x50",
 709		.flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
 710		.exit_latency = 480,
 711		.target_residency = 5000,
 712		.enter = &intel_idle,
 713		.enter_s2idle = intel_idle_s2idle, },
 714	{
 715		.name = "C10",
 716		.desc = "MWAIT 0x60",
 717		.flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
 718		.exit_latency = 890,
 719		.target_residency = 5000,
 720		.enter = &intel_idle,
 721		.enter_s2idle = intel_idle_s2idle, },
 722	{
 723		.enter = NULL }
 724};
 725
 726static struct cpuidle_state skx_cstates[] __initdata = {
 727	{
 728		.name = "C1",
 729		.desc = "MWAIT 0x00",
 730		.flags = MWAIT2flg(0x00),
 731		.exit_latency = 2,
 732		.target_residency = 2,
 733		.enter = &intel_idle,
 734		.enter_s2idle = intel_idle_s2idle, },
 735	{
 736		.name = "C1E",
 737		.desc = "MWAIT 0x01",
 738		.flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
 739		.exit_latency = 10,
 740		.target_residency = 20,
 741		.enter = &intel_idle,
 742		.enter_s2idle = intel_idle_s2idle, },
 743	{
 744		.name = "C6",
 745		.desc = "MWAIT 0x20",
 746		.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
 747		.exit_latency = 133,
 748		.target_residency = 600,
 749		.enter = &intel_idle,
 750		.enter_s2idle = intel_idle_s2idle, },
 751	{
 752		.enter = NULL }
 753};
 754
 755static struct cpuidle_state atom_cstates[] __initdata = {
 756	{
 757		.name = "C1E",
 758		.desc = "MWAIT 0x00",
 759		.flags = MWAIT2flg(0x00),
 760		.exit_latency = 10,
 761		.target_residency = 20,
 762		.enter = &intel_idle,
 763		.enter_s2idle = intel_idle_s2idle, },
 764	{
 765		.name = "C2",
 766		.desc = "MWAIT 0x10",
 767		.flags = MWAIT2flg(0x10),
 768		.exit_latency = 20,
 769		.target_residency = 80,
 770		.enter = &intel_idle,
 771		.enter_s2idle = intel_idle_s2idle, },
 772	{
 773		.name = "C4",
 774		.desc = "MWAIT 0x30",
 775		.flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
 776		.exit_latency = 100,
 777		.target_residency = 400,
 778		.enter = &intel_idle,
 779		.enter_s2idle = intel_idle_s2idle, },
 780	{
 781		.name = "C6",
 782		.desc = "MWAIT 0x52",
 783		.flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
 784		.exit_latency = 140,
 785		.target_residency = 560,
 786		.enter = &intel_idle,
 787		.enter_s2idle = intel_idle_s2idle, },
 788	{
 789		.enter = NULL }
 790};
 791static struct cpuidle_state tangier_cstates[] __initdata = {
 792	{
 793		.name = "C1",
 794		.desc = "MWAIT 0x00",
 795		.flags = MWAIT2flg(0x00),
 796		.exit_latency = 1,
 797		.target_residency = 4,
 798		.enter = &intel_idle,
 799		.enter_s2idle = intel_idle_s2idle, },
 800	{
 801		.name = "C4",
 802		.desc = "MWAIT 0x30",
 803		.flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
 804		.exit_latency = 100,
 805		.target_residency = 400,
 806		.enter = &intel_idle,
 807		.enter_s2idle = intel_idle_s2idle, },
 808	{
 809		.name = "C6",
 810		.desc = "MWAIT 0x52",
 811		.flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
 812		.exit_latency = 140,
 813		.target_residency = 560,
 814		.enter = &intel_idle,
 815		.enter_s2idle = intel_idle_s2idle, },
 816	{
 817		.name = "C7",
 818		.desc = "MWAIT 0x60",
 819		.flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
 820		.exit_latency = 1200,
 821		.target_residency = 4000,
 822		.enter = &intel_idle,
 823		.enter_s2idle = intel_idle_s2idle, },
 824	{
 825		.name = "C9",
 826		.desc = "MWAIT 0x64",
 827		.flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED,
 828		.exit_latency = 10000,
 829		.target_residency = 20000,
 830		.enter = &intel_idle,
 831		.enter_s2idle = intel_idle_s2idle, },
 832	{
 833		.enter = NULL }
 834};
 835static struct cpuidle_state avn_cstates[] __initdata = {
 836	{
 837		.name = "C1",
 838		.desc = "MWAIT 0x00",
 839		.flags = MWAIT2flg(0x00),
 840		.exit_latency = 2,
 841		.target_residency = 2,
 842		.enter = &intel_idle,
 843		.enter_s2idle = intel_idle_s2idle, },
 844	{
 845		.name = "C6",
 846		.desc = "MWAIT 0x51",
 847		.flags = MWAIT2flg(0x51) | CPUIDLE_FLAG_TLB_FLUSHED,
 848		.exit_latency = 15,
 849		.target_residency = 45,
 850		.enter = &intel_idle,
 851		.enter_s2idle = intel_idle_s2idle, },
 852	{
 853		.enter = NULL }
 854};
 855static struct cpuidle_state knl_cstates[] __initdata = {
 856	{
 857		.name = "C1",
 858		.desc = "MWAIT 0x00",
 859		.flags = MWAIT2flg(0x00),
 860		.exit_latency = 1,
 861		.target_residency = 2,
 862		.enter = &intel_idle,
 863		.enter_s2idle = intel_idle_s2idle },
 864	{
 865		.name = "C6",
 866		.desc = "MWAIT 0x10",
 867		.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
 868		.exit_latency = 120,
 869		.target_residency = 500,
 870		.enter = &intel_idle,
 871		.enter_s2idle = intel_idle_s2idle },
 872	{
 873		.enter = NULL }
 874};
 875
 876static struct cpuidle_state bxt_cstates[] __initdata = {
 877	{
 878		.name = "C1",
 879		.desc = "MWAIT 0x00",
 880		.flags = MWAIT2flg(0x00),
 881		.exit_latency = 2,
 882		.target_residency = 2,
 883		.enter = &intel_idle,
 884		.enter_s2idle = intel_idle_s2idle, },
 885	{
 886		.name = "C1E",
 887		.desc = "MWAIT 0x01",
 888		.flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
 889		.exit_latency = 10,
 890		.target_residency = 20,
 891		.enter = &intel_idle,
 892		.enter_s2idle = intel_idle_s2idle, },
 893	{
 894		.name = "C6",
 895		.desc = "MWAIT 0x20",
 896		.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
 897		.exit_latency = 133,
 898		.target_residency = 133,
 899		.enter = &intel_idle,
 900		.enter_s2idle = intel_idle_s2idle, },
 901	{
 902		.name = "C7s",
 903		.desc = "MWAIT 0x31",
 904		.flags = MWAIT2flg(0x31) | CPUIDLE_FLAG_TLB_FLUSHED,
 905		.exit_latency = 155,
 906		.target_residency = 155,
 907		.enter = &intel_idle,
 908		.enter_s2idle = intel_idle_s2idle, },
 909	{
 910		.name = "C8",
 911		.desc = "MWAIT 0x40",
 912		.flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
 913		.exit_latency = 1000,
 914		.target_residency = 1000,
 915		.enter = &intel_idle,
 916		.enter_s2idle = intel_idle_s2idle, },
 917	{
 918		.name = "C9",
 919		.desc = "MWAIT 0x50",
 920		.flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
 921		.exit_latency = 2000,
 922		.target_residency = 2000,
 923		.enter = &intel_idle,
 924		.enter_s2idle = intel_idle_s2idle, },
 925	{
 926		.name = "C10",
 927		.desc = "MWAIT 0x60",
 928		.flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
 929		.exit_latency = 10000,
 930		.target_residency = 10000,
 931		.enter = &intel_idle,
 932		.enter_s2idle = intel_idle_s2idle, },
 933	{
 934		.enter = NULL }
 935};
 936
 937static struct cpuidle_state dnv_cstates[] __initdata = {
 938	{
 939		.name = "C1",
 940		.desc = "MWAIT 0x00",
 941		.flags = MWAIT2flg(0x00),
 942		.exit_latency = 2,
 943		.target_residency = 2,
 944		.enter = &intel_idle,
 945		.enter_s2idle = intel_idle_s2idle, },
 946	{
 947		.name = "C1E",
 948		.desc = "MWAIT 0x01",
 949		.flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
 950		.exit_latency = 10,
 951		.target_residency = 20,
 952		.enter = &intel_idle,
 953		.enter_s2idle = intel_idle_s2idle, },
 954	{
 955		.name = "C6",
 956		.desc = "MWAIT 0x20",
 957		.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
 958		.exit_latency = 50,
 959		.target_residency = 500,
 960		.enter = &intel_idle,
 961		.enter_s2idle = intel_idle_s2idle, },
 962	{
 963		.enter = NULL }
 964};
 965
 966static const struct idle_cpu idle_cpu_nehalem __initconst = {
 967	.state_table = nehalem_cstates,
 968	.auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE,
 969	.disable_promotion_to_c1e = true,
 970};
 971
 972static const struct idle_cpu idle_cpu_nhx __initconst = {
 973	.state_table = nehalem_cstates,
 974	.auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE,
 975	.disable_promotion_to_c1e = true,
 976	.use_acpi = true,
 977};
 978
 979static const struct idle_cpu idle_cpu_atom __initconst = {
 980	.state_table = atom_cstates,
 981};
 982
 983static const struct idle_cpu idle_cpu_tangier __initconst = {
 984	.state_table = tangier_cstates,
 985};
 986
 987static const struct idle_cpu idle_cpu_lincroft __initconst = {
 988	.state_table = atom_cstates,
 989	.auto_demotion_disable_flags = ATM_LNC_C6_AUTO_DEMOTE,
 990};
 991
 992static const struct idle_cpu idle_cpu_snb __initconst = {
 993	.state_table = snb_cstates,
 994	.disable_promotion_to_c1e = true,
 995};
 996
 997static const struct idle_cpu idle_cpu_snx __initconst = {
 998	.state_table = snb_cstates,
 999	.disable_promotion_to_c1e = true,
1000	.use_acpi = true,
1001};
1002
1003static const struct idle_cpu idle_cpu_byt __initconst = {
1004	.state_table = byt_cstates,
1005	.disable_promotion_to_c1e = true,
1006	.byt_auto_demotion_disable_flag = true,
1007};
1008
1009static const struct idle_cpu idle_cpu_cht __initconst = {
1010	.state_table = cht_cstates,
1011	.disable_promotion_to_c1e = true,
1012	.byt_auto_demotion_disable_flag = true,
1013};
1014
1015static const struct idle_cpu idle_cpu_ivb __initconst = {
1016	.state_table = ivb_cstates,
1017	.disable_promotion_to_c1e = true,
1018};
1019
1020static const struct idle_cpu idle_cpu_ivt __initconst = {
1021	.state_table = ivt_cstates,
1022	.disable_promotion_to_c1e = true,
1023	.use_acpi = true,
1024};
1025
1026static const struct idle_cpu idle_cpu_hsw __initconst = {
1027	.state_table = hsw_cstates,
1028	.disable_promotion_to_c1e = true,
1029};
1030
1031static const struct idle_cpu idle_cpu_hsx __initconst = {
1032	.state_table = hsw_cstates,
1033	.disable_promotion_to_c1e = true,
1034	.use_acpi = true,
1035};
1036
1037static const struct idle_cpu idle_cpu_bdw __initconst = {
1038	.state_table = bdw_cstates,
1039	.disable_promotion_to_c1e = true,
1040};
1041
1042static const struct idle_cpu idle_cpu_bdx __initconst = {
1043	.state_table = bdw_cstates,
1044	.disable_promotion_to_c1e = true,
1045	.use_acpi = true,
1046};
1047
1048static const struct idle_cpu idle_cpu_skl __initconst = {
1049	.state_table = skl_cstates,
1050	.disable_promotion_to_c1e = true,
1051};
1052
1053static const struct idle_cpu idle_cpu_skx __initconst = {
1054	.state_table = skx_cstates,
1055	.disable_promotion_to_c1e = true,
1056	.use_acpi = true,
1057};
1058
1059static const struct idle_cpu idle_cpu_avn __initconst = {
1060	.state_table = avn_cstates,
1061	.disable_promotion_to_c1e = true,
1062	.use_acpi = true,
1063};
1064
1065static const struct idle_cpu idle_cpu_knl __initconst = {
1066	.state_table = knl_cstates,
1067	.use_acpi = true,
1068};
1069
1070static const struct idle_cpu idle_cpu_bxt __initconst = {
1071	.state_table = bxt_cstates,
1072	.disable_promotion_to_c1e = true,
1073};
1074
1075static const struct idle_cpu idle_cpu_dnv __initconst = {
1076	.state_table = dnv_cstates,
1077	.disable_promotion_to_c1e = true,
1078	.use_acpi = true,
1079};
1080
1081static const struct x86_cpu_id intel_idle_ids[] __initconst = {
1082	X86_MATCH_INTEL_FAM6_MODEL(NEHALEM_EP,		&idle_cpu_nhx),
1083	X86_MATCH_INTEL_FAM6_MODEL(NEHALEM,		&idle_cpu_nehalem),
1084	X86_MATCH_INTEL_FAM6_MODEL(NEHALEM_G,		&idle_cpu_nehalem),
1085	X86_MATCH_INTEL_FAM6_MODEL(WESTMERE,		&idle_cpu_nehalem),
1086	X86_MATCH_INTEL_FAM6_MODEL(WESTMERE_EP,		&idle_cpu_nhx),
1087	X86_MATCH_INTEL_FAM6_MODEL(NEHALEM_EX,		&idle_cpu_nhx),
1088	X86_MATCH_INTEL_FAM6_MODEL(ATOM_BONNELL,	&idle_cpu_atom),
1089	X86_MATCH_INTEL_FAM6_MODEL(ATOM_BONNELL_MID,	&idle_cpu_lincroft),
1090	X86_MATCH_INTEL_FAM6_MODEL(WESTMERE_EX,		&idle_cpu_nhx),
1091	X86_MATCH_INTEL_FAM6_MODEL(SANDYBRIDGE,		&idle_cpu_snb),
1092	X86_MATCH_INTEL_FAM6_MODEL(SANDYBRIDGE_X,	&idle_cpu_snx),
1093	X86_MATCH_INTEL_FAM6_MODEL(ATOM_SALTWELL,	&idle_cpu_atom),
1094	X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT,	&idle_cpu_byt),
1095	X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT_MID,	&idle_cpu_tangier),
1096	X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT,	&idle_cpu_cht),
1097	X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE,		&idle_cpu_ivb),
1098	X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE_X,		&idle_cpu_ivt),
1099	X86_MATCH_INTEL_FAM6_MODEL(HASWELL,		&idle_cpu_hsw),
1100	X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X,		&idle_cpu_hsx),
1101	X86_MATCH_INTEL_FAM6_MODEL(HASWELL_L,		&idle_cpu_hsw),
1102	X86_MATCH_INTEL_FAM6_MODEL(HASWELL_G,		&idle_cpu_hsw),
1103	X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT_D,	&idle_cpu_avn),
1104	X86_MATCH_INTEL_FAM6_MODEL(BROADWELL,		&idle_cpu_bdw),
1105	X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_G,		&idle_cpu_bdw),
1106	X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X,		&idle_cpu_bdx),
1107	X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_D,		&idle_cpu_bdx),
1108	X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_L,		&idle_cpu_skl),
1109	X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE,		&idle_cpu_skl),
1110	X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE_L,		&idle_cpu_skl),
1111	X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE,		&idle_cpu_skl),
1112	X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_X,		&idle_cpu_skx),
1113	X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNL,	&idle_cpu_knl),
1114	X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNM,	&idle_cpu_knl),
1115	X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT,	&idle_cpu_bxt),
1116	X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_PLUS,	&idle_cpu_bxt),
1117	X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_D,	&idle_cpu_dnv),
1118	X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D,	&idle_cpu_dnv),
1119	{}
1120};
1121
1122static const struct x86_cpu_id intel_mwait_ids[] __initconst = {
1123	X86_MATCH_VENDOR_FAM_FEATURE(INTEL, 6, X86_FEATURE_MWAIT, NULL),
1124	{}
1125};
1126
1127static bool __init intel_idle_max_cstate_reached(int cstate)
1128{
1129	if (cstate + 1 > max_cstate) {
1130		pr_info("max_cstate %d reached\n", max_cstate);
1131		return true;
1132	}
1133	return false;
1134}
1135
1136#ifdef CONFIG_ACPI_PROCESSOR_CSTATE
1137#include <acpi/processor.h>
1138
1139static bool no_acpi __read_mostly;
1140module_param(no_acpi, bool, 0444);
1141MODULE_PARM_DESC(no_acpi, "Do not use ACPI _CST for building the idle states list");
1142
1143static bool force_use_acpi __read_mostly; /* No effect if no_acpi is set. */
1144module_param_named(use_acpi, force_use_acpi, bool, 0444);
1145MODULE_PARM_DESC(use_acpi, "Use ACPI _CST for building the idle states list");
1146
1147static struct acpi_processor_power acpi_state_table __initdata;
1148
1149/**
1150 * intel_idle_cst_usable - Check if the _CST information can be used.
1151 *
1152 * Check if all of the C-states listed by _CST in the max_cstate range are
1153 * ACPI_CSTATE_FFH, which means that they should be entered via MWAIT.
1154 */
1155static bool __init intel_idle_cst_usable(void)
1156{
1157	int cstate, limit;
1158
1159	limit = min_t(int, min_t(int, CPUIDLE_STATE_MAX, max_cstate + 1),
1160		      acpi_state_table.count);
1161
1162	for (cstate = 1; cstate < limit; cstate++) {
1163		struct acpi_processor_cx *cx = &acpi_state_table.states[cstate];
1164
1165		if (cx->entry_method != ACPI_CSTATE_FFH)
1166			return false;
1167	}
1168
1169	return true;
1170}
1171
1172static bool __init intel_idle_acpi_cst_extract(void)
1173{
1174	unsigned int cpu;
1175
1176	if (no_acpi) {
1177		pr_debug("Not allowed to use ACPI _CST\n");
1178		return false;
1179	}
1180
1181	for_each_possible_cpu(cpu) {
1182		struct acpi_processor *pr = per_cpu(processors, cpu);
1183
1184		if (!pr)
1185			continue;
1186
1187		if (acpi_processor_evaluate_cst(pr->handle, cpu, &acpi_state_table))
1188			continue;
1189
1190		acpi_state_table.count++;
1191
1192		if (!intel_idle_cst_usable())
1193			continue;
1194
1195		if (!acpi_processor_claim_cst_control()) {
1196			acpi_state_table.count = 0;
1197			return false;
1198		}
1199
1200		return true;
1201	}
1202
1203	pr_debug("ACPI _CST not found or not usable\n");
1204	return false;
1205}
1206
1207static void __init intel_idle_init_cstates_acpi(struct cpuidle_driver *drv)
1208{
1209	int cstate, limit = min_t(int, CPUIDLE_STATE_MAX, acpi_state_table.count);
1210
1211	/*
1212	 * If limit > 0, intel_idle_cst_usable() has returned 'true', so all of
1213	 * the interesting states are ACPI_CSTATE_FFH.
1214	 */
1215	for (cstate = 1; cstate < limit; cstate++) {
1216		struct acpi_processor_cx *cx;
1217		struct cpuidle_state *state;
1218
1219		if (intel_idle_max_cstate_reached(cstate))
1220			break;
1221
1222		cx = &acpi_state_table.states[cstate];
1223
1224		state = &drv->states[drv->state_count++];
1225
1226		snprintf(state->name, CPUIDLE_NAME_LEN, "C%d_ACPI", cstate);
1227		strlcpy(state->desc, cx->desc, CPUIDLE_DESC_LEN);
1228		state->exit_latency = cx->latency;
1229		/*
1230		 * For C1-type C-states use the same number for both the exit
1231		 * latency and target residency, because that is the case for
1232		 * C1 in the majority of the static C-states tables above.
1233		 * For the other types of C-states, however, set the target
1234		 * residency to 3 times the exit latency which should lead to
1235		 * a reasonable balance between energy-efficiency and
1236		 * performance in the majority of interesting cases.
1237		 */
1238		state->target_residency = cx->latency;
1239		if (cx->type > ACPI_STATE_C1)
1240			state->target_residency *= 3;
1241
1242		state->flags = MWAIT2flg(cx->address);
1243		if (cx->type > ACPI_STATE_C2)
1244			state->flags |= CPUIDLE_FLAG_TLB_FLUSHED;
1245
1246		if (disabled_states_mask & BIT(cstate))
1247			state->flags |= CPUIDLE_FLAG_OFF;
1248
1249		state->enter = intel_idle;
1250		state->enter_s2idle = intel_idle_s2idle;
1251	}
1252}
1253
1254static bool __init intel_idle_off_by_default(u32 mwait_hint)
1255{
1256	int cstate, limit;
1257
1258	/*
1259	 * If there are no _CST C-states, do not disable any C-states by
1260	 * default.
1261	 */
1262	if (!acpi_state_table.count)
1263		return false;
1264
1265	limit = min_t(int, CPUIDLE_STATE_MAX, acpi_state_table.count);
1266	/*
1267	 * If limit > 0, intel_idle_cst_usable() has returned 'true', so all of
1268	 * the interesting states are ACPI_CSTATE_FFH.
1269	 */
1270	for (cstate = 1; cstate < limit; cstate++) {
1271		if (acpi_state_table.states[cstate].address == mwait_hint)
1272			return false;
1273	}
1274	return true;
1275}
1276#else /* !CONFIG_ACPI_PROCESSOR_CSTATE */
1277#define force_use_acpi	(false)
1278
1279static inline bool intel_idle_acpi_cst_extract(void) { return false; }
1280static inline void intel_idle_init_cstates_acpi(struct cpuidle_driver *drv) { }
1281static inline bool intel_idle_off_by_default(u32 mwait_hint) { return false; }
1282#endif /* !CONFIG_ACPI_PROCESSOR_CSTATE */
1283
1284/**
1285 * ivt_idle_state_table_update - Tune the idle states table for Ivy Town.
1286 *
1287 * Tune IVT multi-socket targets.
1288 * Assumption: num_sockets == (max_package_num + 1).
1289 */
1290static void __init ivt_idle_state_table_update(void)
1291{
1292	/* IVT uses a different table for 1-2, 3-4, and > 4 sockets */
1293	int cpu, package_num, num_sockets = 1;
1294
1295	for_each_online_cpu(cpu) {
1296		package_num = topology_physical_package_id(cpu);
1297		if (package_num + 1 > num_sockets) {
1298			num_sockets = package_num + 1;
1299
1300			if (num_sockets > 4) {
1301				cpuidle_state_table = ivt_cstates_8s;
1302				return;
1303			}
1304		}
1305	}
1306
1307	if (num_sockets > 2)
1308		cpuidle_state_table = ivt_cstates_4s;
1309
1310	/* else, 1 and 2 socket systems use default ivt_cstates */
1311}
1312
1313/**
1314 * irtl_2_usec - IRTL to microseconds conversion.
1315 * @irtl: IRTL MSR value.
1316 *
1317 * Translate the IRTL (Interrupt Response Time Limit) MSR value to microseconds.
1318 */
1319static unsigned long long __init irtl_2_usec(unsigned long long irtl)
1320{
1321	static const unsigned int irtl_ns_units[] __initconst = {
1322		1, 32, 1024, 32768, 1048576, 33554432, 0, 0
1323	};
1324	unsigned long long ns;
1325
1326	if (!irtl)
1327		return 0;
1328
1329	ns = irtl_ns_units[(irtl >> 10) & 0x7];
1330
1331	return div_u64((irtl & 0x3FF) * ns, NSEC_PER_USEC);
1332}
1333
1334/**
1335 * bxt_idle_state_table_update - Fix up the Broxton idle states table.
1336 *
1337 * On BXT, trust the IRTL (Interrupt Response Time Limit) MSR to show the
1338 * definitive maximum latency and use the same value for target_residency.
1339 */
1340static void __init bxt_idle_state_table_update(void)
1341{
1342	unsigned long long msr;
1343	unsigned int usec;
1344
1345	rdmsrl(MSR_PKGC6_IRTL, msr);
1346	usec = irtl_2_usec(msr);
1347	if (usec) {
1348		bxt_cstates[2].exit_latency = usec;
1349		bxt_cstates[2].target_residency = usec;
1350	}
1351
1352	rdmsrl(MSR_PKGC7_IRTL, msr);
1353	usec = irtl_2_usec(msr);
1354	if (usec) {
1355		bxt_cstates[3].exit_latency = usec;
1356		bxt_cstates[3].target_residency = usec;
1357	}
1358
1359	rdmsrl(MSR_PKGC8_IRTL, msr);
1360	usec = irtl_2_usec(msr);
1361	if (usec) {
1362		bxt_cstates[4].exit_latency = usec;
1363		bxt_cstates[4].target_residency = usec;
1364	}
1365
1366	rdmsrl(MSR_PKGC9_IRTL, msr);
1367	usec = irtl_2_usec(msr);
1368	if (usec) {
1369		bxt_cstates[5].exit_latency = usec;
1370		bxt_cstates[5].target_residency = usec;
1371	}
1372
1373	rdmsrl(MSR_PKGC10_IRTL, msr);
1374	usec = irtl_2_usec(msr);
1375	if (usec) {
1376		bxt_cstates[6].exit_latency = usec;
1377		bxt_cstates[6].target_residency = usec;
1378	}
1379
1380}
1381
1382/**
1383 * sklh_idle_state_table_update - Fix up the Sky Lake idle states table.
1384 *
1385 * On SKL-H (model 0x5e) skip C8 and C9 if C10 is enabled and SGX disabled.
1386 */
1387static void __init sklh_idle_state_table_update(void)
1388{
1389	unsigned long long msr;
1390	unsigned int eax, ebx, ecx, edx;
1391
1392
1393	/* if PC10 disabled via cmdline intel_idle.max_cstate=7 or shallower */
1394	if (max_cstate <= 7)
1395		return;
1396
1397	/* if PC10 not present in CPUID.MWAIT.EDX */
1398	if ((mwait_substates & (0xF << 28)) == 0)
1399		return;
1400
1401	rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr);
1402
1403	/* PC10 is not enabled in PKG C-state limit */
1404	if ((msr & 0xF) != 8)
1405		return;
1406
1407	ecx = 0;
1408	cpuid(7, &eax, &ebx, &ecx, &edx);
1409
1410	/* if SGX is present */
1411	if (ebx & (1 << 2)) {
1412
1413		rdmsrl(MSR_IA32_FEAT_CTL, msr);
1414
1415		/* if SGX is enabled */
1416		if (msr & (1 << 18))
1417			return;
1418	}
1419
1420	skl_cstates[5].flags |= CPUIDLE_FLAG_UNUSABLE;	/* C8-SKL */
1421	skl_cstates[6].flags |= CPUIDLE_FLAG_UNUSABLE;	/* C9-SKL */
1422}
1423
1424static bool __init intel_idle_verify_cstate(unsigned int mwait_hint)
1425{
1426	unsigned int mwait_cstate = MWAIT_HINT2CSTATE(mwait_hint) + 1;
1427	unsigned int num_substates = (mwait_substates >> mwait_cstate * 4) &
1428					MWAIT_SUBSTATE_MASK;
1429
1430	/* Ignore the C-state if there are NO sub-states in CPUID for it. */
1431	if (num_substates == 0)
1432		return false;
1433
1434	if (mwait_cstate > 2 && !boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
1435		mark_tsc_unstable("TSC halts in idle states deeper than C2");
1436
1437	return true;
1438}
1439
1440static void __init intel_idle_init_cstates_icpu(struct cpuidle_driver *drv)
1441{
1442	int cstate;
1443
1444	switch (boot_cpu_data.x86_model) {
1445	case INTEL_FAM6_IVYBRIDGE_X:
1446		ivt_idle_state_table_update();
1447		break;
1448	case INTEL_FAM6_ATOM_GOLDMONT:
1449	case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
1450		bxt_idle_state_table_update();
1451		break;
1452	case INTEL_FAM6_SKYLAKE:
1453		sklh_idle_state_table_update();
1454		break;
1455	}
1456
1457	for (cstate = 0; cstate < CPUIDLE_STATE_MAX; ++cstate) {
1458		unsigned int mwait_hint;
1459
1460		if (intel_idle_max_cstate_reached(cstate))
1461			break;
1462
1463		if (!cpuidle_state_table[cstate].enter &&
1464		    !cpuidle_state_table[cstate].enter_s2idle)
1465			break;
1466
1467		/* If marked as unusable, skip this state. */
1468		if (cpuidle_state_table[cstate].flags & CPUIDLE_FLAG_UNUSABLE) {
1469			pr_debug("state %s is disabled\n",
1470				 cpuidle_state_table[cstate].name);
1471			continue;
1472		}
1473
1474		mwait_hint = flg2MWAIT(cpuidle_state_table[cstate].flags);
1475		if (!intel_idle_verify_cstate(mwait_hint))
1476			continue;
1477
1478		/* Structure copy. */
1479		drv->states[drv->state_count] = cpuidle_state_table[cstate];
1480
1481		if ((disabled_states_mask & BIT(drv->state_count)) ||
1482		    ((icpu->use_acpi || force_use_acpi) &&
1483		     intel_idle_off_by_default(mwait_hint) &&
1484		     !(cpuidle_state_table[cstate].flags & CPUIDLE_FLAG_ALWAYS_ENABLE)))
1485			drv->states[drv->state_count].flags |= CPUIDLE_FLAG_OFF;
1486
1487		drv->state_count++;
1488	}
1489
1490	if (icpu->byt_auto_demotion_disable_flag) {
1491		wrmsrl(MSR_CC6_DEMOTION_POLICY_CONFIG, 0);
1492		wrmsrl(MSR_MC6_DEMOTION_POLICY_CONFIG, 0);
1493	}
1494}
1495
1496/**
1497 * intel_idle_cpuidle_driver_init - Create the list of available idle states.
1498 * @drv: cpuidle driver structure to initialize.
1499 */
1500static void __init intel_idle_cpuidle_driver_init(struct cpuidle_driver *drv)
1501{
1502	cpuidle_poll_state_init(drv);
1503
1504	if (disabled_states_mask & BIT(0))
1505		drv->states[0].flags |= CPUIDLE_FLAG_OFF;
1506
1507	drv->state_count = 1;
1508
1509	if (icpu)
1510		intel_idle_init_cstates_icpu(drv);
1511	else
1512		intel_idle_init_cstates_acpi(drv);
1513}
1514
1515static void auto_demotion_disable(void)
1516{
1517	unsigned long long msr_bits;
1518
1519	rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr_bits);
1520	msr_bits &= ~auto_demotion_disable_flags;
1521	wrmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr_bits);
1522}
1523
1524static void c1e_promotion_disable(void)
1525{
1526	unsigned long long msr_bits;
1527
1528	rdmsrl(MSR_IA32_POWER_CTL, msr_bits);
1529	msr_bits &= ~0x2;
1530	wrmsrl(MSR_IA32_POWER_CTL, msr_bits);
1531}
1532
1533/**
1534 * intel_idle_cpu_init - Register the target CPU with the cpuidle core.
1535 * @cpu: CPU to initialize.
1536 *
1537 * Register a cpuidle device object for @cpu and update its MSRs in accordance
1538 * with the processor model flags.
1539 */
1540static int intel_idle_cpu_init(unsigned int cpu)
1541{
1542	struct cpuidle_device *dev;
1543
1544	dev = per_cpu_ptr(intel_idle_cpuidle_devices, cpu);
1545	dev->cpu = cpu;
1546
1547	if (cpuidle_register_device(dev)) {
1548		pr_debug("cpuidle_register_device %d failed!\n", cpu);
1549		return -EIO;
1550	}
1551
1552	if (auto_demotion_disable_flags)
1553		auto_demotion_disable();
1554
1555	if (disable_promotion_to_c1e)
1556		c1e_promotion_disable();
1557
1558	return 0;
1559}
1560
1561static int intel_idle_cpu_online(unsigned int cpu)
1562{
1563	struct cpuidle_device *dev;
1564
1565	if (!lapic_timer_always_reliable)
1566		tick_broadcast_enable();
1567
1568	/*
1569	 * Some systems can hotplug a cpu at runtime after
1570	 * the kernel has booted, we have to initialize the
1571	 * driver in this case
1572	 */
1573	dev = per_cpu_ptr(intel_idle_cpuidle_devices, cpu);
1574	if (!dev->registered)
1575		return intel_idle_cpu_init(cpu);
1576
1577	return 0;
1578}
1579
1580/**
1581 * intel_idle_cpuidle_devices_uninit - Unregister all cpuidle devices.
1582 */
1583static void __init intel_idle_cpuidle_devices_uninit(void)
1584{
1585	int i;
1586
1587	for_each_online_cpu(i)
1588		cpuidle_unregister_device(per_cpu_ptr(intel_idle_cpuidle_devices, i));
1589}
1590
1591static int __init intel_idle_init(void)
1592{
1593	const struct x86_cpu_id *id;
1594	unsigned int eax, ebx, ecx;
1595	int retval;
1596
1597	/* Do not load intel_idle at all for now if idle= is passed */
1598	if (boot_option_idle_override != IDLE_NO_OVERRIDE)
1599		return -ENODEV;
1600
1601	if (max_cstate == 0) {
1602		pr_debug("disabled\n");
1603		return -EPERM;
1604	}
1605
1606	id = x86_match_cpu(intel_idle_ids);
1607	if (id) {
1608		if (!boot_cpu_has(X86_FEATURE_MWAIT)) {
1609			pr_debug("Please enable MWAIT in BIOS SETUP\n");
1610			return -ENODEV;
1611		}
1612	} else {
1613		id = x86_match_cpu(intel_mwait_ids);
1614		if (!id)
1615			return -ENODEV;
1616	}
1617
1618	if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
1619		return -ENODEV;
1620
1621	cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates);
1622
1623	if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) ||
1624	    !(ecx & CPUID5_ECX_INTERRUPT_BREAK) ||
1625	    !mwait_substates)
1626			return -ENODEV;
1627
1628	pr_debug("MWAIT substates: 0x%x\n", mwait_substates);
1629
1630	icpu = (const struct idle_cpu *)id->driver_data;
1631	if (icpu) {
1632		cpuidle_state_table = icpu->state_table;
1633		auto_demotion_disable_flags = icpu->auto_demotion_disable_flags;
1634		disable_promotion_to_c1e = icpu->disable_promotion_to_c1e;
1635		if (icpu->use_acpi || force_use_acpi)
1636			intel_idle_acpi_cst_extract();
1637	} else if (!intel_idle_acpi_cst_extract()) {
1638		return -ENODEV;
1639	}
1640
1641	pr_debug("v" INTEL_IDLE_VERSION " model 0x%X\n",
1642		 boot_cpu_data.x86_model);
1643
1644	intel_idle_cpuidle_devices = alloc_percpu(struct cpuidle_device);
1645	if (!intel_idle_cpuidle_devices)
1646		return -ENOMEM;
1647
1648	intel_idle_cpuidle_driver_init(&intel_idle_driver);
1649
1650	retval = cpuidle_register_driver(&intel_idle_driver);
1651	if (retval) {
1652		struct cpuidle_driver *drv = cpuidle_get_driver();
1653		printk(KERN_DEBUG pr_fmt("intel_idle yielding to %s\n"),
1654		       drv ? drv->name : "none");
1655		goto init_driver_fail;
1656	}
1657
1658	if (boot_cpu_has(X86_FEATURE_ARAT))	/* Always Reliable APIC Timer */
1659		lapic_timer_always_reliable = true;
1660
1661	retval = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "idle/intel:online",
1662				   intel_idle_cpu_online, NULL);
1663	if (retval < 0)
1664		goto hp_setup_fail;
1665
1666	pr_debug("Local APIC timer is reliable in %s\n",
1667		 lapic_timer_always_reliable ? "all C-states" : "C1");
1668
1669	return 0;
1670
1671hp_setup_fail:
1672	intel_idle_cpuidle_devices_uninit();
1673	cpuidle_unregister_driver(&intel_idle_driver);
1674init_driver_fail:
1675	free_percpu(intel_idle_cpuidle_devices);
1676	return retval;
1677
1678}
1679device_initcall(intel_idle_init);
1680
1681/*
1682 * We are not really modular, but we used to support that.  Meaning we also
1683 * support "intel_idle.max_cstate=..." at boot and also a read-only export of
1684 * it at /sys/module/intel_idle/parameters/max_cstate -- so using module_param
1685 * is the easiest way (currently) to continue doing that.
1686 */
1687module_param(max_cstate, int, 0444);
1688/*
1689 * The positions of the bits that are set in this number are the indices of the
1690 * idle states to be disabled by default (as reflected by the names of the
1691 * corresponding idle state directories in sysfs, "state0", "state1" ...
1692 * "state<i>" ..., where <i> is the index of the given state).
1693 */
1694module_param_named(states_off, disabled_states_mask, uint, 0444);
1695MODULE_PARM_DESC(states_off, "Mask of disabled idle states");