/drivers/bcma/scan.c

http://github.com/mirrors/linux · C · 527 lines · 438 code · 59 blank · 30 comment · 112 complexity · 27e508de3c03b24a9b9e819252b9764f MD5 · raw file

  1. /*
  2. * Broadcom specific AMBA
  3. * Bus scanning
  4. *
  5. * Licensed under the GNU/GPL. See COPYING for details.
  6. */
  7. #include "scan.h"
  8. #include "bcma_private.h"
  9. #include <linux/bcma/bcma.h>
  10. #include <linux/bcma/bcma_regs.h>
  11. #include <linux/pci.h>
  12. #include <linux/io.h>
  13. #include <linux/dma-mapping.h>
  14. #include <linux/slab.h>
  15. struct bcma_device_id_name {
  16. u16 id;
  17. const char *name;
  18. };
  19. static const struct bcma_device_id_name bcma_arm_device_names[] = {
  20. { BCMA_CORE_4706_MAC_GBIT_COMMON, "BCM4706 GBit MAC Common" },
  21. { BCMA_CORE_ARM_1176, "ARM 1176" },
  22. { BCMA_CORE_ARM_7TDMI, "ARM 7TDMI" },
  23. { BCMA_CORE_ARM_CM3, "ARM CM3" },
  24. };
  25. static const struct bcma_device_id_name bcma_bcm_device_names[] = {
  26. { BCMA_CORE_OOB_ROUTER, "OOB Router" },
  27. { BCMA_CORE_4706_CHIPCOMMON, "BCM4706 ChipCommon" },
  28. { BCMA_CORE_4706_SOC_RAM, "BCM4706 SOC RAM" },
  29. { BCMA_CORE_4706_MAC_GBIT, "BCM4706 GBit MAC" },
  30. { BCMA_CORE_NS_PCIEG2, "PCIe Gen 2" },
  31. { BCMA_CORE_NS_DMA, "DMA" },
  32. { BCMA_CORE_NS_SDIO3, "SDIO3" },
  33. { BCMA_CORE_NS_USB20, "USB 2.0" },
  34. { BCMA_CORE_NS_USB30, "USB 3.0" },
  35. { BCMA_CORE_NS_A9JTAG, "ARM Cortex A9 JTAG" },
  36. { BCMA_CORE_NS_DDR23, "Denali DDR2/DDR3 memory controller" },
  37. { BCMA_CORE_NS_ROM, "ROM" },
  38. { BCMA_CORE_NS_NAND, "NAND flash controller" },
  39. { BCMA_CORE_NS_QSPI, "SPI flash controller" },
  40. { BCMA_CORE_NS_CHIPCOMMON_B, "Chipcommon B" },
  41. { BCMA_CORE_ARMCA9, "ARM Cortex A9 core (ihost)" },
  42. { BCMA_CORE_AMEMC, "AMEMC (DDR)" },
  43. { BCMA_CORE_ALTA, "ALTA (I2S)" },
  44. { BCMA_CORE_INVALID, "Invalid" },
  45. { BCMA_CORE_CHIPCOMMON, "ChipCommon" },
  46. { BCMA_CORE_ILINE20, "ILine 20" },
  47. { BCMA_CORE_SRAM, "SRAM" },
  48. { BCMA_CORE_SDRAM, "SDRAM" },
  49. { BCMA_CORE_PCI, "PCI" },
  50. { BCMA_CORE_ETHERNET, "Fast Ethernet" },
  51. { BCMA_CORE_V90, "V90" },
  52. { BCMA_CORE_USB11_HOSTDEV, "USB 1.1 Hostdev" },
  53. { BCMA_CORE_ADSL, "ADSL" },
  54. { BCMA_CORE_ILINE100, "ILine 100" },
  55. { BCMA_CORE_IPSEC, "IPSEC" },
  56. { BCMA_CORE_UTOPIA, "UTOPIA" },
  57. { BCMA_CORE_PCMCIA, "PCMCIA" },
  58. { BCMA_CORE_INTERNAL_MEM, "Internal Memory" },
  59. { BCMA_CORE_MEMC_SDRAM, "MEMC SDRAM" },
  60. { BCMA_CORE_OFDM, "OFDM" },
  61. { BCMA_CORE_EXTIF, "EXTIF" },
  62. { BCMA_CORE_80211, "IEEE 802.11" },
  63. { BCMA_CORE_PHY_A, "PHY A" },
  64. { BCMA_CORE_PHY_B, "PHY B" },
  65. { BCMA_CORE_PHY_G, "PHY G" },
  66. { BCMA_CORE_USB11_HOST, "USB 1.1 Host" },
  67. { BCMA_CORE_USB11_DEV, "USB 1.1 Device" },
  68. { BCMA_CORE_USB20_HOST, "USB 2.0 Host" },
  69. { BCMA_CORE_USB20_DEV, "USB 2.0 Device" },
  70. { BCMA_CORE_SDIO_HOST, "SDIO Host" },
  71. { BCMA_CORE_ROBOSWITCH, "Roboswitch" },
  72. { BCMA_CORE_PARA_ATA, "PATA" },
  73. { BCMA_CORE_SATA_XORDMA, "SATA XOR-DMA" },
  74. { BCMA_CORE_ETHERNET_GBIT, "GBit Ethernet" },
  75. { BCMA_CORE_PCIE, "PCIe" },
  76. { BCMA_CORE_PHY_N, "PHY N" },
  77. { BCMA_CORE_SRAM_CTL, "SRAM Controller" },
  78. { BCMA_CORE_MINI_MACPHY, "Mini MACPHY" },
  79. { BCMA_CORE_PHY_LP, "PHY LP" },
  80. { BCMA_CORE_PMU, "PMU" },
  81. { BCMA_CORE_PHY_SSN, "PHY SSN" },
  82. { BCMA_CORE_SDIO_DEV, "SDIO Device" },
  83. { BCMA_CORE_PHY_HT, "PHY HT" },
  84. { BCMA_CORE_MAC_GBIT, "GBit MAC" },
  85. { BCMA_CORE_DDR12_MEM_CTL, "DDR1/DDR2 Memory Controller" },
  86. { BCMA_CORE_PCIE_RC, "PCIe Root Complex" },
  87. { BCMA_CORE_OCP_OCP_BRIDGE, "OCP to OCP Bridge" },
  88. { BCMA_CORE_SHARED_COMMON, "Common Shared" },
  89. { BCMA_CORE_OCP_AHB_BRIDGE, "OCP to AHB Bridge" },
  90. { BCMA_CORE_SPI_HOST, "SPI Host" },
  91. { BCMA_CORE_I2S, "I2S" },
  92. { BCMA_CORE_SDR_DDR1_MEM_CTL, "SDR/DDR1 Memory Controller" },
  93. { BCMA_CORE_SHIM, "SHIM" },
  94. { BCMA_CORE_PCIE2, "PCIe Gen2" },
  95. { BCMA_CORE_ARM_CR4, "ARM CR4" },
  96. { BCMA_CORE_GCI, "GCI" },
  97. { BCMA_CORE_CMEM, "CNDS DDR2/3 memory controller" },
  98. { BCMA_CORE_ARM_CA7, "ARM CA7" },
  99. { BCMA_CORE_DEFAULT, "Default" },
  100. };
  101. static const struct bcma_device_id_name bcma_mips_device_names[] = {
  102. { BCMA_CORE_MIPS, "MIPS" },
  103. { BCMA_CORE_MIPS_3302, "MIPS 3302" },
  104. { BCMA_CORE_MIPS_74K, "MIPS 74K" },
  105. };
  106. static const char *bcma_device_name(const struct bcma_device_id *id)
  107. {
  108. const struct bcma_device_id_name *names;
  109. int size, i;
  110. /* search manufacturer specific names */
  111. switch (id->manuf) {
  112. case BCMA_MANUF_ARM:
  113. names = bcma_arm_device_names;
  114. size = ARRAY_SIZE(bcma_arm_device_names);
  115. break;
  116. case BCMA_MANUF_BCM:
  117. names = bcma_bcm_device_names;
  118. size = ARRAY_SIZE(bcma_bcm_device_names);
  119. break;
  120. case BCMA_MANUF_MIPS:
  121. names = bcma_mips_device_names;
  122. size = ARRAY_SIZE(bcma_mips_device_names);
  123. break;
  124. default:
  125. return "UNKNOWN";
  126. }
  127. for (i = 0; i < size; i++) {
  128. if (names[i].id == id->id)
  129. return names[i].name;
  130. }
  131. return "UNKNOWN";
  132. }
  133. static u32 bcma_scan_read32(struct bcma_bus *bus, u8 current_coreidx,
  134. u16 offset)
  135. {
  136. return readl(bus->mmio + offset);
  137. }
  138. static void bcma_scan_switch_core(struct bcma_bus *bus, u32 addr)
  139. {
  140. if (bus->hosttype == BCMA_HOSTTYPE_PCI)
  141. pci_write_config_dword(bus->host_pci, BCMA_PCI_BAR0_WIN,
  142. addr);
  143. }
  144. static u32 bcma_erom_get_ent(struct bcma_bus *bus, u32 __iomem **eromptr)
  145. {
  146. u32 ent = readl(*eromptr);
  147. (*eromptr)++;
  148. return ent;
  149. }
  150. static void bcma_erom_push_ent(u32 __iomem **eromptr)
  151. {
  152. (*eromptr)--;
  153. }
  154. static s32 bcma_erom_get_ci(struct bcma_bus *bus, u32 __iomem **eromptr)
  155. {
  156. u32 ent = bcma_erom_get_ent(bus, eromptr);
  157. if (!(ent & SCAN_ER_VALID))
  158. return -ENOENT;
  159. if ((ent & SCAN_ER_TAG) != SCAN_ER_TAG_CI)
  160. return -ENOENT;
  161. return ent;
  162. }
  163. static bool bcma_erom_is_end(struct bcma_bus *bus, u32 __iomem **eromptr)
  164. {
  165. u32 ent = bcma_erom_get_ent(bus, eromptr);
  166. bcma_erom_push_ent(eromptr);
  167. return (ent == (SCAN_ER_TAG_END | SCAN_ER_VALID));
  168. }
  169. static bool bcma_erom_is_bridge(struct bcma_bus *bus, u32 __iomem **eromptr)
  170. {
  171. u32 ent = bcma_erom_get_ent(bus, eromptr);
  172. bcma_erom_push_ent(eromptr);
  173. return (((ent & SCAN_ER_VALID)) &&
  174. ((ent & SCAN_ER_TAGX) == SCAN_ER_TAG_ADDR) &&
  175. ((ent & SCAN_ADDR_TYPE) == SCAN_ADDR_TYPE_BRIDGE));
  176. }
  177. static void bcma_erom_skip_component(struct bcma_bus *bus, u32 __iomem **eromptr)
  178. {
  179. u32 ent;
  180. while (1) {
  181. ent = bcma_erom_get_ent(bus, eromptr);
  182. if ((ent & SCAN_ER_VALID) &&
  183. ((ent & SCAN_ER_TAG) == SCAN_ER_TAG_CI))
  184. break;
  185. if (ent == (SCAN_ER_TAG_END | SCAN_ER_VALID))
  186. break;
  187. }
  188. bcma_erom_push_ent(eromptr);
  189. }
  190. static s32 bcma_erom_get_mst_port(struct bcma_bus *bus, u32 __iomem **eromptr)
  191. {
  192. u32 ent = bcma_erom_get_ent(bus, eromptr);
  193. if (!(ent & SCAN_ER_VALID))
  194. return -ENOENT;
  195. if ((ent & SCAN_ER_TAG) != SCAN_ER_TAG_MP)
  196. return -ENOENT;
  197. return ent;
  198. }
  199. static u32 bcma_erom_get_addr_desc(struct bcma_bus *bus, u32 __iomem **eromptr,
  200. u32 type, u8 port)
  201. {
  202. u32 addrl, addrh, sizeh = 0;
  203. u32 size;
  204. u32 ent = bcma_erom_get_ent(bus, eromptr);
  205. if ((!(ent & SCAN_ER_VALID)) ||
  206. ((ent & SCAN_ER_TAGX) != SCAN_ER_TAG_ADDR) ||
  207. ((ent & SCAN_ADDR_TYPE) != type) ||
  208. (((ent & SCAN_ADDR_PORT) >> SCAN_ADDR_PORT_SHIFT) != port)) {
  209. bcma_erom_push_ent(eromptr);
  210. return (u32)-EINVAL;
  211. }
  212. addrl = ent & SCAN_ADDR_ADDR;
  213. if (ent & SCAN_ADDR_AG32)
  214. addrh = bcma_erom_get_ent(bus, eromptr);
  215. else
  216. addrh = 0;
  217. if ((ent & SCAN_ADDR_SZ) == SCAN_ADDR_SZ_SZD) {
  218. size = bcma_erom_get_ent(bus, eromptr);
  219. if (size & SCAN_SIZE_SG32)
  220. sizeh = bcma_erom_get_ent(bus, eromptr);
  221. }
  222. return addrl;
  223. }
  224. static struct bcma_device *bcma_find_core_by_index(struct bcma_bus *bus,
  225. u16 index)
  226. {
  227. struct bcma_device *core;
  228. list_for_each_entry(core, &bus->cores, list) {
  229. if (core->core_index == index)
  230. return core;
  231. }
  232. return NULL;
  233. }
  234. static struct bcma_device *bcma_find_core_reverse(struct bcma_bus *bus, u16 coreid)
  235. {
  236. struct bcma_device *core;
  237. list_for_each_entry_reverse(core, &bus->cores, list) {
  238. if (core->id.id == coreid)
  239. return core;
  240. }
  241. return NULL;
  242. }
  243. #define IS_ERR_VALUE_U32(x) ((x) >= (u32)-MAX_ERRNO)
  244. static int bcma_get_next_core(struct bcma_bus *bus, u32 __iomem **eromptr,
  245. struct bcma_device_id *match, int core_num,
  246. struct bcma_device *core)
  247. {
  248. u32 tmp;
  249. u8 i, j, k;
  250. s32 cia, cib;
  251. u8 ports[2], wrappers[2];
  252. /* get CIs */
  253. cia = bcma_erom_get_ci(bus, eromptr);
  254. if (cia < 0) {
  255. bcma_erom_push_ent(eromptr);
  256. if (bcma_erom_is_end(bus, eromptr))
  257. return -ESPIPE;
  258. return -EILSEQ;
  259. }
  260. cib = bcma_erom_get_ci(bus, eromptr);
  261. if (cib < 0)
  262. return -EILSEQ;
  263. /* parse CIs */
  264. core->id.class = (cia & SCAN_CIA_CLASS) >> SCAN_CIA_CLASS_SHIFT;
  265. core->id.id = (cia & SCAN_CIA_ID) >> SCAN_CIA_ID_SHIFT;
  266. core->id.manuf = (cia & SCAN_CIA_MANUF) >> SCAN_CIA_MANUF_SHIFT;
  267. ports[0] = (cib & SCAN_CIB_NMP) >> SCAN_CIB_NMP_SHIFT;
  268. ports[1] = (cib & SCAN_CIB_NSP) >> SCAN_CIB_NSP_SHIFT;
  269. wrappers[0] = (cib & SCAN_CIB_NMW) >> SCAN_CIB_NMW_SHIFT;
  270. wrappers[1] = (cib & SCAN_CIB_NSW) >> SCAN_CIB_NSW_SHIFT;
  271. core->id.rev = (cib & SCAN_CIB_REV) >> SCAN_CIB_REV_SHIFT;
  272. if (((core->id.manuf == BCMA_MANUF_ARM) &&
  273. (core->id.id == 0xFFF)) ||
  274. (ports[1] == 0)) {
  275. bcma_erom_skip_component(bus, eromptr);
  276. return -ENXIO;
  277. }
  278. /* check if component is a core at all */
  279. if (wrappers[0] + wrappers[1] == 0) {
  280. /* Some specific cores don't need wrappers */
  281. switch (core->id.id) {
  282. case BCMA_CORE_4706_MAC_GBIT_COMMON:
  283. case BCMA_CORE_NS_CHIPCOMMON_B:
  284. case BCMA_CORE_PMU:
  285. case BCMA_CORE_GCI:
  286. /* Not used yet: case BCMA_CORE_OOB_ROUTER: */
  287. break;
  288. default:
  289. bcma_erom_skip_component(bus, eromptr);
  290. return -ENXIO;
  291. }
  292. }
  293. if (bcma_erom_is_bridge(bus, eromptr)) {
  294. bcma_erom_skip_component(bus, eromptr);
  295. return -ENXIO;
  296. }
  297. if (bcma_find_core_by_index(bus, core_num)) {
  298. bcma_erom_skip_component(bus, eromptr);
  299. return -ENODEV;
  300. }
  301. if (match && ((match->manuf != BCMA_ANY_MANUF &&
  302. match->manuf != core->id.manuf) ||
  303. (match->id != BCMA_ANY_ID && match->id != core->id.id) ||
  304. (match->rev != BCMA_ANY_REV && match->rev != core->id.rev) ||
  305. (match->class != BCMA_ANY_CLASS && match->class != core->id.class)
  306. )) {
  307. bcma_erom_skip_component(bus, eromptr);
  308. return -ENODEV;
  309. }
  310. /* get & parse master ports */
  311. for (i = 0; i < ports[0]; i++) {
  312. s32 mst_port_d = bcma_erom_get_mst_port(bus, eromptr);
  313. if (mst_port_d < 0)
  314. return -EILSEQ;
  315. }
  316. /* First Slave Address Descriptor should be port 0:
  317. * the main register space for the core
  318. */
  319. tmp = bcma_erom_get_addr_desc(bus, eromptr, SCAN_ADDR_TYPE_SLAVE, 0);
  320. if (tmp == 0 || IS_ERR_VALUE_U32(tmp)) {
  321. /* Try again to see if it is a bridge */
  322. tmp = bcma_erom_get_addr_desc(bus, eromptr,
  323. SCAN_ADDR_TYPE_BRIDGE, 0);
  324. if (tmp == 0 || IS_ERR_VALUE_U32(tmp)) {
  325. return -EILSEQ;
  326. } else {
  327. bcma_info(bus, "Bridge found\n");
  328. return -ENXIO;
  329. }
  330. }
  331. core->addr = tmp;
  332. /* get & parse slave ports */
  333. k = 0;
  334. for (i = 0; i < ports[1]; i++) {
  335. for (j = 0; ; j++) {
  336. tmp = bcma_erom_get_addr_desc(bus, eromptr,
  337. SCAN_ADDR_TYPE_SLAVE, i);
  338. if (IS_ERR_VALUE_U32(tmp)) {
  339. /* no more entries for port _i_ */
  340. /* pr_debug("erom: slave port %d "
  341. * "has %d descriptors\n", i, j); */
  342. break;
  343. } else if (k < ARRAY_SIZE(core->addr_s)) {
  344. core->addr_s[k] = tmp;
  345. k++;
  346. }
  347. }
  348. }
  349. /* get & parse master wrappers */
  350. for (i = 0; i < wrappers[0]; i++) {
  351. for (j = 0; ; j++) {
  352. tmp = bcma_erom_get_addr_desc(bus, eromptr,
  353. SCAN_ADDR_TYPE_MWRAP, i);
  354. if (IS_ERR_VALUE_U32(tmp)) {
  355. /* no more entries for port _i_ */
  356. /* pr_debug("erom: master wrapper %d "
  357. * "has %d descriptors\n", i, j); */
  358. break;
  359. } else {
  360. if (i == 0 && j == 0)
  361. core->wrap = tmp;
  362. }
  363. }
  364. }
  365. /* get & parse slave wrappers */
  366. for (i = 0; i < wrappers[1]; i++) {
  367. u8 hack = (ports[1] == 1) ? 0 : 1;
  368. for (j = 0; ; j++) {
  369. tmp = bcma_erom_get_addr_desc(bus, eromptr,
  370. SCAN_ADDR_TYPE_SWRAP, i + hack);
  371. if (IS_ERR_VALUE_U32(tmp)) {
  372. /* no more entries for port _i_ */
  373. /* pr_debug("erom: master wrapper %d "
  374. * has %d descriptors\n", i, j); */
  375. break;
  376. } else {
  377. if (wrappers[0] == 0 && !i && !j)
  378. core->wrap = tmp;
  379. }
  380. }
  381. }
  382. if (bus->hosttype == BCMA_HOSTTYPE_SOC) {
  383. core->io_addr = ioremap(core->addr, BCMA_CORE_SIZE);
  384. if (!core->io_addr)
  385. return -ENOMEM;
  386. if (core->wrap) {
  387. core->io_wrap = ioremap(core->wrap,
  388. BCMA_CORE_SIZE);
  389. if (!core->io_wrap) {
  390. iounmap(core->io_addr);
  391. return -ENOMEM;
  392. }
  393. }
  394. }
  395. return 0;
  396. }
  397. void bcma_detect_chip(struct bcma_bus *bus)
  398. {
  399. s32 tmp;
  400. struct bcma_chipinfo *chipinfo = &(bus->chipinfo);
  401. char chip_id[8];
  402. bcma_scan_switch_core(bus, BCMA_ADDR_BASE);
  403. tmp = bcma_scan_read32(bus, 0, BCMA_CC_ID);
  404. chipinfo->id = (tmp & BCMA_CC_ID_ID) >> BCMA_CC_ID_ID_SHIFT;
  405. chipinfo->rev = (tmp & BCMA_CC_ID_REV) >> BCMA_CC_ID_REV_SHIFT;
  406. chipinfo->pkg = (tmp & BCMA_CC_ID_PKG) >> BCMA_CC_ID_PKG_SHIFT;
  407. snprintf(chip_id, ARRAY_SIZE(chip_id),
  408. (chipinfo->id > 0x9999) ? "%d" : "0x%04X", chipinfo->id);
  409. bcma_info(bus, "Found chip with id %s, rev 0x%02X and package 0x%02X\n",
  410. chip_id, chipinfo->rev, chipinfo->pkg);
  411. }
  412. int bcma_bus_scan(struct bcma_bus *bus)
  413. {
  414. u32 erombase;
  415. u32 __iomem *eromptr, *eromend;
  416. int err, core_num = 0;
  417. /* Skip if bus was already scanned (e.g. during early register) */
  418. if (bus->nr_cores)
  419. return 0;
  420. erombase = bcma_scan_read32(bus, 0, BCMA_CC_EROM);
  421. if (bus->hosttype == BCMA_HOSTTYPE_SOC) {
  422. eromptr = ioremap(erombase, BCMA_CORE_SIZE);
  423. if (!eromptr)
  424. return -ENOMEM;
  425. } else {
  426. eromptr = bus->mmio;
  427. }
  428. eromend = eromptr + BCMA_CORE_SIZE / sizeof(u32);
  429. bcma_scan_switch_core(bus, erombase);
  430. while (eromptr < eromend) {
  431. struct bcma_device *other_core;
  432. struct bcma_device *core = kzalloc(sizeof(*core), GFP_KERNEL);
  433. if (!core) {
  434. err = -ENOMEM;
  435. goto out;
  436. }
  437. INIT_LIST_HEAD(&core->list);
  438. core->bus = bus;
  439. err = bcma_get_next_core(bus, &eromptr, NULL, core_num, core);
  440. if (err < 0) {
  441. kfree(core);
  442. if (err == -ENODEV) {
  443. core_num++;
  444. continue;
  445. } else if (err == -ENXIO) {
  446. continue;
  447. } else if (err == -ESPIPE) {
  448. break;
  449. }
  450. goto out;
  451. }
  452. core->core_index = core_num++;
  453. bus->nr_cores++;
  454. other_core = bcma_find_core_reverse(bus, core->id.id);
  455. core->core_unit = (other_core == NULL) ? 0 : other_core->core_unit + 1;
  456. bcma_prepare_core(bus, core);
  457. bcma_info(bus, "Core %d found: %s (manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n",
  458. core->core_index, bcma_device_name(&core->id),
  459. core->id.manuf, core->id.id, core->id.rev,
  460. core->id.class);
  461. list_add_tail(&core->list, &bus->cores);
  462. }
  463. err = 0;
  464. out:
  465. if (bus->hosttype == BCMA_HOSTTYPE_SOC)
  466. iounmap(eromptr);
  467. return err;
  468. }