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/drivers/isdn/hisax/hfc_sx.c

http://github.com/mirrors/linux
C | 1520 lines | 1255 code | 115 blank | 150 comment | 245 complexity | cccee0f9d3ec83f9c7359f3b4b2b7e0d MD5 | raw file
   1/* $Id: hfc_sx.c,v 1.12.2.5 2004/02/11 13:21:33 keil Exp $
   2 *
   3 * level driver for Cologne Chip Designs hfc-s+/sp based cards
   4 *
   5 * Author       Werner Cornelius
   6 *              based on existing driver for CCD HFC PCI cards
   7 * Copyright    by Werner Cornelius  <werner@isdn4linux.de>
   8 *
   9 * This software may be used and distributed according to the terms
  10 * of the GNU General Public License, incorporated herein by reference.
  11 *
  12 */
  13
  14#include <linux/init.h>
  15#include "hisax.h"
  16#include "hfc_sx.h"
  17#include "isdnl1.h"
  18#include <linux/interrupt.h>
  19#include <linux/isapnp.h>
  20#include <linux/slab.h>
  21
  22static const char *hfcsx_revision = "$Revision: 1.12.2.5 $";
  23
  24/***************************************/
  25/* IRQ-table for CCDs demo board       */
  26/* IRQs 6,5,10,11,12,15 are supported  */
  27/***************************************/
  28
  29/* Teles 16.3c Vendor Id TAG2620, Version 1.0, Vendor version 2.1
  30 *
  31 * Thanks to Uwe Wisniewski
  32 *
  33 * ISA-SLOT  Signal      PIN
  34 * B25        IRQ3     92 IRQ_G
  35 * B23        IRQ5     94 IRQ_A
  36 * B4         IRQ2/9   95 IRQ_B
  37 * D3         IRQ10    96 IRQ_C
  38 * D4         IRQ11    97 IRQ_D
  39 * D5         IRQ12    98 IRQ_E
  40 * D6         IRQ15    99 IRQ_F
  41 */
  42
  43#undef CCD_DEMO_BOARD
  44#ifdef CCD_DEMO_BOARD
  45static u_char ccd_sp_irqtab[16] = {
  46	0, 0, 0, 0, 0, 2, 1, 0, 0, 0, 3, 4, 5, 0, 0, 6
  47};
  48#else /* Teles 16.3c */
  49static u_char ccd_sp_irqtab[16] = {
  50	0, 0, 0, 7, 0, 1, 0, 0, 0, 2, 3, 4, 5, 0, 0, 6
  51};
  52#endif
  53#define NT_T1_COUNT 20		/* number of 3.125ms interrupts for G2 timeout */
  54
  55#define byteout(addr, val) outb(val, addr)
  56#define bytein(addr) inb(addr)
  57
  58/******************************/
  59/* In/Out access to registers */
  60/******************************/
  61static inline void
  62Write_hfc(struct IsdnCardState *cs, u_char regnum, u_char val)
  63{
  64	byteout(cs->hw.hfcsx.base + 1, regnum);
  65	byteout(cs->hw.hfcsx.base, val);
  66}
  67
  68static inline u_char
  69Read_hfc(struct IsdnCardState *cs, u_char regnum)
  70{
  71	u_char ret;
  72
  73	byteout(cs->hw.hfcsx.base + 1, regnum);
  74	ret = bytein(cs->hw.hfcsx.base);
  75	return (ret);
  76}
  77
  78
  79/**************************************************/
  80/* select a fifo and remember which one for reuse */
  81/**************************************************/
  82static void
  83fifo_select(struct IsdnCardState *cs, u_char fifo)
  84{
  85	if (fifo == cs->hw.hfcsx.last_fifo)
  86		return; /* still valid */
  87
  88	byteout(cs->hw.hfcsx.base + 1, HFCSX_FIF_SEL);
  89	byteout(cs->hw.hfcsx.base, fifo);
  90	while (bytein(cs->hw.hfcsx.base + 1) & 1); /* wait for busy */
  91	udelay(4);
  92	byteout(cs->hw.hfcsx.base, fifo);
  93	while (bytein(cs->hw.hfcsx.base + 1) & 1); /* wait for busy */
  94}
  95
  96/******************************************/
  97/* reset the specified fifo to defaults.  */
  98/* If its a send fifo init needed markers */
  99/******************************************/
 100static void
 101reset_fifo(struct IsdnCardState *cs, u_char fifo)
 102{
 103	fifo_select(cs, fifo); /* first select the fifo */
 104	byteout(cs->hw.hfcsx.base + 1, HFCSX_CIRM);
 105	byteout(cs->hw.hfcsx.base, cs->hw.hfcsx.cirm | 0x80); /* reset cmd */
 106	udelay(1);
 107	while (bytein(cs->hw.hfcsx.base + 1) & 1); /* wait for busy */
 108}
 109
 110
 111/*************************************************************/
 112/* write_fifo writes the skb contents to the desired fifo    */
 113/* if no space is available or an error occurs 0 is returned */
 114/* the skb is not released in any way.                       */
 115/*************************************************************/
 116static int
 117write_fifo(struct IsdnCardState *cs, struct sk_buff *skb, u_char fifo, int trans_max)
 118{
 119	unsigned short *msp;
 120	int fifo_size, count, z1, z2;
 121	u_char f_msk, f1, f2, *src;
 122
 123	if (skb->len <= 0) return (0);
 124	if (fifo & 1) return (0); /* no write fifo */
 125
 126	fifo_select(cs, fifo);
 127	if (fifo & 4) {
 128		fifo_size = D_FIFO_SIZE; /* D-channel */
 129		f_msk = MAX_D_FRAMES;
 130		if (trans_max) return (0); /* only HDLC */
 131	}
 132	else {
 133		fifo_size = cs->hw.hfcsx.b_fifo_size; /* B-channel */
 134		f_msk = MAX_B_FRAMES;
 135	}
 136
 137	z1 = Read_hfc(cs, HFCSX_FIF_Z1H);
 138	z1 = ((z1 << 8) | Read_hfc(cs, HFCSX_FIF_Z1L));
 139
 140	/* Check for transparent mode */
 141	if (trans_max) {
 142		z2 = Read_hfc(cs, HFCSX_FIF_Z2H);
 143		z2 = ((z2 << 8) | Read_hfc(cs, HFCSX_FIF_Z2L));
 144		count = z2 - z1;
 145		if (count <= 0)
 146			count += fifo_size; /* free bytes */
 147		if (count < skb->len + 1) return (0); /* no room */
 148		count = fifo_size - count; /* bytes still not send */
 149		if (count > 2 * trans_max) return (0); /* delay to long */
 150		count = skb->len;
 151		src = skb->data;
 152		while (count--)
 153			Write_hfc(cs, HFCSX_FIF_DWR, *src++);
 154		return (1); /* success */
 155	}
 156
 157	msp = ((struct hfcsx_extra *)(cs->hw.hfcsx.extra))->marker;
 158	msp += (((fifo >> 1) & 3) * (MAX_B_FRAMES + 1));
 159	f1 = Read_hfc(cs, HFCSX_FIF_F1) & f_msk;
 160	f2 = Read_hfc(cs, HFCSX_FIF_F2) & f_msk;
 161
 162	count = f1 - f2; /* frame count actually buffered */
 163	if (count < 0)
 164		count += (f_msk + 1);	/* if wrap around */
 165	if (count > f_msk - 1) {
 166		if (cs->debug & L1_DEB_ISAC_FIFO)
 167			debugl1(cs, "hfcsx_write_fifo %d more as %d frames", fifo, f_msk - 1);
 168		return (0);
 169	}
 170
 171	*(msp + f1) = z1; /* remember marker */
 172
 173	if (cs->debug & L1_DEB_ISAC_FIFO)
 174		debugl1(cs, "hfcsx_write_fifo %d f1(%x) f2(%x) z1(f1)(%x)",
 175			fifo, f1, f2, z1);
 176	/* now determine free bytes in FIFO buffer */
 177	count = *(msp + f2) - z1;
 178	if (count <= 0)
 179		count += fifo_size;	/* count now contains available bytes */
 180
 181	if (cs->debug & L1_DEB_ISAC_FIFO)
 182		debugl1(cs, "hfcsx_write_fifo %d count(%u/%d)",
 183			fifo, skb->len, count);
 184	if (count < skb->len) {
 185		if (cs->debug & L1_DEB_ISAC_FIFO)
 186			debugl1(cs, "hfcsx_write_fifo %d no fifo mem", fifo);
 187		return (0);
 188	}
 189
 190	count = skb->len; /* get frame len */
 191	src = skb->data;	/* source pointer */
 192	while (count--)
 193		Write_hfc(cs, HFCSX_FIF_DWR, *src++);
 194
 195	Read_hfc(cs, HFCSX_FIF_INCF1); /* increment F1 */
 196	udelay(1);
 197	while (bytein(cs->hw.hfcsx.base + 1) & 1); /* wait for busy */
 198	return (1);
 199}
 200
 201/***************************************************************/
 202/* read_fifo reads data to an skb from the desired fifo        */
 203/* if no data is available or an error occurs NULL is returned */
 204/* the skb is not released in any way.                         */
 205/***************************************************************/
 206static struct sk_buff *
 207read_fifo(struct IsdnCardState *cs, u_char fifo, int trans_max)
 208{       int fifo_size, count, z1, z2;
 209	u_char f_msk, f1, f2, *dst;
 210	struct sk_buff *skb;
 211
 212	if (!(fifo & 1)) return (NULL); /* no read fifo */
 213	fifo_select(cs, fifo);
 214	if (fifo & 4) {
 215		fifo_size = D_FIFO_SIZE; /* D-channel */
 216		f_msk = MAX_D_FRAMES;
 217		if (trans_max) return (NULL); /* only hdlc */
 218	}
 219	else {
 220		fifo_size = cs->hw.hfcsx.b_fifo_size; /* B-channel */
 221		f_msk = MAX_B_FRAMES;
 222	}
 223
 224	/* transparent mode */
 225	if (trans_max) {
 226		z1 = Read_hfc(cs, HFCSX_FIF_Z1H);
 227		z1 = ((z1 << 8) | Read_hfc(cs, HFCSX_FIF_Z1L));
 228		z2 = Read_hfc(cs, HFCSX_FIF_Z2H);
 229		z2 = ((z2 << 8) | Read_hfc(cs, HFCSX_FIF_Z2L));
 230		/* now determine bytes in actual FIFO buffer */
 231		count = z1 - z2;
 232		if (count <= 0)
 233			count += fifo_size;	/* count now contains buffered bytes */
 234		count++;
 235		if (count > trans_max)
 236			count = trans_max; /* limit length */
 237		skb = dev_alloc_skb(count);
 238		if (skb) {
 239			dst = skb_put(skb, count);
 240			while (count--)
 241				*dst++ = Read_hfc(cs, HFCSX_FIF_DRD);
 242			return skb;
 243		} else
 244			return NULL; /* no memory */
 245	}
 246
 247	do {
 248		f1 = Read_hfc(cs, HFCSX_FIF_F1) & f_msk;
 249		f2 = Read_hfc(cs, HFCSX_FIF_F2) & f_msk;
 250
 251		if (f1 == f2) return (NULL); /* no frame available */
 252
 253		z1 = Read_hfc(cs, HFCSX_FIF_Z1H);
 254		z1 = ((z1 << 8) | Read_hfc(cs, HFCSX_FIF_Z1L));
 255		z2 = Read_hfc(cs, HFCSX_FIF_Z2H);
 256		z2 = ((z2 << 8) | Read_hfc(cs, HFCSX_FIF_Z2L));
 257
 258		if (cs->debug & L1_DEB_ISAC_FIFO)
 259			debugl1(cs, "hfcsx_read_fifo %d f1(%x) f2(%x) z1(f2)(%x) z2(f2)(%x)",
 260				fifo, f1, f2, z1, z2);
 261		/* now determine bytes in actual FIFO buffer */
 262		count = z1 - z2;
 263		if (count <= 0)
 264			count += fifo_size;	/* count now contains buffered bytes */
 265		count++;
 266
 267		if (cs->debug & L1_DEB_ISAC_FIFO)
 268			debugl1(cs, "hfcsx_read_fifo %d count %u)",
 269				fifo, count);
 270
 271		if ((count > fifo_size) || (count < 4)) {
 272			if (cs->debug & L1_DEB_WARN)
 273				debugl1(cs, "hfcsx_read_fifo %d packet inv. len %d ", fifo , count);
 274			while (count) {
 275				count--; /* empty fifo */
 276				Read_hfc(cs, HFCSX_FIF_DRD);
 277			}
 278			skb = NULL;
 279		} else
 280			if ((skb = dev_alloc_skb(count - 3))) {
 281				count -= 3;
 282				dst = skb_put(skb, count);
 283
 284				while (count--)
 285					*dst++ = Read_hfc(cs, HFCSX_FIF_DRD);
 286
 287				Read_hfc(cs, HFCSX_FIF_DRD); /* CRC 1 */
 288				Read_hfc(cs, HFCSX_FIF_DRD); /* CRC 2 */
 289				if (Read_hfc(cs, HFCSX_FIF_DRD)) {
 290					dev_kfree_skb_irq(skb);
 291					if (cs->debug & L1_DEB_ISAC_FIFO)
 292						debugl1(cs, "hfcsx_read_fifo %d crc error", fifo);
 293					skb = NULL;
 294				}
 295			} else {
 296				printk(KERN_WARNING "HFC-SX: receive out of memory\n");
 297				return (NULL);
 298			}
 299
 300		Read_hfc(cs, HFCSX_FIF_INCF2); /* increment F2 */
 301		udelay(1);
 302		while (bytein(cs->hw.hfcsx.base + 1) & 1); /* wait for busy */
 303		udelay(1);
 304	} while (!skb); /* retry in case of crc error */
 305	return (skb);
 306}
 307
 308/******************************************/
 309/* free hardware resources used by driver */
 310/******************************************/
 311static void
 312release_io_hfcsx(struct IsdnCardState *cs)
 313{
 314	cs->hw.hfcsx.int_m2 = 0;	/* interrupt output off ! */
 315	Write_hfc(cs, HFCSX_INT_M2, cs->hw.hfcsx.int_m2);
 316	Write_hfc(cs, HFCSX_CIRM, HFCSX_RESET);	/* Reset On */
 317	msleep(30);				/* Timeout 30ms */
 318	Write_hfc(cs, HFCSX_CIRM, 0);	/* Reset Off */
 319	del_timer(&cs->hw.hfcsx.timer);
 320	release_region(cs->hw.hfcsx.base, 2); /* release IO-Block */
 321	kfree(cs->hw.hfcsx.extra);
 322	cs->hw.hfcsx.extra = NULL;
 323}
 324
 325/**********************************************************/
 326/* set_fifo_size determines the size of the RAM and FIFOs */
 327/* returning 0 -> need to reset the chip again.           */
 328/**********************************************************/
 329static int set_fifo_size(struct IsdnCardState *cs)
 330{
 331
 332	if (cs->hw.hfcsx.b_fifo_size) return (1); /* already determined */
 333
 334	if ((cs->hw.hfcsx.chip >> 4) == 9) {
 335		cs->hw.hfcsx.b_fifo_size = B_FIFO_SIZE_32K;
 336		return (1);
 337	}
 338
 339	cs->hw.hfcsx.b_fifo_size = B_FIFO_SIZE_8K;
 340	cs->hw.hfcsx.cirm |= 0x10; /* only 8K of ram */
 341	return (0);
 342
 343}
 344
 345/********************************************************************************/
 346/* function called to reset the HFC SX chip. A complete software reset of chip */
 347/* and fifos is done.                                                           */
 348/********************************************************************************/
 349static void
 350reset_hfcsx(struct IsdnCardState *cs)
 351{
 352	cs->hw.hfcsx.int_m2 = 0;	/* interrupt output off ! */
 353	Write_hfc(cs, HFCSX_INT_M2, cs->hw.hfcsx.int_m2);
 354
 355	printk(KERN_INFO "HFC_SX: resetting card\n");
 356	while (1) {
 357		Write_hfc(cs, HFCSX_CIRM, HFCSX_RESET | cs->hw.hfcsx.cirm); /* Reset */
 358		mdelay(30);
 359		Write_hfc(cs, HFCSX_CIRM, cs->hw.hfcsx.cirm); /* Reset Off */
 360		mdelay(20);
 361		if (Read_hfc(cs, HFCSX_STATUS) & 2)
 362			printk(KERN_WARNING "HFC-SX init bit busy\n");
 363		cs->hw.hfcsx.last_fifo = 0xff; /* invalidate */
 364		if (!set_fifo_size(cs)) continue;
 365		break;
 366	}
 367
 368	cs->hw.hfcsx.trm = 0 + HFCSX_BTRANS_THRESMASK;	/* no echo connect , threshold */
 369	Write_hfc(cs, HFCSX_TRM, cs->hw.hfcsx.trm);
 370
 371	Write_hfc(cs, HFCSX_CLKDEL, 0x0e);	/* ST-Bit delay for TE-Mode */
 372	cs->hw.hfcsx.sctrl_e = HFCSX_AUTO_AWAKE;
 373	Write_hfc(cs, HFCSX_SCTRL_E, cs->hw.hfcsx.sctrl_e);	/* S/T Auto awake */
 374	cs->hw.hfcsx.bswapped = 0;	/* no exchange */
 375	cs->hw.hfcsx.nt_mode = 0;	/* we are in TE mode */
 376	cs->hw.hfcsx.ctmt = HFCSX_TIM3_125 | HFCSX_AUTO_TIMER;
 377	Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt);
 378
 379	cs->hw.hfcsx.int_m1 = HFCSX_INTS_DTRANS | HFCSX_INTS_DREC |
 380		HFCSX_INTS_L1STATE | HFCSX_INTS_TIMER;
 381	Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
 382
 383	/* Clear already pending ints */
 384	if (Read_hfc(cs, HFCSX_INT_S1));
 385
 386	Write_hfc(cs, HFCSX_STATES, HFCSX_LOAD_STATE | 2);	/* HFC ST 2 */
 387	udelay(10);
 388	Write_hfc(cs, HFCSX_STATES, 2);	/* HFC ST 2 */
 389	cs->hw.hfcsx.mst_m = HFCSX_MASTER;	/* HFC Master Mode */
 390
 391	Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m);
 392	cs->hw.hfcsx.sctrl = 0x40;	/* set tx_lo mode, error in datasheet ! */
 393	Write_hfc(cs, HFCSX_SCTRL, cs->hw.hfcsx.sctrl);
 394	cs->hw.hfcsx.sctrl_r = 0;
 395	Write_hfc(cs, HFCSX_SCTRL_R, cs->hw.hfcsx.sctrl_r);
 396
 397	/* Init GCI/IOM2 in master mode */
 398	/* Slots 0 and 1 are set for B-chan 1 and 2 */
 399	/* D- and monitor/CI channel are not enabled */
 400	/* STIO1 is used as output for data, B1+B2 from ST->IOM+HFC */
 401	/* STIO2 is used as data input, B1+B2 from IOM->ST */
 402	/* ST B-channel send disabled -> continuous 1s */
 403	/* The IOM slots are always enabled */
 404	cs->hw.hfcsx.conn = 0x36;	/* set data flow directions */
 405	Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn);
 406	Write_hfc(cs, HFCSX_B1_SSL, 0x80);	/* B1-Slot 0 STIO1 out enabled */
 407	Write_hfc(cs, HFCSX_B2_SSL, 0x81);	/* B2-Slot 1 STIO1 out enabled */
 408	Write_hfc(cs, HFCSX_B1_RSL, 0x80);	/* B1-Slot 0 STIO2 in enabled */
 409	Write_hfc(cs, HFCSX_B2_RSL, 0x81);	/* B2-Slot 1 STIO2 in enabled */
 410
 411	/* Finally enable IRQ output */
 412	cs->hw.hfcsx.int_m2 = HFCSX_IRQ_ENABLE;
 413	Write_hfc(cs, HFCSX_INT_M2, cs->hw.hfcsx.int_m2);
 414	if (Read_hfc(cs, HFCSX_INT_S2));
 415}
 416
 417/***************************************************/
 418/* Timer function called when kernel timer expires */
 419/***************************************************/
 420static void
 421hfcsx_Timer(struct IsdnCardState *cs)
 422{
 423	cs->hw.hfcsx.timer.expires = jiffies + 75;
 424	/* WD RESET */
 425/*      WriteReg(cs, HFCD_DATA, HFCD_CTMT, cs->hw.hfcsx.ctmt | 0x80);
 426	add_timer(&cs->hw.hfcsx.timer);
 427*/
 428}
 429
 430/************************************************/
 431/* select a b-channel entry matching and active */
 432/************************************************/
 433static
 434struct BCState *
 435Sel_BCS(struct IsdnCardState *cs, int channel)
 436{
 437	if (cs->bcs[0].mode && (cs->bcs[0].channel == channel))
 438		return (&cs->bcs[0]);
 439	else if (cs->bcs[1].mode && (cs->bcs[1].channel == channel))
 440		return (&cs->bcs[1]);
 441	else
 442		return (NULL);
 443}
 444
 445/*******************************/
 446/* D-channel receive procedure */
 447/*******************************/
 448static
 449int
 450receive_dmsg(struct IsdnCardState *cs)
 451{
 452	struct sk_buff *skb;
 453	int count = 5;
 454
 455	if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
 456		debugl1(cs, "rec_dmsg blocked");
 457		return (1);
 458	}
 459
 460	do {
 461		skb = read_fifo(cs, HFCSX_SEL_D_RX, 0);
 462		if (skb) {
 463			skb_queue_tail(&cs->rq, skb);
 464			schedule_event(cs, D_RCVBUFREADY);
 465		}
 466	} while (--count && skb);
 467
 468	test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
 469	return (1);
 470}
 471
 472/**********************************/
 473/* B-channel main receive routine */
 474/**********************************/
 475static void
 476main_rec_hfcsx(struct BCState *bcs)
 477{
 478	struct IsdnCardState *cs = bcs->cs;
 479	int count = 5;
 480	struct sk_buff *skb;
 481
 482Begin:
 483	count--;
 484	if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
 485		debugl1(cs, "rec_data %d blocked", bcs->channel);
 486		return;
 487	}
 488	skb = read_fifo(cs, ((bcs->channel) && (!cs->hw.hfcsx.bswapped)) ?
 489			HFCSX_SEL_B2_RX : HFCSX_SEL_B1_RX,
 490			(bcs->mode == L1_MODE_TRANS) ?
 491			HFCSX_BTRANS_THRESHOLD : 0);
 492
 493	if (skb) {
 494		skb_queue_tail(&bcs->rqueue, skb);
 495		schedule_event(bcs, B_RCVBUFREADY);
 496	}
 497
 498	test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
 499	if (count && skb)
 500		goto Begin;
 501	return;
 502}
 503
 504/**************************/
 505/* D-channel send routine */
 506/**************************/
 507static void
 508hfcsx_fill_dfifo(struct IsdnCardState *cs)
 509{
 510	if (!cs->tx_skb)
 511		return;
 512	if (cs->tx_skb->len <= 0)
 513		return;
 514
 515	if (write_fifo(cs, cs->tx_skb, HFCSX_SEL_D_TX, 0)) {
 516		dev_kfree_skb_any(cs->tx_skb);
 517		cs->tx_skb = NULL;
 518	}
 519	return;
 520}
 521
 522/**************************/
 523/* B-channel send routine */
 524/**************************/
 525static void
 526hfcsx_fill_fifo(struct BCState *bcs)
 527{
 528	struct IsdnCardState *cs = bcs->cs;
 529
 530	if (!bcs->tx_skb)
 531		return;
 532	if (bcs->tx_skb->len <= 0)
 533		return;
 534
 535	if (write_fifo(cs, bcs->tx_skb,
 536		       ((bcs->channel) && (!cs->hw.hfcsx.bswapped)) ?
 537		       HFCSX_SEL_B2_TX : HFCSX_SEL_B1_TX,
 538		       (bcs->mode == L1_MODE_TRANS) ?
 539		       HFCSX_BTRANS_THRESHOLD : 0)) {
 540
 541		bcs->tx_cnt -= bcs->tx_skb->len;
 542		if (test_bit(FLG_LLI_L1WAKEUP, &bcs->st->lli.flag) &&
 543		    (PACKET_NOACK != bcs->tx_skb->pkt_type)) {
 544			u_long	flags;
 545			spin_lock_irqsave(&bcs->aclock, flags);
 546			bcs->ackcnt += bcs->tx_skb->len;
 547			spin_unlock_irqrestore(&bcs->aclock, flags);
 548			schedule_event(bcs, B_ACKPENDING);
 549		}
 550		dev_kfree_skb_any(bcs->tx_skb);
 551		bcs->tx_skb = NULL;
 552		test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
 553	}
 554}
 555
 556/**********************************************/
 557/* D-channel l1 state call for leased NT-mode */
 558/**********************************************/
 559static void
 560dch_nt_l2l1(struct PStack *st, int pr, void *arg)
 561{
 562	struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware;
 563
 564	switch (pr) {
 565	case (PH_DATA | REQUEST):
 566	case (PH_PULL | REQUEST):
 567	case (PH_PULL | INDICATION):
 568		st->l1.l1hw(st, pr, arg);
 569		break;
 570	case (PH_ACTIVATE | REQUEST):
 571		st->l1.l1l2(st, PH_ACTIVATE | CONFIRM, NULL);
 572		break;
 573	case (PH_TESTLOOP | REQUEST):
 574		if (1 & (long) arg)
 575			debugl1(cs, "PH_TEST_LOOP B1");
 576		if (2 & (long) arg)
 577			debugl1(cs, "PH_TEST_LOOP B2");
 578		if (!(3 & (long) arg))
 579			debugl1(cs, "PH_TEST_LOOP DISABLED");
 580		st->l1.l1hw(st, HW_TESTLOOP | REQUEST, arg);
 581		break;
 582	default:
 583		if (cs->debug)
 584			debugl1(cs, "dch_nt_l2l1 msg %04X unhandled", pr);
 585		break;
 586	}
 587}
 588
 589
 590
 591/***********************/
 592/* set/reset echo mode */
 593/***********************/
 594static int
 595hfcsx_auxcmd(struct IsdnCardState *cs, isdn_ctrl *ic)
 596{
 597	unsigned long flags;
 598	int i = *(unsigned int *) ic->parm.num;
 599
 600	if ((ic->arg == 98) &&
 601	    (!(cs->hw.hfcsx.int_m1 & (HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC + HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC)))) {
 602		spin_lock_irqsave(&cs->lock, flags);
 603		Write_hfc(cs, HFCSX_STATES, HFCSX_LOAD_STATE | 0);	/* HFC ST G0 */
 604		udelay(10);
 605		cs->hw.hfcsx.sctrl |= SCTRL_MODE_NT;
 606		Write_hfc(cs, HFCSX_SCTRL, cs->hw.hfcsx.sctrl);	/* set NT-mode */
 607		udelay(10);
 608		Write_hfc(cs, HFCSX_STATES, HFCSX_LOAD_STATE | 1);	/* HFC ST G1 */
 609		udelay(10);
 610		Write_hfc(cs, HFCSX_STATES, 1 | HFCSX_ACTIVATE | HFCSX_DO_ACTION);
 611		cs->dc.hfcsx.ph_state = 1;
 612		cs->hw.hfcsx.nt_mode = 1;
 613		cs->hw.hfcsx.nt_timer = 0;
 614		spin_unlock_irqrestore(&cs->lock, flags);
 615		cs->stlist->l2.l2l1 = dch_nt_l2l1;
 616		debugl1(cs, "NT mode activated");
 617		return (0);
 618	}
 619	if ((cs->chanlimit > 1) || (cs->hw.hfcsx.bswapped) ||
 620	    (cs->hw.hfcsx.nt_mode) || (ic->arg != 12))
 621		return (-EINVAL);
 622
 623	if (i) {
 624		cs->logecho = 1;
 625		cs->hw.hfcsx.trm |= 0x20;	/* enable echo chan */
 626		cs->hw.hfcsx.int_m1 |= HFCSX_INTS_B2REC;
 627		/* reset Channel !!!!! */
 628	} else {
 629		cs->logecho = 0;
 630		cs->hw.hfcsx.trm &= ~0x20;	/* disable echo chan */
 631		cs->hw.hfcsx.int_m1 &= ~HFCSX_INTS_B2REC;
 632	}
 633	cs->hw.hfcsx.sctrl_r &= ~SCTRL_B2_ENA;
 634	cs->hw.hfcsx.sctrl &= ~SCTRL_B2_ENA;
 635	cs->hw.hfcsx.conn |= 0x10;	/* B2-IOM -> B2-ST */
 636	cs->hw.hfcsx.ctmt &= ~2;
 637	spin_lock_irqsave(&cs->lock, flags);
 638	Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt);
 639	Write_hfc(cs, HFCSX_SCTRL_R, cs->hw.hfcsx.sctrl_r);
 640	Write_hfc(cs, HFCSX_SCTRL, cs->hw.hfcsx.sctrl);
 641	Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn);
 642	Write_hfc(cs, HFCSX_TRM, cs->hw.hfcsx.trm);
 643	Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
 644	spin_unlock_irqrestore(&cs->lock, flags);
 645	return (0);
 646}				/* hfcsx_auxcmd */
 647
 648/*****************************/
 649/* E-channel receive routine */
 650/*****************************/
 651static void
 652receive_emsg(struct IsdnCardState *cs)
 653{
 654	int count = 5;
 655	u_char *ptr;
 656	struct sk_buff *skb;
 657
 658	if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
 659		debugl1(cs, "echo_rec_data blocked");
 660		return;
 661	}
 662	do {
 663		skb = read_fifo(cs, HFCSX_SEL_B2_RX, 0);
 664		if (skb) {
 665			if (cs->debug & DEB_DLOG_HEX) {
 666				ptr = cs->dlog;
 667				if ((skb->len) < MAX_DLOG_SPACE / 3 - 10) {
 668					*ptr++ = 'E';
 669					*ptr++ = 'C';
 670					*ptr++ = 'H';
 671					*ptr++ = 'O';
 672					*ptr++ = ':';
 673					ptr += QuickHex(ptr, skb->data, skb->len);
 674					ptr--;
 675					*ptr++ = '\n';
 676					*ptr = 0;
 677					HiSax_putstatus(cs, NULL, cs->dlog);
 678				} else
 679					HiSax_putstatus(cs, "LogEcho: ", "warning Frame too big (%d)", skb->len);
 680			}
 681			dev_kfree_skb_any(skb);
 682		}
 683	} while (--count && skb);
 684
 685	test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
 686	return;
 687}				/* receive_emsg */
 688
 689
 690/*********************/
 691/* Interrupt handler */
 692/*********************/
 693static irqreturn_t
 694hfcsx_interrupt(int intno, void *dev_id)
 695{
 696	struct IsdnCardState *cs = dev_id;
 697	u_char exval;
 698	struct BCState *bcs;
 699	int count = 15;
 700	u_long flags;
 701	u_char val, stat;
 702
 703	if (!(cs->hw.hfcsx.int_m2 & 0x08))
 704		return IRQ_NONE;		/* not initialised */
 705
 706	spin_lock_irqsave(&cs->lock, flags);
 707	if (HFCSX_ANYINT & (stat = Read_hfc(cs, HFCSX_STATUS))) {
 708		val = Read_hfc(cs, HFCSX_INT_S1);
 709		if (cs->debug & L1_DEB_ISAC)
 710			debugl1(cs, "HFC-SX: stat(%02x) s1(%02x)", stat, val);
 711	} else {
 712		spin_unlock_irqrestore(&cs->lock, flags);
 713		return IRQ_NONE;
 714	}
 715	if (cs->debug & L1_DEB_ISAC)
 716		debugl1(cs, "HFC-SX irq %x %s", val,
 717			test_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags) ?
 718			"locked" : "unlocked");
 719	val &= cs->hw.hfcsx.int_m1;
 720	if (val & 0x40) {	/* state machine irq */
 721		exval = Read_hfc(cs, HFCSX_STATES) & 0xf;
 722		if (cs->debug & L1_DEB_ISAC)
 723			debugl1(cs, "ph_state chg %d->%d", cs->dc.hfcsx.ph_state,
 724				exval);
 725		cs->dc.hfcsx.ph_state = exval;
 726		schedule_event(cs, D_L1STATECHANGE);
 727		val &= ~0x40;
 728	}
 729	if (val & 0x80) {	/* timer irq */
 730		if (cs->hw.hfcsx.nt_mode) {
 731			if ((--cs->hw.hfcsx.nt_timer) < 0)
 732				schedule_event(cs, D_L1STATECHANGE);
 733		}
 734		val &= ~0x80;
 735		Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt | HFCSX_CLTIMER);
 736	}
 737	while (val) {
 738		if (test_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
 739			cs->hw.hfcsx.int_s1 |= val;
 740			spin_unlock_irqrestore(&cs->lock, flags);
 741			return IRQ_HANDLED;
 742		}
 743		if (cs->hw.hfcsx.int_s1 & 0x18) {
 744			exval = val;
 745			val = cs->hw.hfcsx.int_s1;
 746			cs->hw.hfcsx.int_s1 = exval;
 747		}
 748		if (val & 0x08) {
 749			if (!(bcs = Sel_BCS(cs, cs->hw.hfcsx.bswapped ? 1 : 0))) {
 750				if (cs->debug)
 751					debugl1(cs, "hfcsx spurious 0x08 IRQ");
 752			} else
 753				main_rec_hfcsx(bcs);
 754		}
 755		if (val & 0x10) {
 756			if (cs->logecho)
 757				receive_emsg(cs);
 758			else if (!(bcs = Sel_BCS(cs, 1))) {
 759				if (cs->debug)
 760					debugl1(cs, "hfcsx spurious 0x10 IRQ");
 761			} else
 762				main_rec_hfcsx(bcs);
 763		}
 764		if (val & 0x01) {
 765			if (!(bcs = Sel_BCS(cs, cs->hw.hfcsx.bswapped ? 1 : 0))) {
 766				if (cs->debug)
 767					debugl1(cs, "hfcsx spurious 0x01 IRQ");
 768			} else {
 769				if (bcs->tx_skb) {
 770					if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
 771						hfcsx_fill_fifo(bcs);
 772						test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
 773					} else
 774						debugl1(cs, "fill_data %d blocked", bcs->channel);
 775				} else {
 776					if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
 777						if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
 778							hfcsx_fill_fifo(bcs);
 779							test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
 780						} else
 781							debugl1(cs, "fill_data %d blocked", bcs->channel);
 782					} else {
 783						schedule_event(bcs, B_XMTBUFREADY);
 784					}
 785				}
 786			}
 787		}
 788		if (val & 0x02) {
 789			if (!(bcs = Sel_BCS(cs, 1))) {
 790				if (cs->debug)
 791					debugl1(cs, "hfcsx spurious 0x02 IRQ");
 792			} else {
 793				if (bcs->tx_skb) {
 794					if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
 795						hfcsx_fill_fifo(bcs);
 796						test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
 797					} else
 798						debugl1(cs, "fill_data %d blocked", bcs->channel);
 799				} else {
 800					if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
 801						if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
 802							hfcsx_fill_fifo(bcs);
 803							test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
 804						} else
 805							debugl1(cs, "fill_data %d blocked", bcs->channel);
 806					} else {
 807						schedule_event(bcs, B_XMTBUFREADY);
 808					}
 809				}
 810			}
 811		}
 812		if (val & 0x20) {	/* receive dframe */
 813			receive_dmsg(cs);
 814		}
 815		if (val & 0x04) {	/* dframe transmitted */
 816			if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
 817				del_timer(&cs->dbusytimer);
 818			if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
 819				schedule_event(cs, D_CLEARBUSY);
 820			if (cs->tx_skb) {
 821				if (cs->tx_skb->len) {
 822					if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
 823						hfcsx_fill_dfifo(cs);
 824						test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
 825					} else {
 826						debugl1(cs, "hfcsx_fill_dfifo irq blocked");
 827					}
 828					goto afterXPR;
 829				} else {
 830					dev_kfree_skb_irq(cs->tx_skb);
 831					cs->tx_cnt = 0;
 832					cs->tx_skb = NULL;
 833				}
 834			}
 835			if ((cs->tx_skb = skb_dequeue(&cs->sq))) {
 836				cs->tx_cnt = 0;
 837				if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
 838					hfcsx_fill_dfifo(cs);
 839					test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
 840				} else {
 841					debugl1(cs, "hfcsx_fill_dfifo irq blocked");
 842				}
 843			} else
 844				schedule_event(cs, D_XMTBUFREADY);
 845		}
 846	afterXPR:
 847		if (cs->hw.hfcsx.int_s1 && count--) {
 848			val = cs->hw.hfcsx.int_s1;
 849			cs->hw.hfcsx.int_s1 = 0;
 850			if (cs->debug & L1_DEB_ISAC)
 851				debugl1(cs, "HFC-SX irq %x loop %d", val, 15 - count);
 852		} else
 853			val = 0;
 854	}
 855	spin_unlock_irqrestore(&cs->lock, flags);
 856	return IRQ_HANDLED;
 857}
 858
 859/********************************************************************/
 860/* timer callback for D-chan busy resolution. Currently no function */
 861/********************************************************************/
 862static void
 863hfcsx_dbusy_timer(struct IsdnCardState *cs)
 864{
 865}
 866
 867/*************************************/
 868/* Layer 1 D-channel hardware access */
 869/*************************************/
 870static void
 871HFCSX_l1hw(struct PStack *st, int pr, void *arg)
 872{
 873	struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware;
 874	struct sk_buff *skb = arg;
 875	u_long flags;
 876
 877	switch (pr) {
 878	case (PH_DATA | REQUEST):
 879		if (cs->debug & DEB_DLOG_HEX)
 880			LogFrame(cs, skb->data, skb->len);
 881		if (cs->debug & DEB_DLOG_VERBOSE)
 882			dlogframe(cs, skb, 0);
 883		spin_lock_irqsave(&cs->lock, flags);
 884		if (cs->tx_skb) {
 885			skb_queue_tail(&cs->sq, skb);
 886#ifdef L2FRAME_DEBUG		/* psa */
 887			if (cs->debug & L1_DEB_LAPD)
 888				Logl2Frame(cs, skb, "PH_DATA Queued", 0);
 889#endif
 890		} else {
 891			cs->tx_skb = skb;
 892			cs->tx_cnt = 0;
 893#ifdef L2FRAME_DEBUG		/* psa */
 894			if (cs->debug & L1_DEB_LAPD)
 895				Logl2Frame(cs, skb, "PH_DATA", 0);
 896#endif
 897			if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
 898				hfcsx_fill_dfifo(cs);
 899				test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
 900			} else
 901				debugl1(cs, "hfcsx_fill_dfifo blocked");
 902
 903		}
 904		spin_unlock_irqrestore(&cs->lock, flags);
 905		break;
 906	case (PH_PULL | INDICATION):
 907		spin_lock_irqsave(&cs->lock, flags);
 908		if (cs->tx_skb) {
 909			if (cs->debug & L1_DEB_WARN)
 910				debugl1(cs, " l2l1 tx_skb exist this shouldn't happen");
 911			skb_queue_tail(&cs->sq, skb);
 912			spin_unlock_irqrestore(&cs->lock, flags);
 913			break;
 914		}
 915		if (cs->debug & DEB_DLOG_HEX)
 916			LogFrame(cs, skb->data, skb->len);
 917		if (cs->debug & DEB_DLOG_VERBOSE)
 918			dlogframe(cs, skb, 0);
 919		cs->tx_skb = skb;
 920		cs->tx_cnt = 0;
 921#ifdef L2FRAME_DEBUG		/* psa */
 922		if (cs->debug & L1_DEB_LAPD)
 923			Logl2Frame(cs, skb, "PH_DATA_PULLED", 0);
 924#endif
 925		if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
 926			hfcsx_fill_dfifo(cs);
 927			test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
 928		} else
 929			debugl1(cs, "hfcsx_fill_dfifo blocked");
 930		spin_unlock_irqrestore(&cs->lock, flags);
 931		break;
 932	case (PH_PULL | REQUEST):
 933#ifdef L2FRAME_DEBUG		/* psa */
 934		if (cs->debug & L1_DEB_LAPD)
 935			debugl1(cs, "-> PH_REQUEST_PULL");
 936#endif
 937		if (!cs->tx_skb) {
 938			test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
 939			st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
 940		} else
 941			test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
 942		break;
 943	case (HW_RESET | REQUEST):
 944		spin_lock_irqsave(&cs->lock, flags);
 945		Write_hfc(cs, HFCSX_STATES, HFCSX_LOAD_STATE | 3);	/* HFC ST 3 */
 946		udelay(6);
 947		Write_hfc(cs, HFCSX_STATES, 3);	/* HFC ST 2 */
 948		cs->hw.hfcsx.mst_m |= HFCSX_MASTER;
 949		Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m);
 950		Write_hfc(cs, HFCSX_STATES, HFCSX_ACTIVATE | HFCSX_DO_ACTION);
 951		spin_unlock_irqrestore(&cs->lock, flags);
 952		l1_msg(cs, HW_POWERUP | CONFIRM, NULL);
 953		break;
 954	case (HW_ENABLE | REQUEST):
 955		spin_lock_irqsave(&cs->lock, flags);
 956		Write_hfc(cs, HFCSX_STATES, HFCSX_ACTIVATE | HFCSX_DO_ACTION);
 957		spin_unlock_irqrestore(&cs->lock, flags);
 958		break;
 959	case (HW_DEACTIVATE | REQUEST):
 960		spin_lock_irqsave(&cs->lock, flags);
 961		cs->hw.hfcsx.mst_m &= ~HFCSX_MASTER;
 962		Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m);
 963		spin_unlock_irqrestore(&cs->lock, flags);
 964		break;
 965	case (HW_INFO3 | REQUEST):
 966		spin_lock_irqsave(&cs->lock, flags);
 967		cs->hw.hfcsx.mst_m |= HFCSX_MASTER;
 968		Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m);
 969		spin_unlock_irqrestore(&cs->lock, flags);
 970		break;
 971	case (HW_TESTLOOP | REQUEST):
 972		spin_lock_irqsave(&cs->lock, flags);
 973		switch ((long) arg) {
 974		case (1):
 975			Write_hfc(cs, HFCSX_B1_SSL, 0x80);	/* tx slot */
 976			Write_hfc(cs, HFCSX_B1_RSL, 0x80);	/* rx slot */
 977			cs->hw.hfcsx.conn = (cs->hw.hfcsx.conn & ~7) | 1;
 978			Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn);
 979			break;
 980		case (2):
 981			Write_hfc(cs, HFCSX_B2_SSL, 0x81);	/* tx slot */
 982			Write_hfc(cs, HFCSX_B2_RSL, 0x81);	/* rx slot */
 983			cs->hw.hfcsx.conn = (cs->hw.hfcsx.conn & ~0x38) | 0x08;
 984			Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn);
 985			break;
 986		default:
 987			spin_unlock_irqrestore(&cs->lock, flags);
 988			if (cs->debug & L1_DEB_WARN)
 989				debugl1(cs, "hfcsx_l1hw loop invalid %4lx", (unsigned long)arg);
 990			return;
 991		}
 992		cs->hw.hfcsx.trm |= 0x80;	/* enable IOM-loop */
 993		Write_hfc(cs, HFCSX_TRM, cs->hw.hfcsx.trm);
 994		spin_unlock_irqrestore(&cs->lock, flags);
 995		break;
 996	default:
 997		if (cs->debug & L1_DEB_WARN)
 998			debugl1(cs, "hfcsx_l1hw unknown pr %4x", pr);
 999		break;
1000	}
1001}
1002
1003/***********************************************/
1004/* called during init setting l1 stack pointer */
1005/***********************************************/
1006static void
1007setstack_hfcsx(struct PStack *st, struct IsdnCardState *cs)
1008{
1009	st->l1.l1hw = HFCSX_l1hw;
1010}
1011
1012/**************************************/
1013/* send B-channel data if not blocked */
1014/**************************************/
1015static void
1016hfcsx_send_data(struct BCState *bcs)
1017{
1018	struct IsdnCardState *cs = bcs->cs;
1019
1020	if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1021		hfcsx_fill_fifo(bcs);
1022		test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1023	} else
1024		debugl1(cs, "send_data %d blocked", bcs->channel);
1025}
1026
1027/***************************************************************/
1028/* activate/deactivate hardware for selected channels and mode */
1029/***************************************************************/
1030static void
1031mode_hfcsx(struct BCState *bcs, int mode, int bc)
1032{
1033	struct IsdnCardState *cs = bcs->cs;
1034	int fifo2;
1035
1036	if (cs->debug & L1_DEB_HSCX)
1037		debugl1(cs, "HFCSX bchannel mode %d bchan %d/%d",
1038			mode, bc, bcs->channel);
1039	bcs->mode = mode;
1040	bcs->channel = bc;
1041	fifo2 = bc;
1042	if (cs->chanlimit > 1) {
1043		cs->hw.hfcsx.bswapped = 0;	/* B1 and B2 normal mode */
1044		cs->hw.hfcsx.sctrl_e &= ~0x80;
1045	} else {
1046		if (bc) {
1047			if (mode != L1_MODE_NULL) {
1048				cs->hw.hfcsx.bswapped = 1;	/* B1 and B2 exchanged */
1049				cs->hw.hfcsx.sctrl_e |= 0x80;
1050			} else {
1051				cs->hw.hfcsx.bswapped = 0;	/* B1 and B2 normal mode */
1052				cs->hw.hfcsx.sctrl_e &= ~0x80;
1053			}
1054			fifo2 = 0;
1055		} else {
1056			cs->hw.hfcsx.bswapped = 0;	/* B1 and B2 normal mode */
1057			cs->hw.hfcsx.sctrl_e &= ~0x80;
1058		}
1059	}
1060	switch (mode) {
1061	case (L1_MODE_NULL):
1062		if (bc) {
1063			cs->hw.hfcsx.sctrl &= ~SCTRL_B2_ENA;
1064			cs->hw.hfcsx.sctrl_r &= ~SCTRL_B2_ENA;
1065		} else {
1066			cs->hw.hfcsx.sctrl &= ~SCTRL_B1_ENA;
1067			cs->hw.hfcsx.sctrl_r &= ~SCTRL_B1_ENA;
1068		}
1069		if (fifo2) {
1070			cs->hw.hfcsx.int_m1 &= ~(HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC);
1071		} else {
1072			cs->hw.hfcsx.int_m1 &= ~(HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC);
1073		}
1074		break;
1075	case (L1_MODE_TRANS):
1076		if (bc) {
1077			cs->hw.hfcsx.sctrl |= SCTRL_B2_ENA;
1078			cs->hw.hfcsx.sctrl_r |= SCTRL_B2_ENA;
1079		} else {
1080			cs->hw.hfcsx.sctrl |= SCTRL_B1_ENA;
1081			cs->hw.hfcsx.sctrl_r |= SCTRL_B1_ENA;
1082		}
1083		if (fifo2) {
1084			cs->hw.hfcsx.int_m1 |= (HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC);
1085			cs->hw.hfcsx.ctmt |= 2;
1086			cs->hw.hfcsx.conn &= ~0x18;
1087		} else {
1088			cs->hw.hfcsx.int_m1 |= (HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC);
1089			cs->hw.hfcsx.ctmt |= 1;
1090			cs->hw.hfcsx.conn &= ~0x03;
1091		}
1092		break;
1093	case (L1_MODE_HDLC):
1094		if (bc) {
1095			cs->hw.hfcsx.sctrl |= SCTRL_B2_ENA;
1096			cs->hw.hfcsx.sctrl_r |= SCTRL_B2_ENA;
1097		} else {
1098			cs->hw.hfcsx.sctrl |= SCTRL_B1_ENA;
1099			cs->hw.hfcsx.sctrl_r |= SCTRL_B1_ENA;
1100		}
1101		if (fifo2) {
1102			cs->hw.hfcsx.int_m1 |= (HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC);
1103			cs->hw.hfcsx.ctmt &= ~2;
1104			cs->hw.hfcsx.conn &= ~0x18;
1105		} else {
1106			cs->hw.hfcsx.int_m1 |= (HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC);
1107			cs->hw.hfcsx.ctmt &= ~1;
1108			cs->hw.hfcsx.conn &= ~0x03;
1109		}
1110		break;
1111	case (L1_MODE_EXTRN):
1112		if (bc) {
1113			cs->hw.hfcsx.conn |= 0x10;
1114			cs->hw.hfcsx.sctrl |= SCTRL_B2_ENA;
1115			cs->hw.hfcsx.sctrl_r |= SCTRL_B2_ENA;
1116			cs->hw.hfcsx.int_m1 &= ~(HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC);
1117		} else {
1118			cs->hw.hfcsx.conn |= 0x02;
1119			cs->hw.hfcsx.sctrl |= SCTRL_B1_ENA;
1120			cs->hw.hfcsx.sctrl_r |= SCTRL_B1_ENA;
1121			cs->hw.hfcsx.int_m1 &= ~(HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC);
1122		}
1123		break;
1124	}
1125	Write_hfc(cs, HFCSX_SCTRL_E, cs->hw.hfcsx.sctrl_e);
1126	Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
1127	Write_hfc(cs, HFCSX_SCTRL, cs->hw.hfcsx.sctrl);
1128	Write_hfc(cs, HFCSX_SCTRL_R, cs->hw.hfcsx.sctrl_r);
1129	Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt);
1130	Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn);
1131	if (mode != L1_MODE_EXTRN) {
1132		reset_fifo(cs, fifo2 ? HFCSX_SEL_B2_RX : HFCSX_SEL_B1_RX);
1133		reset_fifo(cs, fifo2 ? HFCSX_SEL_B2_TX : HFCSX_SEL_B1_TX);
1134	}
1135}
1136
1137/******************************/
1138/* Layer2 -> Layer 1 Transfer */
1139/******************************/
1140static void
1141hfcsx_l2l1(struct PStack *st, int pr, void *arg)
1142{
1143	struct BCState *bcs = st->l1.bcs;
1144	struct sk_buff *skb = arg;
1145	u_long flags;
1146
1147	switch (pr) {
1148	case (PH_DATA | REQUEST):
1149		spin_lock_irqsave(&bcs->cs->lock, flags);
1150		if (bcs->tx_skb) {
1151			skb_queue_tail(&bcs->squeue, skb);
1152		} else {
1153			bcs->tx_skb = skb;
1154//                              test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
1155			bcs->cs->BC_Send_Data(bcs);
1156		}
1157		spin_unlock_irqrestore(&bcs->cs->lock, flags);
1158		break;
1159	case (PH_PULL | INDICATION):
1160		spin_lock_irqsave(&bcs->cs->lock, flags);
1161		if (bcs->tx_skb) {
1162			printk(KERN_WARNING "%s: this shouldn't happen\n",
1163			       __func__);
1164		} else {
1165//				test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
1166			bcs->tx_skb = skb;
1167			bcs->cs->BC_Send_Data(bcs);
1168		}
1169		spin_unlock_irqrestore(&bcs->cs->lock, flags);
1170		break;
1171	case (PH_PULL | REQUEST):
1172		if (!bcs->tx_skb) {
1173			test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
1174			st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
1175		} else
1176			test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
1177		break;
1178	case (PH_ACTIVATE | REQUEST):
1179		spin_lock_irqsave(&bcs->cs->lock, flags);
1180		test_and_set_bit(BC_FLG_ACTIV, &bcs->Flag);
1181		mode_hfcsx(bcs, st->l1.mode, st->l1.bc);
1182		spin_unlock_irqrestore(&bcs->cs->lock, flags);
1183		l1_msg_b(st, pr, arg);
1184		break;
1185	case (PH_DEACTIVATE | REQUEST):
1186		l1_msg_b(st, pr, arg);
1187		break;
1188	case (PH_DEACTIVATE | CONFIRM):
1189		spin_lock_irqsave(&bcs->cs->lock, flags);
1190		test_and_clear_bit(BC_FLG_ACTIV, &bcs->Flag);
1191		test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
1192		mode_hfcsx(bcs, 0, st->l1.bc);
1193		spin_unlock_irqrestore(&bcs->cs->lock, flags);
1194		st->l1.l1l2(st, PH_DEACTIVATE | CONFIRM, NULL);
1195		break;
1196	}
1197}
1198
1199/******************************************/
1200/* deactivate B-channel access and queues */
1201/******************************************/
1202static void
1203close_hfcsx(struct BCState *bcs)
1204{
1205	mode_hfcsx(bcs, 0, bcs->channel);
1206	if (test_and_clear_bit(BC_FLG_INIT, &bcs->Flag)) {
1207		skb_queue_purge(&bcs->rqueue);
1208		skb_queue_purge(&bcs->squeue);
1209		if (bcs->tx_skb) {
1210			dev_kfree_skb_any(bcs->tx_skb);
1211			bcs->tx_skb = NULL;
1212			test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
1213		}
1214	}
1215}
1216
1217/*************************************/
1218/* init B-channel queues and control */
1219/*************************************/
1220static int
1221open_hfcsxstate(struct IsdnCardState *cs, struct BCState *bcs)
1222{
1223	if (!test_and_set_bit(BC_FLG_INIT, &bcs->Flag)) {
1224		skb_queue_head_init(&bcs->rqueue);
1225		skb_queue_head_init(&bcs->squeue);
1226	}
1227	bcs->tx_skb = NULL;
1228	test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
1229	bcs->event = 0;
1230	bcs->tx_cnt = 0;
1231	return (0);
1232}
1233
1234/*********************************/
1235/* inits the stack for B-channel */
1236/*********************************/
1237static int
1238setstack_2b(struct PStack *st, struct BCState *bcs)
1239{
1240	bcs->channel = st->l1.bc;
1241	if (open_hfcsxstate(st->l1.hardware, bcs))
1242		return (-1);
1243	st->l1.bcs = bcs;
1244	st->l2.l2l1 = hfcsx_l2l1;
1245	setstack_manager(st);
1246	bcs->st = st;
1247	setstack_l1_B(st);
1248	return (0);
1249}
1250
1251/***************************/
1252/* handle L1 state changes */
1253/***************************/
1254static void
1255hfcsx_bh(struct work_struct *work)
1256{
1257	struct IsdnCardState *cs =
1258		container_of(work, struct IsdnCardState, tqueue);
1259	u_long flags;
1260
1261	if (test_and_clear_bit(D_L1STATECHANGE, &cs->event)) {
1262		if (!cs->hw.hfcsx.nt_mode)
1263			switch (cs->dc.hfcsx.ph_state) {
1264			case (0):
1265				l1_msg(cs, HW_RESET | INDICATION, NULL);
1266				break;
1267			case (3):
1268				l1_msg(cs, HW_DEACTIVATE | INDICATION, NULL);
1269				break;
1270			case (8):
1271				l1_msg(cs, HW_RSYNC | INDICATION, NULL);
1272				break;
1273			case (6):
1274				l1_msg(cs, HW_INFO2 | INDICATION, NULL);
1275				break;
1276			case (7):
1277				l1_msg(cs, HW_INFO4_P8 | INDICATION, NULL);
1278				break;
1279			default:
1280				break;
1281			} else {
1282			switch (cs->dc.hfcsx.ph_state) {
1283			case (2):
1284				spin_lock_irqsave(&cs->lock, flags);
1285				if (cs->hw.hfcsx.nt_timer < 0) {
1286					cs->hw.hfcsx.nt_timer = 0;
1287					cs->hw.hfcsx.int_m1 &= ~HFCSX_INTS_TIMER;
1288					Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
1289					/* Clear already pending ints */
1290					if (Read_hfc(cs, HFCSX_INT_S1));
1291
1292					Write_hfc(cs, HFCSX_STATES, 4 | HFCSX_LOAD_STATE);
1293					udelay(10);
1294					Write_hfc(cs, HFCSX_STATES, 4);
1295					cs->dc.hfcsx.ph_state = 4;
1296				} else {
1297					cs->hw.hfcsx.int_m1 |= HFCSX_INTS_TIMER;
1298					Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
1299					cs->hw.hfcsx.ctmt &= ~HFCSX_AUTO_TIMER;
1300					cs->hw.hfcsx.ctmt |= HFCSX_TIM3_125;
1301					Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt | HFCSX_CLTIMER);
1302					Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt | HFCSX_CLTIMER);
1303					cs->hw.hfcsx.nt_timer = NT_T1_COUNT;
1304					Write_hfc(cs, HFCSX_STATES, 2 | HFCSX_NT_G2_G3);	/* allow G2 -> G3 transition */
1305				}
1306				spin_unlock_irqrestore(&cs->lock, flags);
1307				break;
1308			case (1):
1309			case (3):
1310			case (4):
1311				spin_lock_irqsave(&cs->lock, flags);
1312				cs->hw.hfcsx.nt_timer = 0;
1313				cs->hw.hfcsx.int_m1 &= ~HFCSX_INTS_TIMER;
1314				Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
1315				spin_unlock_irqrestore(&cs->lock, flags);
1316				break;
1317			default:
1318				break;
1319			}
1320		}
1321	}
1322	if (test_and_clear_bit(D_RCVBUFREADY, &cs->event))
1323		DChannel_proc_rcv(cs);
1324	if (test_and_clear_bit(D_XMTBUFREADY, &cs->event))
1325		DChannel_proc_xmt(cs);
1326}
1327
1328
1329/********************************/
1330/* called for card init message */
1331/********************************/
1332static void inithfcsx(struct IsdnCardState *cs)
1333{
1334	cs->setstack_d = setstack_hfcsx;
1335	cs->BC_Send_Data = &hfcsx_send_data;
1336	cs->bcs[0].BC_SetStack = setstack_2b;
1337	cs->bcs[1].BC_SetStack = setstack_2b;
1338	cs->bcs[0].BC_Close = close_hfcsx;
1339	cs->bcs[1].BC_Close = close_hfcsx;
1340	mode_hfcsx(cs->bcs, 0, 0);
1341	mode_hfcsx(cs->bcs + 1, 0, 1);
1342}
1343
1344
1345
1346/*******************************************/
1347/* handle card messages from control layer */
1348/*******************************************/
1349static int
1350hfcsx_card_msg(struct IsdnCardState *cs, int mt, void *arg)
1351{
1352	u_long flags;
1353
1354	if (cs->debug & L1_DEB_ISAC)
1355		debugl1(cs, "HFCSX: card_msg %x", mt);
1356	switch (mt) {
1357	case CARD_RESET:
1358		spin_lock_irqsave(&cs->lock, flags);
1359		reset_hfcsx(cs);
1360		spin_unlock_irqrestore(&cs->lock, flags);
1361		return (0);
1362	case CARD_RELEASE:
1363		release_io_hfcsx(cs);
1364		return (0);
1365	case CARD_INIT:
1366		spin_lock_irqsave(&cs->lock, flags);
1367		inithfcsx(cs);
1368		spin_unlock_irqrestore(&cs->lock, flags);
1369		msleep(80);				/* Timeout 80ms */
1370		/* now switch timer interrupt off */
1371		spin_lock_irqsave(&cs->lock, flags);
1372		cs->hw.hfcsx.int_m1 &= ~HFCSX_INTS_TIMER;
1373		Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
1374		/* reinit mode reg */
1375		Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m);
1376		spin_unlock_irqrestore(&cs->lock, flags);
1377		return (0);
1378	case CARD_TEST:
1379		return (0);
1380	}
1381	return (0);
1382}
1383
1384#ifdef __ISAPNP__
1385static struct isapnp_device_id hfc_ids[] = {
1386	{ ISAPNP_VENDOR('T', 'A', 'G'), ISAPNP_FUNCTION(0x2620),
1387	  ISAPNP_VENDOR('T', 'A', 'G'), ISAPNP_FUNCTION(0x2620),
1388	  (unsigned long) "Teles 16.3c2" },
1389	{ 0, }
1390};
1391
1392static struct isapnp_device_id *ipid = &hfc_ids[0];
1393static struct pnp_card *pnp_c = NULL;
1394#endif
1395
1396int setup_hfcsx(struct IsdnCard *card)
1397{
1398	struct IsdnCardState *cs = card->cs;
1399	char tmp[64];
1400
1401	strcpy(tmp, hfcsx_revision);
1402	printk(KERN_INFO "HiSax: HFC-SX driver Rev. %s\n", HiSax_getrev(tmp));
1403#ifdef __ISAPNP__
1404	if (!card->para[1] && isapnp_present()) {
1405		struct pnp_dev *pnp_d;
1406		while (ipid->card_vendor) {
1407			if ((pnp_c = pnp_find_card(ipid->card_vendor,
1408						   ipid->card_device, pnp_c))) {
1409				pnp_d = NULL;
1410				if ((pnp_d = pnp_find_dev(pnp_c,
1411							  ipid->vendor, ipid->function, pnp_d))) {
1412					int err;
1413
1414					printk(KERN_INFO "HiSax: %s detected\n",
1415					       (char *)ipid->driver_data);
1416					pnp_disable_dev(pnp_d);
1417					err = pnp_activate_dev(pnp_d);
1418					if (err < 0) {
1419						printk(KERN_WARNING "%s: pnp_activate_dev ret(%d)\n",
1420						       __func__, err);
1421						return (0);
1422					}
1423					card->para[1] = pnp_port_start(pnp_d, 0);
1424					card->para[0] = pnp_irq(pnp_d, 0);
1425					if (!card->para[0] || !card->para[1]) {
1426						printk(KERN_ERR "HFC PnP:some resources are missing %ld/%lx\n",
1427						       card->para[0], card->para[1]);
1428						pnp_disable_dev(pnp_d);
1429						return (0);
1430					}
1431					break;
1432				} else {
1433					printk(KERN_ERR "HFC PnP: PnP error card found, no device\n");
1434				}
1435			}
1436			ipid++;
1437			pnp_c = NULL;
1438		}
1439		if (!ipid->card_vendor) {
1440			printk(KERN_INFO "HFC PnP: no ISAPnP card found\n");
1441			return (0);
1442		}
1443	}
1444#endif
1445	cs->hw.hfcsx.base = card->para[1] & 0xfffe;
1446	cs->irq = card->para[0];
1447	cs->hw.hfcsx.int_s1 = 0;
1448	cs->dc.hfcsx.ph_state = 0;
1449	cs->hw.hfcsx.fifo = 255;
1450	if ((cs->typ == ISDN_CTYPE_HFC_SX) ||
1451	    (cs->typ == ISDN_CTYPE_HFC_SP_PCMCIA)) {
1452		if ((!cs->hw.hfcsx.base) || !request_region(cs->hw.hfcsx.base, 2, "HFCSX isdn")) {
1453			printk(KERN_WARNING
1454			       "HiSax: HFC-SX io-base %#lx already in use\n",
1455			       cs->hw.hfcsx.base);
1456			return (0);
1457		}
1458		byteout(cs->hw.hfcsx.base, cs->hw.hfcsx.base & 0xFF);
1459		byteout(cs->hw.hfcsx.base + 1,
1460			((cs->hw.hfcsx.base >> 8) & 3) | 0x54);
1461		udelay(10);
1462		cs->hw.hfcsx.chip = Read_hfc(cs, HFCSX_CHIP_ID);
1463		switch (cs->hw.hfcsx.chip >> 4) {
1464		case 1:
1465			tmp[0] = '+';
1466			break;
1467		case 9:
1468			tmp[0] = 'P';
1469			break;
1470		default:
1471			printk(KERN_WARNING
1472			       "HFC-SX: invalid chip id 0x%x\n",
1473			       cs->hw.hfcsx.chip >> 4);
1474			release_region(cs->hw.hfcsx.base, 2);
1475			return (0);
1476		}
1477		if (!ccd_sp_irqtab[cs->irq & 0xF]) {
1478			printk(KERN_WARNING
1479			       "HFC_SX: invalid irq %d specified\n", cs->irq & 0xF);
1480			release_region(cs->hw.hfcsx.base, 2);
1481			return (0);
1482		}
1483		if (!(cs->hw.hfcsx.extra =
1484		      kmalloc(sizeof(struct hfcsx_extra), GFP_ATOMIC))) {
1485			release_region(cs->hw.hfcsx.base, 2);
1486			printk(KERN_WARNING "HFC-SX: unable to allocate memory\n");
1487			return (0);
1488		}
1489		printk(KERN_INFO "HFC-S%c chip detected at base 0x%x IRQ %d HZ %d\n",
1490		       tmp[0], (u_int) cs->hw.hfcsx.base, cs->irq, HZ);
1491		cs->hw.hfcsx.int_m2 = 0;	/* disable alle interrupts */
1492		cs->hw.hfcsx.int_m1 = 0;
1493		Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
1494		Write_hfc(cs, HFCSX_INT_M2, cs->hw.hfcsx.int_m2);
1495	} else
1496		return (0);	/* no valid card type */
1497
1498	cs->dbusytimer.function = (void *) hfcsx_dbusy_timer;
1499	cs->dbusytimer.data = (long) cs;
1500	init_timer(&cs->dbusytimer);
1501	INIT_WORK(&cs->tqueue, hfcsx_bh);
1502	cs->readisac = NULL;
1503	cs->writeisac = NULL;
1504	cs->readisacfifo = NULL;
1505	cs->writeisacfifo = NULL;
1506	cs->BC_Read_Reg = NULL;
1507	cs->BC_Write_Reg = NULL;
1508	cs->irq_func = &hfcsx_interrupt;
1509
1510	cs->hw.hfcsx.timer.function = (void *) hfcsx_Timer;
1511	cs->hw.hfcsx.timer.data = (long) cs;
1512	cs->hw.hfcsx.b_fifo_size = 0; /* fifo size still unknown */
1513	cs->hw.hfcsx.cirm = ccd_sp_irqtab[cs->irq & 0xF]; /* RAM not evaluated */
1514	init_timer(&cs->hw.hfcsx.timer);
1515
1516	reset_hfcsx(cs);
1517	cs->cardmsg = &hfcsx_card_msg;
1518	cs->auxcmd = &hfcsx_auxcmd;
1519	return (1);
1520}