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/drivers/isdn/hisax/hfc4s8s_l1.h

http://github.com/mirrors/linux
C++ Header | 88 lines | 62 code | 9 blank | 17 comment | 0 complexity | 75070042e67e6730db27d720f9255ab2 MD5 | raw file
 1/***************************************************************/
 2/*  $Id: hfc4s8s_l1.h,v 1.1 2005/02/02 17:28:55 martinb1 Exp $ */
 3/*                                                             */
 4/*  This file is a minimal required extraction of hfc48scu.h   */
 5/*  (Genero 3.2, HFC XML 1.7a for HFC-E1, HFC-4S and HFC-8S)   */
 6/*                                                             */
 7/*  To get this complete register description contact          */
 8/*  Cologne Chip AG :                                          */
 9/*  Internet:  http://www.colognechip.com/                     */
10/*  E-Mail:    info@colognechip.com                            */
11/***************************************************************/
12
13#ifndef _HFC4S8S_L1_H_
14#define _HFC4S8S_L1_H_
15
16
17/*
18 *  include Genero generated HFC-4S/8S header file hfc48scu.h
19 *  for complete register description. This will define _HFC48SCU_H_
20 *  to prevent redefinitions
21 */
22
23// #include "hfc48scu.h"
24
25#ifndef _HFC48SCU_H_
26#define _HFC48SCU_H_
27
28#ifndef PCI_VENDOR_ID_CCD
29#define PCI_VENDOR_ID_CCD	0x1397
30#endif
31
32#define CHIP_ID_4S		0x0C
33#define CHIP_ID_8S		0x08
34#define PCI_DEVICE_ID_4S	0x08B4
35#define PCI_DEVICE_ID_8S	0x16B8
36
37#define R_IRQ_MISC	0x11
38#define M_TI_IRQ	0x02
39#define A_ST_RD_STA	0x30
40#define A_ST_WR_STA	0x30
41#define M_SET_G2_G3	0x80
42#define A_ST_CTRL0	0x31
43#define A_ST_CTRL2	0x33
44#define A_ST_CLK_DLY	0x37
45#define A_Z1		0x04
46#define A_Z2		0x06
47#define R_CIRM		0x00
48#define M_SRES		0x08
49#define R_CTRL		0x01
50#define R_BRG_PCM_CFG	0x02
51#define M_PCM_CLK	0x20
52#define R_RAM_MISC	0x0C
53#define M_FZ_MD		0x80
54#define R_FIFO_MD	0x0D
55#define A_INC_RES_FIFO	0x0E
56#define R_FIFO		0x0F
57#define A_F1		0x0C
58#define A_F2		0x0D
59#define R_IRQ_OVIEW	0x10
60#define R_CHIP_ID	0x16
61#define R_STATUS	0x1C
62#define M_BUSY		0x01
63#define M_MISC_IRQSTA	0x40
64#define M_FR_IRQSTA	0x80
65#define R_CHIP_RV	0x1F
66#define R_IRQ_CTRL	0x13
67#define M_FIFO_IRQ	0x01
68#define M_GLOB_IRQ_EN	0x08
69#define R_PCM_MD0	0x14
70#define M_PCM_MD	0x01
71#define A_FIFO_DATA0	0x80
72#define R_TI_WD		0x1A
73#define R_PWM1		0x39
74#define R_PWM_MD	0x46
75#define R_IRQ_FIFO_BL0	0xC8
76#define A_CON_HDLC	0xFA
77#define A_SUBCH_CFG	0xFB
78#define A_IRQ_MSK	0xFF
79#define R_SCI_MSK	0x12
80#define R_ST_SEL	0x16
81#define R_ST_SYNC	0x17
82#define M_AUTO_SYNC	0x08
83#define R_SCI		0x12
84#define R_IRQMSK_MISC	0x11
85#define M_TI_IRQMSK	0x02
86
87#endif	/* _HFC4S8S_L1_H_ */
88#endif	/* _HFC48SCU_H_ */