/drivers/dma/coh901318.c
C | 2809 lines | 2215 code | 322 blank | 272 comment | 120 complexity | 634f806a110a532eb22bc2bb4cea9280 MD5 | raw file
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1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * driver/dma/coh901318.c 4 * 5 * Copyright (C) 2007-2009 ST-Ericsson 6 * DMA driver for COH 901 318 7 * Author: Per Friden <per.friden@stericsson.com> 8 */ 9 10#include <linux/init.h> 11#include <linux/module.h> 12#include <linux/kernel.h> /* printk() */ 13#include <linux/fs.h> /* everything... */ 14#include <linux/scatterlist.h> 15#include <linux/slab.h> /* kmalloc() */ 16#include <linux/dmaengine.h> 17#include <linux/platform_device.h> 18#include <linux/device.h> 19#include <linux/irqreturn.h> 20#include <linux/interrupt.h> 21#include <linux/io.h> 22#include <linux/uaccess.h> 23#include <linux/debugfs.h> 24#include <linux/platform_data/dma-coh901318.h> 25#include <linux/of_dma.h> 26 27#include "coh901318.h" 28#include "dmaengine.h" 29 30#define COH901318_MOD32_MASK (0x1F) 31#define COH901318_WORD_MASK (0xFFFFFFFF) 32/* INT_STATUS - Interrupt Status Registers 32bit (R/-) */ 33#define COH901318_INT_STATUS1 (0x0000) 34#define COH901318_INT_STATUS2 (0x0004) 35/* TC_INT_STATUS - Terminal Count Interrupt Status Registers 32bit (R/-) */ 36#define COH901318_TC_INT_STATUS1 (0x0008) 37#define COH901318_TC_INT_STATUS2 (0x000C) 38/* TC_INT_CLEAR - Terminal Count Interrupt Clear Registers 32bit (-/W) */ 39#define COH901318_TC_INT_CLEAR1 (0x0010) 40#define COH901318_TC_INT_CLEAR2 (0x0014) 41/* RAW_TC_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */ 42#define COH901318_RAW_TC_INT_STATUS1 (0x0018) 43#define COH901318_RAW_TC_INT_STATUS2 (0x001C) 44/* BE_INT_STATUS - Bus Error Interrupt Status Registers 32bit (R/-) */ 45#define COH901318_BE_INT_STATUS1 (0x0020) 46#define COH901318_BE_INT_STATUS2 (0x0024) 47/* BE_INT_CLEAR - Bus Error Interrupt Clear Registers 32bit (-/W) */ 48#define COH901318_BE_INT_CLEAR1 (0x0028) 49#define COH901318_BE_INT_CLEAR2 (0x002C) 50/* RAW_BE_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */ 51#define COH901318_RAW_BE_INT_STATUS1 (0x0030) 52#define COH901318_RAW_BE_INT_STATUS2 (0x0034) 53 54/* 55 * CX_CFG - Channel Configuration Registers 32bit (R/W) 56 */ 57#define COH901318_CX_CFG (0x0100) 58#define COH901318_CX_CFG_SPACING (0x04) 59/* Channel enable activates tha dma job */ 60#define COH901318_CX_CFG_CH_ENABLE (0x00000001) 61#define COH901318_CX_CFG_CH_DISABLE (0x00000000) 62/* Request Mode */ 63#define COH901318_CX_CFG_RM_MASK (0x00000006) 64#define COH901318_CX_CFG_RM_MEMORY_TO_MEMORY (0x0 << 1) 65#define COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY (0x1 << 1) 66#define COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY (0x1 << 1) 67#define COH901318_CX_CFG_RM_PRIMARY_TO_SECONDARY (0x3 << 1) 68#define COH901318_CX_CFG_RM_SECONDARY_TO_PRIMARY (0x3 << 1) 69/* Linked channel request field. RM must == 11 */ 70#define COH901318_CX_CFG_LCRF_SHIFT 3 71#define COH901318_CX_CFG_LCRF_MASK (0x000001F8) 72#define COH901318_CX_CFG_LCR_DISABLE (0x00000000) 73/* Terminal Counter Interrupt Request Mask */ 74#define COH901318_CX_CFG_TC_IRQ_ENABLE (0x00000200) 75#define COH901318_CX_CFG_TC_IRQ_DISABLE (0x00000000) 76/* Bus Error interrupt Mask */ 77#define COH901318_CX_CFG_BE_IRQ_ENABLE (0x00000400) 78#define COH901318_CX_CFG_BE_IRQ_DISABLE (0x00000000) 79 80/* 81 * CX_STAT - Channel Status Registers 32bit (R/-) 82 */ 83#define COH901318_CX_STAT (0x0200) 84#define COH901318_CX_STAT_SPACING (0x04) 85#define COH901318_CX_STAT_RBE_IRQ_IND (0x00000008) 86#define COH901318_CX_STAT_RTC_IRQ_IND (0x00000004) 87#define COH901318_CX_STAT_ACTIVE (0x00000002) 88#define COH901318_CX_STAT_ENABLED (0x00000001) 89 90/* 91 * CX_CTRL - Channel Control Registers 32bit (R/W) 92 */ 93#define COH901318_CX_CTRL (0x0400) 94#define COH901318_CX_CTRL_SPACING (0x10) 95/* Transfer Count Enable */ 96#define COH901318_CX_CTRL_TC_ENABLE (0x00001000) 97#define COH901318_CX_CTRL_TC_DISABLE (0x00000000) 98/* Transfer Count Value 0 - 4095 */ 99#define COH901318_CX_CTRL_TC_VALUE_MASK (0x00000FFF) 100/* Burst count */ 101#define COH901318_CX_CTRL_BURST_COUNT_MASK (0x0000E000) 102#define COH901318_CX_CTRL_BURST_COUNT_64_BYTES (0x7 << 13) 103#define COH901318_CX_CTRL_BURST_COUNT_48_BYTES (0x6 << 13) 104#define COH901318_CX_CTRL_BURST_COUNT_32_BYTES (0x5 << 13) 105#define COH901318_CX_CTRL_BURST_COUNT_16_BYTES (0x4 << 13) 106#define COH901318_CX_CTRL_BURST_COUNT_8_BYTES (0x3 << 13) 107#define COH901318_CX_CTRL_BURST_COUNT_4_BYTES (0x2 << 13) 108#define COH901318_CX_CTRL_BURST_COUNT_2_BYTES (0x1 << 13) 109#define COH901318_CX_CTRL_BURST_COUNT_1_BYTE (0x0 << 13) 110/* Source bus size */ 111#define COH901318_CX_CTRL_SRC_BUS_SIZE_MASK (0x00030000) 112#define COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS (0x2 << 16) 113#define COH901318_CX_CTRL_SRC_BUS_SIZE_16_BITS (0x1 << 16) 114#define COH901318_CX_CTRL_SRC_BUS_SIZE_8_BITS (0x0 << 16) 115/* Source address increment */ 116#define COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE (0x00040000) 117#define COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE (0x00000000) 118/* Destination Bus Size */ 119#define COH901318_CX_CTRL_DST_BUS_SIZE_MASK (0x00180000) 120#define COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS (0x2 << 19) 121#define COH901318_CX_CTRL_DST_BUS_SIZE_16_BITS (0x1 << 19) 122#define COH901318_CX_CTRL_DST_BUS_SIZE_8_BITS (0x0 << 19) 123/* Destination address increment */ 124#define COH901318_CX_CTRL_DST_ADDR_INC_ENABLE (0x00200000) 125#define COH901318_CX_CTRL_DST_ADDR_INC_DISABLE (0x00000000) 126/* Master Mode (Master2 is only connected to MSL) */ 127#define COH901318_CX_CTRL_MASTER_MODE_MASK (0x00C00000) 128#define COH901318_CX_CTRL_MASTER_MODE_M2R_M1W (0x3 << 22) 129#define COH901318_CX_CTRL_MASTER_MODE_M1R_M2W (0x2 << 22) 130#define COH901318_CX_CTRL_MASTER_MODE_M2RW (0x1 << 22) 131#define COH901318_CX_CTRL_MASTER_MODE_M1RW (0x0 << 22) 132/* Terminal Count flag to PER enable */ 133#define COH901318_CX_CTRL_TCP_ENABLE (0x01000000) 134#define COH901318_CX_CTRL_TCP_DISABLE (0x00000000) 135/* Terminal Count flags to CPU enable */ 136#define COH901318_CX_CTRL_TC_IRQ_ENABLE (0x02000000) 137#define COH901318_CX_CTRL_TC_IRQ_DISABLE (0x00000000) 138/* Hand shake to peripheral */ 139#define COH901318_CX_CTRL_HSP_ENABLE (0x04000000) 140#define COH901318_CX_CTRL_HSP_DISABLE (0x00000000) 141#define COH901318_CX_CTRL_HSS_ENABLE (0x08000000) 142#define COH901318_CX_CTRL_HSS_DISABLE (0x00000000) 143/* DMA mode */ 144#define COH901318_CX_CTRL_DDMA_MASK (0x30000000) 145#define COH901318_CX_CTRL_DDMA_LEGACY (0x0 << 28) 146#define COH901318_CX_CTRL_DDMA_DEMAND_DMA1 (0x1 << 28) 147#define COH901318_CX_CTRL_DDMA_DEMAND_DMA2 (0x2 << 28) 148/* Primary Request Data Destination */ 149#define COH901318_CX_CTRL_PRDD_MASK (0x40000000) 150#define COH901318_CX_CTRL_PRDD_DEST (0x1 << 30) 151#define COH901318_CX_CTRL_PRDD_SOURCE (0x0 << 30) 152 153/* 154 * CX_SRC_ADDR - Channel Source Address Registers 32bit (R/W) 155 */ 156#define COH901318_CX_SRC_ADDR (0x0404) 157#define COH901318_CX_SRC_ADDR_SPACING (0x10) 158 159/* 160 * CX_DST_ADDR - Channel Destination Address Registers 32bit R/W 161 */ 162#define COH901318_CX_DST_ADDR (0x0408) 163#define COH901318_CX_DST_ADDR_SPACING (0x10) 164 165/* 166 * CX_LNK_ADDR - Channel Link Address Registers 32bit (R/W) 167 */ 168#define COH901318_CX_LNK_ADDR (0x040C) 169#define COH901318_CX_LNK_ADDR_SPACING (0x10) 170#define COH901318_CX_LNK_LINK_IMMEDIATE (0x00000001) 171 172/** 173 * struct coh901318_params - parameters for DMAC configuration 174 * @config: DMA config register 175 * @ctrl_lli_last: DMA control register for the last lli in the list 176 * @ctrl_lli: DMA control register for an lli 177 * @ctrl_lli_chained: DMA control register for a chained lli 178 */ 179struct coh901318_params { 180 u32 config; 181 u32 ctrl_lli_last; 182 u32 ctrl_lli; 183 u32 ctrl_lli_chained; 184}; 185 186/** 187 * struct coh_dma_channel - dma channel base 188 * @name: ascii name of dma channel 189 * @number: channel id number 190 * @desc_nbr_max: number of preallocated descriptors 191 * @priority_high: prio of channel, 0 low otherwise high. 192 * @param: configuration parameters 193 */ 194struct coh_dma_channel { 195 const char name[32]; 196 const int number; 197 const int desc_nbr_max; 198 const int priority_high; 199 const struct coh901318_params param; 200}; 201 202/** 203 * struct powersave - DMA power save structure 204 * @lock: lock protecting data in this struct 205 * @started_channels: bit mask indicating active dma channels 206 */ 207struct powersave { 208 spinlock_t lock; 209 u64 started_channels; 210}; 211 212/* points out all dma slave channels. 213 * Syntax is [A1, B1, A2, B2, .... ,-1,-1] 214 * Select all channels from A to B, end of list is marked with -1,-1 215 */ 216static int dma_slave_channels[] = { 217 U300_DMA_MSL_TX_0, U300_DMA_SPI_RX, 218 U300_DMA_UART1_TX, U300_DMA_UART1_RX, -1, -1}; 219 220/* points out all dma memcpy channels. */ 221static int dma_memcpy_channels[] = { 222 U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_8, -1, -1}; 223 224#define flags_memcpy_config (COH901318_CX_CFG_CH_DISABLE | \ 225 COH901318_CX_CFG_RM_MEMORY_TO_MEMORY | \ 226 COH901318_CX_CFG_LCR_DISABLE | \ 227 COH901318_CX_CFG_TC_IRQ_ENABLE | \ 228 COH901318_CX_CFG_BE_IRQ_ENABLE) 229#define flags_memcpy_lli_chained (COH901318_CX_CTRL_TC_ENABLE | \ 230 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \ 231 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \ 232 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \ 233 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \ 234 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \ 235 COH901318_CX_CTRL_MASTER_MODE_M1RW | \ 236 COH901318_CX_CTRL_TCP_DISABLE | \ 237 COH901318_CX_CTRL_TC_IRQ_DISABLE | \ 238 COH901318_CX_CTRL_HSP_DISABLE | \ 239 COH901318_CX_CTRL_HSS_DISABLE | \ 240 COH901318_CX_CTRL_DDMA_LEGACY | \ 241 COH901318_CX_CTRL_PRDD_SOURCE) 242#define flags_memcpy_lli (COH901318_CX_CTRL_TC_ENABLE | \ 243 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \ 244 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \ 245 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \ 246 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \ 247 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \ 248 COH901318_CX_CTRL_MASTER_MODE_M1RW | \ 249 COH901318_CX_CTRL_TCP_DISABLE | \ 250 COH901318_CX_CTRL_TC_IRQ_DISABLE | \ 251 COH901318_CX_CTRL_HSP_DISABLE | \ 252 COH901318_CX_CTRL_HSS_DISABLE | \ 253 COH901318_CX_CTRL_DDMA_LEGACY | \ 254 COH901318_CX_CTRL_PRDD_SOURCE) 255#define flags_memcpy_lli_last (COH901318_CX_CTRL_TC_ENABLE | \ 256 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \ 257 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \ 258 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \ 259 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \ 260 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \ 261 COH901318_CX_CTRL_MASTER_MODE_M1RW | \ 262 COH901318_CX_CTRL_TCP_DISABLE | \ 263 COH901318_CX_CTRL_TC_IRQ_ENABLE | \ 264 COH901318_CX_CTRL_HSP_DISABLE | \ 265 COH901318_CX_CTRL_HSS_DISABLE | \ 266 COH901318_CX_CTRL_DDMA_LEGACY | \ 267 COH901318_CX_CTRL_PRDD_SOURCE) 268 269static const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = { 270 { 271 .number = U300_DMA_MSL_TX_0, 272 .name = "MSL TX 0", 273 .priority_high = 0, 274 }, 275 { 276 .number = U300_DMA_MSL_TX_1, 277 .name = "MSL TX 1", 278 .priority_high = 0, 279 .param.config = COH901318_CX_CFG_CH_DISABLE | 280 COH901318_CX_CFG_LCR_DISABLE | 281 COH901318_CX_CFG_TC_IRQ_ENABLE | 282 COH901318_CX_CFG_BE_IRQ_ENABLE, 283 .param.ctrl_lli_chained = 0 | 284 COH901318_CX_CTRL_TC_ENABLE | 285 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | 286 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | 287 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | 288 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | 289 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | 290 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W | 291 COH901318_CX_CTRL_TCP_DISABLE | 292 COH901318_CX_CTRL_TC_IRQ_DISABLE | 293 COH901318_CX_CTRL_HSP_ENABLE | 294 COH901318_CX_CTRL_HSS_DISABLE | 295 COH901318_CX_CTRL_DDMA_LEGACY | 296 COH901318_CX_CTRL_PRDD_SOURCE, 297 .param.ctrl_lli = 0 | 298 COH901318_CX_CTRL_TC_ENABLE | 299 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | 300 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | 301 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | 302 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | 303 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | 304 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W | 305 COH901318_CX_CTRL_TCP_ENABLE | 306 COH901318_CX_CTRL_TC_IRQ_DISABLE | 307 COH901318_CX_CTRL_HSP_ENABLE | 308 COH901318_CX_CTRL_HSS_DISABLE | 309 COH901318_CX_CTRL_DDMA_LEGACY | 310 COH901318_CX_CTRL_PRDD_SOURCE, 311 .param.ctrl_lli_last = 0 | 312 COH901318_CX_CTRL_TC_ENABLE | 313 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | 314 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | 315 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | 316 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | 317 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | 318 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W | 319 COH901318_CX_CTRL_TCP_ENABLE | 320 COH901318_CX_CTRL_TC_IRQ_ENABLE | 321 COH901318_CX_CTRL_HSP_ENABLE | 322 COH901318_CX_CTRL_HSS_DISABLE | 323 COH901318_CX_CTRL_DDMA_LEGACY | 324 COH901318_CX_CTRL_PRDD_SOURCE, 325 }, 326 { 327 .number = U300_DMA_MSL_TX_2, 328 .name = "MSL TX 2", 329 .priority_high = 0, 330 .param.config = COH901318_CX_CFG_CH_DISABLE | 331 COH901318_CX_CFG_LCR_DISABLE | 332 COH901318_CX_CFG_TC_IRQ_ENABLE | 333 COH901318_CX_CFG_BE_IRQ_ENABLE, 334 .param.ctrl_lli_chained = 0 | 335 COH901318_CX_CTRL_TC_ENABLE | 336 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | 337 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | 338 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | 339 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | 340 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | 341 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W | 342 COH901318_CX_CTRL_TCP_DISABLE | 343 COH901318_CX_CTRL_TC_IRQ_DISABLE | 344 COH901318_CX_CTRL_HSP_ENABLE | 345 COH901318_CX_CTRL_HSS_DISABLE | 346 COH901318_CX_CTRL_DDMA_LEGACY | 347 COH901318_CX_CTRL_PRDD_SOURCE, 348 .param.ctrl_lli = 0 | 349 COH901318_CX_CTRL_TC_ENABLE | 350 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | 351 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | 352 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | 353 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | 354 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | 355 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W | 356 COH901318_CX_CTRL_TCP_ENABLE | 357 COH901318_CX_CTRL_TC_IRQ_DISABLE | 358 COH901318_CX_CTRL_HSP_ENABLE | 359 COH901318_CX_CTRL_HSS_DISABLE | 360 COH901318_CX_CTRL_DDMA_LEGACY | 361 COH901318_CX_CTRL_PRDD_SOURCE, 362 .param.ctrl_lli_last = 0 | 363 COH901318_CX_CTRL_TC_ENABLE | 364 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | 365 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | 366 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | 367 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | 368 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | 369 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W | 370 COH901318_CX_CTRL_TCP_ENABLE | 371 COH901318_CX_CTRL_TC_IRQ_ENABLE | 372 COH901318_CX_CTRL_HSP_ENABLE | 373 COH901318_CX_CTRL_HSS_DISABLE | 374 COH901318_CX_CTRL_DDMA_LEGACY | 375 COH901318_CX_CTRL_PRDD_SOURCE, 376 .desc_nbr_max = 10, 377 }, 378 { 379 .number = U300_DMA_MSL_TX_3, 380 .name = "MSL TX 3", 381 .priority_high = 0, 382 .param.config = COH901318_CX_CFG_CH_DISABLE | 383 COH901318_CX_CFG_LCR_DISABLE | 384 COH901318_CX_CFG_TC_IRQ_ENABLE | 385 COH901318_CX_CFG_BE_IRQ_ENABLE, 386 .param.ctrl_lli_chained = 0 | 387 COH901318_CX_CTRL_TC_ENABLE | 388 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | 389 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | 390 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | 391 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | 392 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | 393 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W | 394 COH901318_CX_CTRL_TCP_DISABLE | 395 COH901318_CX_CTRL_TC_IRQ_DISABLE | 396 COH901318_CX_CTRL_HSP_ENABLE | 397 COH901318_CX_CTRL_HSS_DISABLE | 398 COH901318_CX_CTRL_DDMA_LEGACY | 399 COH901318_CX_CTRL_PRDD_SOURCE, 400 .param.ctrl_lli = 0 | 401 COH901318_CX_CTRL_TC_ENABLE | 402 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | 403 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | 404 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | 405 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | 406 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | 407 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W | 408 COH901318_CX_CTRL_TCP_ENABLE | 409 COH901318_CX_CTRL_TC_IRQ_DISABLE | 410 COH901318_CX_CTRL_HSP_ENABLE | 411 COH901318_CX_CTRL_HSS_DISABLE | 412 COH901318_CX_CTRL_DDMA_LEGACY | 413 COH901318_CX_CTRL_PRDD_SOURCE, 414 .param.ctrl_lli_last = 0 | 415 COH901318_CX_CTRL_TC_ENABLE | 416 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | 417 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | 418 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | 419 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | 420 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | 421 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W | 422 COH901318_CX_CTRL_TCP_ENABLE | 423 COH901318_CX_CTRL_TC_IRQ_ENABLE | 424 COH901318_CX_CTRL_HSP_ENABLE | 425 COH901318_CX_CTRL_HSS_DISABLE | 426 COH901318_CX_CTRL_DDMA_LEGACY | 427 COH901318_CX_CTRL_PRDD_SOURCE, 428 }, 429 { 430 .number = U300_DMA_MSL_TX_4, 431 .name = "MSL TX 4", 432 .priority_high = 0, 433 .param.config = COH901318_CX_CFG_CH_DISABLE | 434 COH901318_CX_CFG_LCR_DISABLE | 435 COH901318_CX_CFG_TC_IRQ_ENABLE | 436 COH901318_CX_CFG_BE_IRQ_ENABLE, 437 .param.ctrl_lli_chained = 0 | 438 COH901318_CX_CTRL_TC_ENABLE | 439 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | 440 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | 441 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | 442 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | 443 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | 444 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W | 445 COH901318_CX_CTRL_TCP_DISABLE | 446 COH901318_CX_CTRL_TC_IRQ_DISABLE | 447 COH901318_CX_CTRL_HSP_ENABLE | 448 COH901318_CX_CTRL_HSS_DISABLE | 449 COH901318_CX_CTRL_DDMA_LEGACY | 450 COH901318_CX_CTRL_PRDD_SOURCE, 451 .param.ctrl_lli = 0 | 452 COH901318_CX_CTRL_TC_ENABLE | 453 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | 454 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | 455 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | 456 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | 457 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | 458 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W | 459 COH901318_CX_CTRL_TCP_ENABLE | 460 COH901318_CX_CTRL_TC_IRQ_DISABLE | 461 COH901318_CX_CTRL_HSP_ENABLE | 462 COH901318_CX_CTRL_HSS_DISABLE | 463 COH901318_CX_CTRL_DDMA_LEGACY | 464 COH901318_CX_CTRL_PRDD_SOURCE, 465 .param.ctrl_lli_last = 0 | 466 COH901318_CX_CTRL_TC_ENABLE | 467 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | 468 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | 469 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | 470 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | 471 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | 472 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W | 473 COH901318_CX_CTRL_TCP_ENABLE | 474 COH901318_CX_CTRL_TC_IRQ_ENABLE | 475 COH901318_CX_CTRL_HSP_ENABLE | 476 COH901318_CX_CTRL_HSS_DISABLE | 477 COH901318_CX_CTRL_DDMA_LEGACY | 478 COH901318_CX_CTRL_PRDD_SOURCE, 479 }, 480 { 481 .number = U300_DMA_MSL_TX_5, 482 .name = "MSL TX 5", 483 .priority_high = 0, 484 }, 485 { 486 .number = U300_DMA_MSL_TX_6, 487 .name = "MSL TX 6", 488 .priority_high = 0, 489 }, 490 { 491 .number = U300_DMA_MSL_RX_0, 492 .name = "MSL RX 0", 493 .priority_high = 0, 494 }, 495 { 496 .number = U300_DMA_MSL_RX_1, 497 .name = "MSL RX 1", 498 .priority_high = 0, 499 .param.config = COH901318_CX_CFG_CH_DISABLE | 500 COH901318_CX_CFG_LCR_DISABLE | 501 COH901318_CX_CFG_TC_IRQ_ENABLE | 502 COH901318_CX_CFG_BE_IRQ_ENABLE, 503 .param.ctrl_lli_chained = 0 | 504 COH901318_CX_CTRL_TC_ENABLE | 505 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | 506 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | 507 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | 508 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | 509 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | 510 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | 511 COH901318_CX_CTRL_TCP_DISABLE | 512 COH901318_CX_CTRL_TC_IRQ_DISABLE | 513 COH901318_CX_CTRL_HSP_ENABLE | 514 COH901318_CX_CTRL_HSS_DISABLE | 515 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | 516 COH901318_CX_CTRL_PRDD_DEST, 517 .param.ctrl_lli = 0, 518 .param.ctrl_lli_last = 0 | 519 COH901318_CX_CTRL_TC_ENABLE | 520 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | 521 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | 522 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | 523 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | 524 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | 525 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | 526 COH901318_CX_CTRL_TCP_DISABLE | 527 COH901318_CX_CTRL_TC_IRQ_ENABLE | 528 COH901318_CX_CTRL_HSP_ENABLE | 529 COH901318_CX_CTRL_HSS_DISABLE | 530 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | 531 COH901318_CX_CTRL_PRDD_DEST, 532 }, 533 { 534 .number = U300_DMA_MSL_RX_2, 535 .name = "MSL RX 2", 536 .priority_high = 0, 537 .param.config = COH901318_CX_CFG_CH_DISABLE | 538 COH901318_CX_CFG_LCR_DISABLE | 539 COH901318_CX_CFG_TC_IRQ_ENABLE | 540 COH901318_CX_CFG_BE_IRQ_ENABLE, 541 .param.ctrl_lli_chained = 0 | 542 COH901318_CX_CTRL_TC_ENABLE | 543 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | 544 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | 545 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | 546 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | 547 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | 548 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | 549 COH901318_CX_CTRL_TCP_DISABLE | 550 COH901318_CX_CTRL_TC_IRQ_DISABLE | 551 COH901318_CX_CTRL_HSP_ENABLE | 552 COH901318_CX_CTRL_HSS_DISABLE | 553 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | 554 COH901318_CX_CTRL_PRDD_DEST, 555 .param.ctrl_lli = 0 | 556 COH901318_CX_CTRL_TC_ENABLE | 557 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | 558 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | 559 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | 560 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | 561 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | 562 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | 563 COH901318_CX_CTRL_TCP_DISABLE | 564 COH901318_CX_CTRL_TC_IRQ_ENABLE | 565 COH901318_CX_CTRL_HSP_ENABLE | 566 COH901318_CX_CTRL_HSS_DISABLE | 567 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | 568 COH901318_CX_CTRL_PRDD_DEST, 569 .param.ctrl_lli_last = 0 | 570 COH901318_CX_CTRL_TC_ENABLE | 571 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | 572 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | 573 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | 574 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | 575 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | 576 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | 577 COH901318_CX_CTRL_TCP_DISABLE | 578 COH901318_CX_CTRL_TC_IRQ_ENABLE | 579 COH901318_CX_CTRL_HSP_ENABLE | 580 COH901318_CX_CTRL_HSS_DISABLE | 581 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | 582 COH901318_CX_CTRL_PRDD_DEST, 583 }, 584 { 585 .number = U300_DMA_MSL_RX_3, 586 .name = "MSL RX 3", 587 .priority_high = 0, 588 .param.config = COH901318_CX_CFG_CH_DISABLE | 589 COH901318_CX_CFG_LCR_DISABLE | 590 COH901318_CX_CFG_TC_IRQ_ENABLE | 591 COH901318_CX_CFG_BE_IRQ_ENABLE, 592 .param.ctrl_lli_chained = 0 | 593 COH901318_CX_CTRL_TC_ENABLE | 594 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | 595 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | 596 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | 597 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | 598 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | 599 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | 600 COH901318_CX_CTRL_TCP_DISABLE | 601 COH901318_CX_CTRL_TC_IRQ_DISABLE | 602 COH901318_CX_CTRL_HSP_ENABLE | 603 COH901318_CX_CTRL_HSS_DISABLE | 604 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | 605 COH901318_CX_CTRL_PRDD_DEST, 606 .param.ctrl_lli = 0 | 607 COH901318_CX_CTRL_TC_ENABLE | 608 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | 609 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | 610 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | 611 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | 612 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | 613 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | 614 COH901318_CX_CTRL_TCP_DISABLE | 615 COH901318_CX_CTRL_TC_IRQ_ENABLE | 616 COH901318_CX_CTRL_HSP_ENABLE | 617 COH901318_CX_CTRL_HSS_DISABLE | 618 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | 619 COH901318_CX_CTRL_PRDD_DEST, 620 .param.ctrl_lli_last = 0 | 621 COH901318_CX_CTRL_TC_ENABLE | 622 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | 623 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | 624 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | 625 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | 626 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | 627 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | 628 COH901318_CX_CTRL_TCP_DISABLE | 629 COH901318_CX_CTRL_TC_IRQ_ENABLE | 630 COH901318_CX_CTRL_HSP_ENABLE | 631 COH901318_CX_CTRL_HSS_DISABLE | 632 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | 633 COH901318_CX_CTRL_PRDD_DEST, 634 }, 635 { 636 .number = U300_DMA_MSL_RX_4, 637 .name = "MSL RX 4", 638 .priority_high = 0, 639 .param.config = COH901318_CX_CFG_CH_DISABLE | 640 COH901318_CX_CFG_LCR_DISABLE | 641 COH901318_CX_CFG_TC_IRQ_ENABLE | 642 COH901318_CX_CFG_BE_IRQ_ENABLE, 643 .param.ctrl_lli_chained = 0 | 644 COH901318_CX_CTRL_TC_ENABLE | 645 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | 646 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | 647 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | 648 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | 649 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | 650 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | 651 COH901318_CX_CTRL_TCP_DISABLE | 652 COH901318_CX_CTRL_TC_IRQ_DISABLE | 653 COH901318_CX_CTRL_HSP_ENABLE | 654 COH901318_CX_CTRL_HSS_DISABLE | 655 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | 656 COH901318_CX_CTRL_PRDD_DEST, 657 .param.ctrl_lli = 0 | 658 COH901318_CX_CTRL_TC_ENABLE | 659 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | 660 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | 661 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | 662 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | 663 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | 664 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | 665 COH901318_CX_CTRL_TCP_DISABLE | 666 COH901318_CX_CTRL_TC_IRQ_ENABLE | 667 COH901318_CX_CTRL_HSP_ENABLE | 668 COH901318_CX_CTRL_HSS_DISABLE | 669 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | 670 COH901318_CX_CTRL_PRDD_DEST, 671 .param.ctrl_lli_last = 0 | 672 COH901318_CX_CTRL_TC_ENABLE | 673 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | 674 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | 675 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | 676 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | 677 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | 678 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | 679 COH901318_CX_CTRL_TCP_DISABLE | 680 COH901318_CX_CTRL_TC_IRQ_ENABLE | 681 COH901318_CX_CTRL_HSP_ENABLE | 682 COH901318_CX_CTRL_HSS_DISABLE | 683 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | 684 COH901318_CX_CTRL_PRDD_DEST, 685 }, 686 { 687 .number = U300_DMA_MSL_RX_5, 688 .name = "MSL RX 5", 689 .priority_high = 0, 690 .param.config = COH901318_CX_CFG_CH_DISABLE | 691 COH901318_CX_CFG_LCR_DISABLE | 692 COH901318_CX_CFG_TC_IRQ_ENABLE | 693 COH901318_CX_CFG_BE_IRQ_ENABLE, 694 .param.ctrl_lli_chained = 0 | 695 COH901318_CX_CTRL_TC_ENABLE | 696 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | 697 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | 698 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | 699 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | 700 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | 701 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | 702 COH901318_CX_CTRL_TCP_DISABLE | 703 COH901318_CX_CTRL_TC_IRQ_DISABLE | 704 COH901318_CX_CTRL_HSP_ENABLE | 705 COH901318_CX_CTRL_HSS_DISABLE | 706 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | 707 COH901318_CX_CTRL_PRDD_DEST, 708 .param.ctrl_lli = 0 | 709 COH901318_CX_CTRL_TC_ENABLE | 710 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | 711 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | 712 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | 713 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | 714 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | 715 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | 716 COH901318_CX_CTRL_TCP_DISABLE | 717 COH901318_CX_CTRL_TC_IRQ_ENABLE | 718 COH901318_CX_CTRL_HSP_ENABLE | 719 COH901318_CX_CTRL_HSS_DISABLE | 720 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | 721 COH901318_CX_CTRL_PRDD_DEST, 722 .param.ctrl_lli_last = 0 | 723 COH901318_CX_CTRL_TC_ENABLE | 724 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | 725 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | 726 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | 727 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | 728 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | 729 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | 730 COH901318_CX_CTRL_TCP_DISABLE | 731 COH901318_CX_CTRL_TC_IRQ_ENABLE | 732 COH901318_CX_CTRL_HSP_ENABLE | 733 COH901318_CX_CTRL_HSS_DISABLE | 734 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | 735 COH901318_CX_CTRL_PRDD_DEST, 736 }, 737 { 738 .number = U300_DMA_MSL_RX_6, 739 .name = "MSL RX 6", 740 .priority_high = 0, 741 }, 742 /* 743 * Don't set up device address, burst count or size of src 744 * or dst bus for this peripheral - handled by PrimeCell 745 * DMA extension. 746 */ 747 { 748 .number = U300_DMA_MMCSD_RX_TX, 749 .name = "MMCSD RX TX", 750 .priority_high = 0, 751 .param.config = COH901318_CX_CFG_CH_DISABLE | 752 COH901318_CX_CFG_LCR_DISABLE | 753 COH901318_CX_CFG_TC_IRQ_ENABLE | 754 COH901318_CX_CFG_BE_IRQ_ENABLE, 755 .param.ctrl_lli_chained = 0 | 756 COH901318_CX_CTRL_TC_ENABLE | 757 COH901318_CX_CTRL_MASTER_MODE_M1RW | 758 COH901318_CX_CTRL_TCP_ENABLE | 759 COH901318_CX_CTRL_TC_IRQ_DISABLE | 760 COH901318_CX_CTRL_HSP_ENABLE | 761 COH901318_CX_CTRL_HSS_DISABLE | 762 COH901318_CX_CTRL_DDMA_LEGACY, 763 .param.ctrl_lli = 0 | 764 COH901318_CX_CTRL_TC_ENABLE | 765 COH901318_CX_CTRL_MASTER_MODE_M1RW | 766 COH901318_CX_CTRL_TCP_ENABLE | 767 COH901318_CX_CTRL_TC_IRQ_DISABLE | 768 COH901318_CX_CTRL_HSP_ENABLE | 769 COH901318_CX_CTRL_HSS_DISABLE | 770 COH901318_CX_CTRL_DDMA_LEGACY, 771 .param.ctrl_lli_last = 0 | 772 COH901318_CX_CTRL_TC_ENABLE | 773 COH901318_CX_CTRL_MASTER_MODE_M1RW | 774 COH901318_CX_CTRL_TCP_DISABLE | 775 COH901318_CX_CTRL_TC_IRQ_ENABLE | 776 COH901318_CX_CTRL_HSP_ENABLE | 777 COH901318_CX_CTRL_HSS_DISABLE | 778 COH901318_CX_CTRL_DDMA_LEGACY, 779 780 }, 781 { 782 .number = U300_DMA_MSPRO_TX, 783 .name = "MSPRO TX", 784 .priority_high = 0, 785 }, 786 { 787 .number = U300_DMA_MSPRO_RX, 788 .name = "MSPRO RX", 789 .priority_high = 0, 790 }, 791 /* 792 * Don't set up device address, burst count or size of src 793 * or dst bus for this peripheral - handled by PrimeCell 794 * DMA extension. 795 */ 796 { 797 .number = U300_DMA_UART0_TX, 798 .name = "UART0 TX", 799 .priority_high = 0, 800 .param.config = COH901318_CX_CFG_CH_DISABLE | 801 COH901318_CX_CFG_LCR_DISABLE | 802 COH901318_CX_CFG_TC_IRQ_ENABLE | 803 COH901318_CX_CFG_BE_IRQ_ENABLE, 804 .param.ctrl_lli_chained = 0 | 805 COH901318_CX_CTRL_TC_ENABLE | 806 COH901318_CX_CTRL_MASTER_MODE_M1RW | 807 COH901318_CX_CTRL_TCP_ENABLE | 808 COH901318_CX_CTRL_TC_IRQ_DISABLE | 809 COH901318_CX_CTRL_HSP_ENABLE | 810 COH901318_CX_CTRL_HSS_DISABLE | 811 COH901318_CX_CTRL_DDMA_LEGACY, 812 .param.ctrl_lli = 0 | 813 COH901318_CX_CTRL_TC_ENABLE | 814 COH901318_CX_CTRL_MASTER_MODE_M1RW | 815 COH901318_CX_CTRL_TCP_ENABLE | 816 COH901318_CX_CTRL_TC_IRQ_ENABLE | 817 COH901318_CX_CTRL_HSP_ENABLE | 818 COH901318_CX_CTRL_HSS_DISABLE | 819 COH901318_CX_CTRL_DDMA_LEGACY, 820 .param.ctrl_lli_last = 0 | 821 COH901318_CX_CTRL_TC_ENABLE | 822 COH901318_CX_CTRL_MASTER_MODE_M1RW | 823 COH901318_CX_CTRL_TCP_ENABLE | 824 COH901318_CX_CTRL_TC_IRQ_ENABLE | 825 COH901318_CX_CTRL_HSP_ENABLE | 826 COH901318_CX_CTRL_HSS_DISABLE | 827 COH901318_CX_CTRL_DDMA_LEGACY, 828 }, 829 { 830 .number = U300_DMA_UART0_RX, 831 .name = "UART0 RX", 832 .priority_high = 0, 833 .param.config = COH901318_CX_CFG_CH_DISABLE | 834 COH901318_CX_CFG_LCR_DISABLE | 835 COH901318_CX_CFG_TC_IRQ_ENABLE | 836 COH901318_CX_CFG_BE_IRQ_ENABLE, 837 .param.ctrl_lli_chained = 0 | 838 COH901318_CX_CTRL_TC_ENABLE | 839 COH901318_CX_CTRL_MASTER_MODE_M1RW | 840 COH901318_CX_CTRL_TCP_ENABLE | 841 COH901318_CX_CTRL_TC_IRQ_DISABLE | 842 COH901318_CX_CTRL_HSP_ENABLE | 843 COH901318_CX_CTRL_HSS_DISABLE | 844 COH901318_CX_CTRL_DDMA_LEGACY, 845 .param.ctrl_lli = 0 | 846 COH901318_CX_CTRL_TC_ENABLE | 847 COH901318_CX_CTRL_MASTER_MODE_M1RW | 848 COH901318_CX_CTRL_TCP_ENABLE | 849 COH901318_CX_CTRL_TC_IRQ_ENABLE | 850 COH901318_CX_CTRL_HSP_ENABLE | 851 COH901318_CX_CTRL_HSS_DISABLE | 852 COH901318_CX_CTRL_DDMA_LEGACY, 853 .param.ctrl_lli_last = 0 | 854 COH901318_CX_CTRL_TC_ENABLE | 855 COH901318_CX_CTRL_MASTER_MODE_M1RW | 856 COH901318_CX_CTRL_TCP_ENABLE | 857 COH901318_CX_CTRL_TC_IRQ_ENABLE | 858 COH901318_CX_CTRL_HSP_ENABLE | 859 COH901318_CX_CTRL_HSS_DISABLE | 860 COH901318_CX_CTRL_DDMA_LEGACY, 861 }, 862 { 863 .number = U300_DMA_APEX_TX, 864 .name = "APEX TX", 865 .priority_high = 0, 866 }, 867 { 868 .number = U300_DMA_APEX_RX, 869 .name = "APEX RX", 870 .priority_high = 0, 871 }, 872 { 873 .number = U300_DMA_PCM_I2S0_TX, 874 .name = "PCM I2S0 TX", 875 .priority_high = 1, 876 .param.config = COH901318_CX_CFG_CH_DISABLE | 877 COH901318_CX_CFG_LCR_DISABLE | 878 COH901318_CX_CFG_TC_IRQ_ENABLE | 879 COH901318_CX_CFG_BE_IRQ_ENABLE, 880 .param.ctrl_lli_chained = 0 | 881 COH901318_CX_CTRL_TC_ENABLE | 882 COH901318_CX_CTRL_BURST_COUNT_16_BYTES | 883 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | 884 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | 885 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | 886 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | 887 COH901318_CX_CTRL_MASTER_MODE_M1RW | 888 COH901318_CX_CTRL_TCP_DISABLE | 889 COH901318_CX_CTRL_TC_IRQ_DISABLE | 890 COH901318_CX_CTRL_HSP_ENABLE | 891 COH901318_CX_CTRL_HSS_DISABLE | 892 COH901318_CX_CTRL_DDMA_LEGACY | 893 COH901318_CX_CTRL_PRDD_SOURCE, 894 .param.ctrl_lli = 0 | 895 COH901318_CX_CTRL_TC_ENABLE | 896 COH901318_CX_CTRL_BURST_COUNT_16_BYTES | 897 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | 898 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | 899 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | 900 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | 901 COH901318_CX_CTRL_MASTER_MODE_M1RW | 902 COH901318_CX_CTRL_TCP_ENABLE | 903 COH901318_CX_CTRL_TC_IRQ_DISABLE | 904 COH901318_CX_CTRL_HSP_ENABLE | 905 COH901318_CX_CTRL_HSS_DISABLE | 906 COH901318_CX_CTRL_DDMA_LEGACY | 907 COH901318_CX_CTRL_PRDD_SOURCE, 908 .param.ctrl_lli_last = 0 | 909 COH901318_CX_CTRL_TC_ENABLE | 910 COH901318_CX_CTRL_BURST_COUNT_16_BYTES | 911 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | 912 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | 913 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | 914 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | 915 COH901318_CX_CTRL_MASTER_MODE_M1RW | 916 COH901318_CX_CTRL_TCP_ENABLE | 917 COH901318_CX_CTRL_TC_IRQ_DISABLE | 918 COH901318_CX_CTRL_HSP_ENABLE | 919 COH901318_CX_CTRL_HSS_DISABLE | 920 COH901318_CX_CTRL_DDMA_LEGACY | 921 COH901318_CX_CTRL_PRDD_SOURCE, 922 }, 923 { 924 .number = U300_DMA_PCM_I2S0_RX, 925 .name = "PCM I2S0 RX", 926 .priority_high = 1, 927 .param.config = COH901318_CX_CFG_CH_DISABLE | 928 COH901318_CX_CFG_LCR_DISABLE | 929 COH901318_CX_CFG_TC_IRQ_ENABLE | 930 COH901318_CX_CFG_BE_IRQ_ENABLE, 931 .param.ctrl_lli_chained = 0 | 932 COH901318_CX_CTRL_TC_ENABLE | 933 COH901318_CX_CTRL_BURST_COUNT_16_BYTES | 934 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | 935 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | 936 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | 937 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | 938 COH901318_CX_CTRL_MASTER_MODE_M1RW | 939 COH901318_CX_CTRL_TCP_DISABLE | 940 COH901318_CX_CTRL_TC_IRQ_DISABLE | 941 COH901318_CX_CTRL_HSP_ENABLE | 942 COH901318_CX_CTRL_HSS_DISABLE | 943 COH901318_CX_CTRL_DDMA_LEGACY | 944 COH901318_CX_CTRL_PRDD_DEST, 945 .param.ctrl_lli = 0 | 946 COH901318_CX_CTRL_TC_ENABLE | 947 COH901318_CX_CTRL_BURST_COUNT_16_BYTES | 948 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | 949 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | 950 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | 951 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | 952 COH901318_CX_CTRL_MASTER_MODE_M1RW | 953 COH901318_CX_CTRL_TCP_ENABLE | 954 COH901318_CX_CTRL_TC_IRQ_DISABLE | 955 COH901318_CX_CTRL_HSP_ENABLE | 956 COH901318_CX_CTRL_HSS_DISABLE | 957 COH901318_CX_CTRL_DDMA_LEGACY | 958 COH901318_CX_CTRL_PRDD_DEST, 959 .param.ctrl_lli_last = 0 | 960 COH901318_CX_CTRL_TC_ENABLE | 961 COH901318_CX_CTRL_BURST_COUNT_16_BYTES | 962 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | 963 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | 964 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | 965 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | 966 COH901318_CX_CTRL_MASTER_MODE_M1RW | 967 COH901318_CX_CTRL_TCP_ENABLE | 968 COH901318_CX_CTRL_TC_IRQ_ENABLE | 969 COH901318_CX_CTRL_HSP_ENABLE | 970 COH901318_CX_CTRL_HSS_DISABLE | 971 COH901318_CX_CTRL_DDMA_LEGACY | 972 COH901318_CX_CTRL_PRDD_DEST, 973 }, 974 { 975 .number = U300_DMA_PCM_I2S1_TX, 976 .name = "PCM I2S1 TX", 977 .priority_high = 1, 978 .param.config = COH901318_CX_CFG_CH_DISABLE | 979 COH901318_CX_CFG_LCR_DISABLE | 980 COH901318_CX_CFG_TC_IRQ_ENABLE | 981 COH901318_CX_CFG_BE_IRQ_ENABLE, 982 .param.ctrl_lli_chained = 0 | 983 COH901318_CX_CTRL_TC_ENABLE | 984 COH901318_CX_CTRL_BURST_COUNT_16_BYTES | 985 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | 986 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | 987 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | 988 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | 989 COH901318_CX_CTRL_MASTER_MODE_M1RW | 990 COH901318_CX_CTRL_TCP_DISABLE | 991 COH901318_CX_CTRL_TC_IRQ_DISABLE | 992 COH901318_CX_CTRL_HSP_ENABLE | 993 COH901318_CX_CTRL_HSS_DISABLE | 994 COH901318_CX_CTRL_DDMA_LEGACY | 995 COH901318_CX_CTRL_PRDD_SOURCE, 996 .param.ctrl_lli = 0 | 997 COH901318_CX_CTRL_TC_ENABLE | 998 COH901318_CX_CTRL_BURST_COUNT_16_BYTES | 999 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | 1000 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | 1001 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | 1002 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | 1003 COH901318_CX_CTRL_MASTER_MODE_M1RW | 1004 COH901318_CX_CTRL_TCP_ENABLE | 1005 COH901318_CX_CTRL_TC_IRQ_DISABLE | 1006 COH901318_CX_CTRL_HSP_ENABLE | 1007 COH901318_CX_CTRL_HSS_DISABLE | 1008 COH901318_CX_CTRL_DDMA_LEGACY | 1009 COH901318_CX_CTRL_PRDD_SOURCE, 1010 .param.ctrl_lli_last = 0 | 1011 COH901318_CX_CTRL_TC_ENABLE | 1012 COH901318_CX_CTRL_BURST_COUNT_16_BYTES | 1013 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | 1014 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | 1015 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | 1016 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | 1017 COH901318_CX_CTRL_MASTER_MODE_M1RW | 1018 COH901318_CX_CTRL_TCP_ENABLE | 1019 COH901318_CX_CTRL_TC_IRQ_ENABLE | 1020 COH901318_CX_CTRL_HSP_ENABLE | 1021 COH901318_CX_CTRL_HSS_DISABLE | 1022 COH901318_CX_CTRL_DDMA_LEGACY | 1023 COH901318_CX_CTRL_PRDD_SOURCE, 1024 }, 1025 { 1026 .number = U300_DMA_PCM_I2S1_RX, 1027 .name = "PCM I2S1 RX", 1028 .priority_high = 1, 1029 .param.config = COH901318_CX_CFG_CH_DISABLE | 1030 COH901318_CX_CFG_LCR_DISABLE | 1031 COH901318_CX_CFG_TC_IRQ_ENABLE | 1032 COH901318_CX_CFG_BE_IRQ_ENABLE, 1033 .param.ctrl_lli_chained = 0 | 1034 COH901318_CX_CTRL_TC_ENABLE | 1035 COH901318_CX_CTRL_BURST_COUNT_16_BYTES | 1036 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | 1037 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | 1038 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | 1039 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | 1040 COH901318_CX_CTRL_MASTER_MODE_M1RW | 1041 COH901318_CX_CTRL_TCP_DISABLE | 1042 COH901318_CX_CTRL_TC_IRQ_DISABLE | 1043 COH901318_CX_CTRL_HSP_ENABLE | 1044 COH901318_CX_CTRL_HSS_DISABLE | 1045 COH901318_CX_CTRL_DDMA_LEGACY | 1046 COH901318_CX_CTRL_PRDD_DEST, 1047 .param.ctrl_lli = 0 | 1048 COH901318_CX_CTRL_TC_ENABLE | 1049 COH901318_CX_CTRL_BURST_COUNT_16_BYTES | 1050 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | 1051 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | 1052 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | 1053 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | 1054 COH901318_CX_CTRL_MASTER_MODE_M1RW | 1055 COH901318_CX_CTRL_TCP_ENABLE | 1056 COH901318_CX_CTRL_TC_IRQ_DISABLE | 1057 COH901318_CX_CTRL_HSP_ENABLE | 1058 COH901318_CX_CTRL_HSS_DISABLE | 1059 COH901318_CX_CTRL_DDMA_LEGACY | 1060 COH901318_CX_CTRL_PRDD_DEST, 1061 .param.ctrl_lli_last = 0 | 1062 COH901318_CX_CTRL_TC_ENABLE | 1063 COH901318_CX_CTRL_BURST_COUNT_16_BYTES | 1064 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | 1065 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | 1066 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | 1067 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | 1068 COH901318_CX_CTRL_MASTER_MODE_M1RW | 1069 COH901318_CX_CTRL_TCP_ENABLE | 1070 COH901318_CX_CTRL_TC_IRQ_ENABLE | 1071 COH901318_CX_CTRL_HSP_ENABLE | 1072 COH901318_CX_CTRL_HSS_DISABLE | 1073 COH901318_CX_CTRL_DDMA_LEGACY | 1074 COH901318_CX_CTRL_PRDD_DEST, 1075 }, 1076 { 1077 .number = U300_DMA_XGAM_CDI, 1078 .name = "XGAM CDI", 1079 .priority_high = 0, 1080 }, 1081 { 1082 .number = U300_DMA_XGAM_PDI, 1083 .name = "XGAM PDI", 1084 .priority_high = 0, 1085 }, 1086 /* 1087 * Don't set up device address, burst count or size of src 1088 * or dst bus for this peripheral - handled by PrimeCell 1089 * DMA extension. 1090 */ 1091 { 1092 .number = U300_DMA_SPI_TX, 1093 .name = "SPI TX", 1094 .priority_high = 0, 1095 .param.config = COH901318_CX_CFG_CH_DISABLE | 1096 COH901318_CX_CFG_LCR_DISABLE | 1097 COH901318_CX_CFG_TC_IRQ_ENABLE | 1098 COH901318_CX_CFG_BE_IRQ_ENABLE, 1099 .param.ctrl_lli_chained = 0 | 1100 COH901318_CX_CTRL_TC_ENABLE | 1101 COH901318_CX_CTRL_MASTER_MODE_M1RW | 1102 COH901318_CX_CTRL_TCP_DISABLE | 1103 COH901318_CX_CTRL_TC_IRQ_DISABLE | 1104 COH901318_CX_CTRL_HSP_ENABLE | 1105 COH901318_CX_CTRL_HSS_DISABLE | 1106 COH901318_CX_CTRL_DDMA_LEGACY, 1107 .param.ctrl_lli = 0 | 1108 COH901318_CX_CTRL_TC_ENABLE | 1109 COH901318_CX_CTRL_MASTER_MODE_M1RW | 1110 COH901318_CX_CTRL_TCP_DISABLE | 1111 COH901318_CX_CTRL_TC_IRQ_ENABLE | 1112 COH901318_CX_CTRL_HSP_ENABLE | 1113 COH901318_CX_CTRL_HSS_DISABLE | 1114 COH901318_CX_CTRL_DDMA_LEGACY, 1115 .param.ctrl_lli_last = 0 | 1116 COH901318_CX_CTRL_TC_ENABLE | 1117 COH901318_CX_CTRL_MASTER_MODE_M1RW | 1118 COH901318_CX_CTRL_TCP_DISABLE | 1119 COH901318_CX_CTRL_TC_IRQ_ENABLE | 1120 COH901318_CX_CTRL_HSP_ENABLE | 1121 COH901318_CX_CTRL_HSS_DISABLE | 1122 COH901318_CX_CTRL_DDMA_LEGACY, 1123 }, 1124 { 1125 .number = U300_DMA_SPI_RX, 1126 .name = "SPI RX", 1127 .priority_high = 0, 1128 .param.config = COH901318_CX_CFG_CH_DISABLE | 1129 COH901318_CX_CFG_LCR_DISABLE | 1130 COH901318_CX_CFG_TC_IRQ_ENABLE | 1131 COH901318_CX_CFG_BE_IRQ_ENABLE, 1132 .param.ctrl_lli_chained = 0 | 1133 COH901318_CX_CTRL_TC_ENABLE | 1134 COH901318_CX_CTRL_MASTER_MODE_M1RW | 1135 COH901318_CX_CTRL_TCP_DISABLE | 1136 COH901318_CX_CTRL_TC_IRQ_DISABLE | 1137 COH901318_CX_CTRL_HSP_ENABLE | 1138 COH901318_CX_CTRL_HSS_DISABLE | 1139 COH901318_CX_CTRL_DDMA_LEGACY, 1140 .param.ctrl_lli = 0 | 1141 COH901318_CX_CTRL_TC_ENABLE | 1142 COH901318_CX_CTRL_MASTER_MODE_M1RW | 1143 COH901318_CX_CTRL_TCP_DISABLE | 1144 COH901318_CX_CTRL_TC_IRQ_ENABLE | 1145 COH901318_CX_CTRL_HSP_ENABLE | 1146 COH901318_CX_CTRL_HSS_DISABLE | 1147 COH901318_CX_CTRL_DDMA_LEGACY, 1148 .param.ctrl_lli_last = 0 | 1149 COH901318_CX_CTRL_TC_ENABLE | 1150 COH901318_CX_CTRL_MASTER_MODE_M1RW | 1151 COH901318_CX_CTRL_TCP_DISABLE | 1152 COH901318_CX_CTRL_TC_IRQ_ENABLE | 1153 COH901318_CX_CTRL_HSP_ENABLE | 1154 COH901318_CX_CTRL_HSS_DISABLE | 1155 COH901318_CX_CTRL_DDMA_LEGACY, 1156 1157 }, 1158 { 1159 .number = U300_DMA_GENERAL_PURPOSE_0, 1160 .name = "GENERAL 00", 1161 .priority_high = 0, 1162 1163 .param.config = flags_memcpy_config, 1164 .param.ctrl_lli_chained = flags_memcpy_lli_chained, 1165 .param.ctrl_lli = flags_memcpy_lli, 1166 .param.ctrl_lli_last = flags_memcpy_lli_last, 1167 }, 1168 { 1169 .number = U300_DMA_GENERAL_PURPOSE_1, 1170 .name = "GENERAL 01", 1171 .priority_high = 0, 1172 1173 .param.config = flags_memcpy_config, 1174 .param.ctrl_lli_chained = flags_memcpy_lli_chained, 1175 .param.ctrl_lli = flags_memcpy_lli, 1176 .param.ctrl_lli_last = flags_memcpy_lli_last, 1177 }, 1178 { 1179 .number = U300_DMA_GENERAL_PURPOSE_2, 1180 .name = "GENERAL 02", 1181 .priority_high = 0, 1182 1183 .param.config = flags_memcpy_config, 1184 .param.ctrl_lli_chained = flags_memcpy_lli_chained, 1185 .param.ctrl_lli = flags_memcpy_lli, 1186 .param.ctrl_lli_last = flags_memcpy_lli_last, 1187 }, 1188 { 1189 .number = U300_DMA_GENERAL_PURPOSE_3, 1190 .name = "GENERAL 03", 1191 .priority_high = 0, 1192 1193 .param.config = flags_memcpy_config, 1194 .param.ctrl_lli_chained = flags_memcpy_lli_chained, 1195 .param.ctrl_lli = flags_memcpy_lli, 1196 .param.ctrl_lli_last = flags_memcpy_lli_last, 1197 }, 1198 { 1199 .number = U300_DMA_GENERAL_PURPOSE_4, 1200 .name = "GENERAL 04", 1201 .priority_high = 0, 1202 1203 .param.config = flags_memcpy_config, 1204 .param.ctrl_lli_chained = flags_memcpy_lli_chained, 1205 .param.ctrl_lli = flags_memcpy_lli, 1206 .param.ctrl_lli_last = flags_memcpy_lli_last, 1207 }, 1208 { 1209 .number = U300_DMA_GENERAL_PURPOSE_5, 1210 .name = "GENERAL 05", 1211 .priority_high = 0, 1212 1213 .param.config = flags_memcpy_config, 1214 .param.ctrl_lli_chained = flags_memcpy_lli_chained, 1215 .param.ctrl_lli = flags_memcpy_lli, 1216 .param.ctrl_lli_last = flags_memcpy_lli_last, 1217 }, 1218 { 1219 .number = U300_DMA_GENERAL_PURPOSE_6, 1220 .name = "GENERAL 06", 1221 .priority_high = 0, 1222 1223 .param.config = flags_memcpy_config, 1224 .param.ctrl_lli_chained = flags_memcpy_lli_chained, 1225 .param.ctrl_lli = flags_memcpy_lli, 1226 .param.ctrl_lli_last = flags_memcpy_lli_last, 1227 }, 1228 { 1229 .number = U300_DMA_GENERAL_PURPOSE_7, 1230 .name = "GENERAL 07", 1231 .priority_high = 0, 1232 1233 .param.config = flags_memcpy_config, 1234 .param.ctrl_lli_chained = flags_memcpy_lli_chained, 1235 .param.ctrl_lli = flags_memcpy_lli, 1236 .param.ctrl_lli_last = flags_memcpy_lli_last, 1237 }, 1238 { 1239 .number = U300_DMA_GENERAL_PURPOSE_8, 1240 .name = "GENERAL 08", 1241 .priority_high = 0, 1242 1243 .param.config = flags_memcpy_config, 1244 .param.ctrl_lli_chained = flags_memcpy_lli_chained, 1245 .param.ctrl_lli = flags_memcpy_lli, 1246 .param.ctrl_lli_last = flags_memcpy_lli_last, 1247 }, 1248 { 1249 .number = U300_DMA_UART1_TX, 1250 .name = "UART1 TX", 1251 .priority_high = 0, 1252 }, 1253 { 1254 .number = U300_DMA_UART1_RX, 1255 .name = "UART1 RX", 1256 .priority_high = 0, 1257 } 1258}; 1259 1260#define COHC_2_DEV(cohc) (&cohc->chan.dev->device) 1261 1262#ifdef VERBOSE_DEBUG 1263#define COH_DBG(x) ({ if (1) x; 0; }) 1264#else 1265#define COH_DBG(x) ({ if (0) x; 0; }) 1266#endif 1267 1268struct coh901318_desc { 1269 struct dma_async_tx_descriptor desc; 1270 struct list_head node; 1271 struct scatterlist *sg; 1272 unsigned int sg_len; 1273 struct coh901318_lli *lli; 1274 enum dma_transfer_direction dir; 1275 unsigned long flags; 1276 u32 head_config; 1277 u32 head_ctrl; 1278}; 1279 1280struct coh901318_base { 1281 struct device *dev; 1282 void __iomem *virtbase; 1283 unsigned int irq; 1284 struct coh901318_pool pool; 1285 struct powersave pm; 1286 struct dma_device dma_slave; 1287 struct dma_device dma_memcpy; 1288 struct coh901318_chan *chans; 1289}; 1290 1291struct coh901318_chan { 1292 spinlock_t lock; 1293 int allocated; 1294 int id; 1295 int stopped; 1296 1297 struct work_struct free_work; 1298 struct dma_chan chan; 1299 1300 struct tasklet_struct tasklet; 1301 1302 struct list_head active; 1303 struct list_head queue; 1304 struct list_head free; 1305 1306 unsigned long nbr_active_done; 1307 unsigned long busy; 1308 1309 struct dma_slave_config config; 1310 u32 addr; 1311 u32 ctrl; 1312 1313 struct coh901318_base *base; 1314}; 1315 1316static void coh901318_list_print(struct coh901318_chan *cohc, 1317 struct coh901318_lli *lli) 1318{ 1319 struct coh901318_lli *l = lli; 1320 int i = 0; 1321 1322 while (l) { 1323 dev_vdbg(COHC_2_DEV(cohc), "i %d, lli %p, ctrl 0x%x, src %pad" 1324 ", dst %pad, link %pad virt_link_addr 0x%p\n", 1325 i, l, l->control, &l->src_addr, &l->dst_addr, 1326 &l->link_addr, l->virt_link_addr); 1327 i++; 1328 l = l->virt_link_addr; 1329 } 1330} 1331 1332#ifdef CONFIG_DEBUG_FS 1333 1334#define COH901318_DEBUGFS_ASSIGN(x, y) (x = y) 1335 1336static struct coh901318_base *debugfs_dma_base; 1337static struct dentry *dma_dentry; 1338 1339static ssize_t coh901318_debugfs_read(struct file *file, char __user *buf, 1340 size_t count, loff_t *f_pos) 1341{ 1342 u64 started_channels = debugfs_dma_base->pm.started_channels; 1343 int pool_count = debugfs_dma_base->pool.debugfs_pool_counter; 1344 char *dev_buf; 1345 char *tmp; 1346 int ret; 1347 int i; 1348 1349 dev_buf = kmalloc(4*1024, GFP_KERNEL); 1350 if (dev_buf == NULL) 1351 return -ENOMEM; 1352 tmp = dev_buf; 1353 1354 tmp += sprintf(tmp, "DMA -- enabled dma channels\n"); 1355 1356 for (i = 0; i < U300_DMA_CHANNELS; i++) { 1357 if (started_channels & (1ULL << i)) 1358 tmp += sprintf(tmp, "channel %d\n", i); 1359 } 1360 1361 tmp += sprintf(tmp, "Pool alloc nbr %d\n", pool_count); 1362 1363 ret = simple_read_from_buffer(buf, count, f_pos, dev_buf, 1364 tmp - dev_buf); 1365 kfree(dev_buf); 1366 return ret; 1367} 1368 1369static const struct file_operations coh901318_debugfs_status_operations = { 1370 .open = simple_open, 1371 .read = coh901318_debugfs_read, 1372 .llseek = default_llseek, 1373}; 1374 1375 1376static int __init init_coh901318_debugfs(void) 1377{ 1378 1379 dma_dentry = debugfs_create_dir("dma", NULL); 1380 1381 debugfs_create_file("status", S_IFREG | S_IRUGO, dma_dentry, NULL, 1382 &coh901318_debugfs_status_operations); 1383 return 0; 1384} 1385 1386static void __exit exit_coh901318_debugfs(void) 1387{ 1388 debugfs_remove_recursive(dma_dentry); 1389} 1390 1391module_init(init_coh901318_debugfs); 1392module_exit(exit_coh901318_debugfs); 1393#else 1394 1395#define COH901318_DEBUGFS_ASSIGN(x, y) 1396 1397#endif /* CONFIG_DEBUG_FS */ 1398 1399static inline struct coh901318_chan *to_coh901318_chan(struct dma_chan *chan) 1400{ 1401 return container_of(chan, struct coh901318_chan, chan); 1402} 1403 1404static int coh901318_dma_set_runtimeconfig(struct dma_chan *chan, 1405 struct dma_slave_config *config, 1406 enum dma_transfer_direction direction); 1407 1408static inline const struct coh901318_params * 1409cohc_chan_param(struct coh901318_chan *cohc) 1410{ 1411 return &chan_config[cohc->id].param; 1412} 1413 1414static inline const struct coh_dma_channel * 1415cohc_chan_conf(struct coh901318_chan *cohc) 1416{ 1417 return &chan_config[cohc->id]; 1418} 1419 1420static void enable_powersave(struct coh901318_chan *cohc) 1421{ 1422 unsigned long flags; 1423 struct powersave *pm = &cohc->base->pm; 1424 1425 spin_lock_irqsave(&pm->lock, flags); 1426 1427 pm->started_channels &= ~(1ULL << cohc->id); 1428 1429 spin_unlock_irqrestore(&pm->lock, flags); 1430} 1431static void disable_powersave(struct coh901318_chan *cohc) 1432{ 1433 unsigned long flags; 1434 struct powersave *pm = &cohc->base->pm; 1435 1436 spin_lock_irqsave(&pm->lock, flags); 1437 1438 pm->started_channels |= (1ULL << cohc->id); 1439 1440 spin_unlock_irqrestore(&pm->lock, flags); 1441} 1442 1443static inline int coh901318_set_ctrl(struct coh901318_chan *cohc, u32 control) 1444{ 1445 int channel = cohc->id; 1446 void __iomem *virtbase = cohc->base->virtbase; 1447 1448 writel(control, 1449 virtbase + COH901318_CX_CTRL + 1450 COH901318_CX_CTRL_SPACING * channel); 1451 return 0; 1452} 1453 1454static inline int coh901318_set_conf(struct coh901318_chan *cohc, u32 conf) 1455{ 1456 int channel = cohc->id; 1457 void __iomem *virtbase = cohc->base->virtbase; 1458 1459 writel(conf, 1460 virtbase + COH901318_CX_CFG + 1461 COH901318_CX_CFG_SPACING*channel); 1462 return 0; 1463} 1464 1465 1466static int coh901318_start(struct coh901318_chan *cohc) 1467{ 1468 u32 val; 1469 int channel = cohc->id; 1470 void __iomem *virtbase = cohc->base->virtbase; 1471 1472 disable_powersave(cohc); 1473 1474 val = readl(virtbase + COH901318_CX_CFG + 1475 COH901318_CX_CFG_SPACING * channel); 1476 1477 /* Enable channel */ 1478 val |= COH901318_CX_CFG_CH_ENABLE; 1479 writel(val, virtbase + COH901318_CX_CFG + 1480 COH901318_CX_CFG_SPACING * channel); 1481 1482 return 0; 1483} 1484 1485static int coh901318_prep_linked_list(struct coh901318_chan *cohc, 1486 struct coh901318_lli *lli) 1487{ 1488 int channel = cohc->id; 1489 void __iomem *virtbase = cohc->base->virtbase; 1490 1491 BUG_ON(readl(virtbase + COH901318_CX_STAT + 1492 COH901318_CX_STAT_SPACING*channel) & 1493 COH901318_CX_STAT_ACTIVE); 1494 1495 writel(lli->src_addr, 1496 virtbase + COH901318_CX_SRC_ADDR + 1497 COH901318_CX_SRC_ADDR_SPACING * channel); 1498 1499 writel(lli->dst_addr, virtbase + 1500 COH901318_CX_DST_ADDR + 1501 COH901318_CX_DST_ADDR_SPACING * channel); 1502 1503 writel(lli->link_addr, virtbase + COH901318_CX_LNK_ADDR + 1504 COH901318_CX_LNK_ADDR_SPACING * channel); 1505 1506 writel(lli->control, virtbase + COH901318_CX_CTRL + 1507 COH901318_CX_CTRL_SPACING * channel); 1508 1509 return 0; 1510} 1511 1512static struct coh901318_desc * 1513coh901318_desc_get(struct coh901318_chan *cohc) 1514{ 1515 struct coh901318_desc *desc; 1516 1517 if (list_empty(&cohc->free)) { 1518 /* alloc new desc because we're out of used ones 1519 * TODO: alloc a pile of descs instead of just one, 1520 * avoid many small allocations. 1521 */ 1522 desc = kzalloc(sizeof(struct coh901318_desc), GFP_NOWAIT); 1523 if (desc == NULL) 1524 goto out; 1525 INIT_LIST_HEAD(&desc->node…
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