/drivers/i2c/busses/i2c-ocores.c

http://github.com/mirrors/linux · C · 818 lines · 612 code · 120 blank · 86 comment · 114 complexity · bb17dd1a3e776e9b17defe13b8c07fdd MD5 · raw file

  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * i2c-ocores.c: I2C bus driver for OpenCores I2C controller
  4. * (https://opencores.org/project/i2c/overview)
  5. *
  6. * Peter Korsgaard <peter@korsgaard.com>
  7. *
  8. * Support for the GRLIB port of the controller by
  9. * Andreas Larsson <andreas@gaisler.com>
  10. */
  11. #include <linux/clk.h>
  12. #include <linux/delay.h>
  13. #include <linux/err.h>
  14. #include <linux/kernel.h>
  15. #include <linux/module.h>
  16. #include <linux/errno.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/i2c.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/wait.h>
  21. #include <linux/platform_data/i2c-ocores.h>
  22. #include <linux/slab.h>
  23. #include <linux/io.h>
  24. #include <linux/log2.h>
  25. #include <linux/spinlock.h>
  26. #include <linux/jiffies.h>
  27. /*
  28. * 'process_lock' exists because ocores_process() and ocores_process_timeout()
  29. * can't run in parallel.
  30. */
  31. struct ocores_i2c {
  32. void __iomem *base;
  33. int iobase;
  34. u32 reg_shift;
  35. u32 reg_io_width;
  36. unsigned long flags;
  37. wait_queue_head_t wait;
  38. struct i2c_adapter adap;
  39. struct i2c_msg *msg;
  40. int pos;
  41. int nmsgs;
  42. int state; /* see STATE_ */
  43. spinlock_t process_lock;
  44. struct clk *clk;
  45. int ip_clock_khz;
  46. int bus_clock_khz;
  47. void (*setreg)(struct ocores_i2c *i2c, int reg, u8 value);
  48. u8 (*getreg)(struct ocores_i2c *i2c, int reg);
  49. };
  50. /* registers */
  51. #define OCI2C_PRELOW 0
  52. #define OCI2C_PREHIGH 1
  53. #define OCI2C_CONTROL 2
  54. #define OCI2C_DATA 3
  55. #define OCI2C_CMD 4 /* write only */
  56. #define OCI2C_STATUS 4 /* read only, same address as OCI2C_CMD */
  57. #define OCI2C_CTRL_IEN 0x40
  58. #define OCI2C_CTRL_EN 0x80
  59. #define OCI2C_CMD_START 0x91
  60. #define OCI2C_CMD_STOP 0x41
  61. #define OCI2C_CMD_READ 0x21
  62. #define OCI2C_CMD_WRITE 0x11
  63. #define OCI2C_CMD_READ_ACK 0x21
  64. #define OCI2C_CMD_READ_NACK 0x29
  65. #define OCI2C_CMD_IACK 0x01
  66. #define OCI2C_STAT_IF 0x01
  67. #define OCI2C_STAT_TIP 0x02
  68. #define OCI2C_STAT_ARBLOST 0x20
  69. #define OCI2C_STAT_BUSY 0x40
  70. #define OCI2C_STAT_NACK 0x80
  71. #define STATE_DONE 0
  72. #define STATE_START 1
  73. #define STATE_WRITE 2
  74. #define STATE_READ 3
  75. #define STATE_ERROR 4
  76. #define TYPE_OCORES 0
  77. #define TYPE_GRLIB 1
  78. #define TYPE_SIFIVE_REV0 2
  79. #define OCORES_FLAG_BROKEN_IRQ BIT(1) /* Broken IRQ for FU540-C000 SoC */
  80. static void oc_setreg_8(struct ocores_i2c *i2c, int reg, u8 value)
  81. {
  82. iowrite8(value, i2c->base + (reg << i2c->reg_shift));
  83. }
  84. static void oc_setreg_16(struct ocores_i2c *i2c, int reg, u8 value)
  85. {
  86. iowrite16(value, i2c->base + (reg << i2c->reg_shift));
  87. }
  88. static void oc_setreg_32(struct ocores_i2c *i2c, int reg, u8 value)
  89. {
  90. iowrite32(value, i2c->base + (reg << i2c->reg_shift));
  91. }
  92. static void oc_setreg_16be(struct ocores_i2c *i2c, int reg, u8 value)
  93. {
  94. iowrite16be(value, i2c->base + (reg << i2c->reg_shift));
  95. }
  96. static void oc_setreg_32be(struct ocores_i2c *i2c, int reg, u8 value)
  97. {
  98. iowrite32be(value, i2c->base + (reg << i2c->reg_shift));
  99. }
  100. static inline u8 oc_getreg_8(struct ocores_i2c *i2c, int reg)
  101. {
  102. return ioread8(i2c->base + (reg << i2c->reg_shift));
  103. }
  104. static inline u8 oc_getreg_16(struct ocores_i2c *i2c, int reg)
  105. {
  106. return ioread16(i2c->base + (reg << i2c->reg_shift));
  107. }
  108. static inline u8 oc_getreg_32(struct ocores_i2c *i2c, int reg)
  109. {
  110. return ioread32(i2c->base + (reg << i2c->reg_shift));
  111. }
  112. static inline u8 oc_getreg_16be(struct ocores_i2c *i2c, int reg)
  113. {
  114. return ioread16be(i2c->base + (reg << i2c->reg_shift));
  115. }
  116. static inline u8 oc_getreg_32be(struct ocores_i2c *i2c, int reg)
  117. {
  118. return ioread32be(i2c->base + (reg << i2c->reg_shift));
  119. }
  120. static void oc_setreg_io_8(struct ocores_i2c *i2c, int reg, u8 value)
  121. {
  122. outb(value, i2c->iobase + reg);
  123. }
  124. static inline u8 oc_getreg_io_8(struct ocores_i2c *i2c, int reg)
  125. {
  126. return inb(i2c->iobase + reg);
  127. }
  128. static inline void oc_setreg(struct ocores_i2c *i2c, int reg, u8 value)
  129. {
  130. i2c->setreg(i2c, reg, value);
  131. }
  132. static inline u8 oc_getreg(struct ocores_i2c *i2c, int reg)
  133. {
  134. return i2c->getreg(i2c, reg);
  135. }
  136. static void ocores_process(struct ocores_i2c *i2c, u8 stat)
  137. {
  138. struct i2c_msg *msg = i2c->msg;
  139. unsigned long flags;
  140. /*
  141. * If we spin here is because we are in timeout, so we are going
  142. * to be in STATE_ERROR. See ocores_process_timeout()
  143. */
  144. spin_lock_irqsave(&i2c->process_lock, flags);
  145. if ((i2c->state == STATE_DONE) || (i2c->state == STATE_ERROR)) {
  146. /* stop has been sent */
  147. oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
  148. wake_up(&i2c->wait);
  149. goto out;
  150. }
  151. /* error? */
  152. if (stat & OCI2C_STAT_ARBLOST) {
  153. i2c->state = STATE_ERROR;
  154. oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
  155. goto out;
  156. }
  157. if ((i2c->state == STATE_START) || (i2c->state == STATE_WRITE)) {
  158. i2c->state =
  159. (msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE;
  160. if (stat & OCI2C_STAT_NACK) {
  161. i2c->state = STATE_ERROR;
  162. oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
  163. goto out;
  164. }
  165. } else {
  166. msg->buf[i2c->pos++] = oc_getreg(i2c, OCI2C_DATA);
  167. }
  168. /* end of msg? */
  169. if (i2c->pos == msg->len) {
  170. i2c->nmsgs--;
  171. i2c->msg++;
  172. i2c->pos = 0;
  173. msg = i2c->msg;
  174. if (i2c->nmsgs) { /* end? */
  175. /* send start? */
  176. if (!(msg->flags & I2C_M_NOSTART)) {
  177. u8 addr = i2c_8bit_addr_from_msg(msg);
  178. i2c->state = STATE_START;
  179. oc_setreg(i2c, OCI2C_DATA, addr);
  180. oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);
  181. goto out;
  182. }
  183. i2c->state = (msg->flags & I2C_M_RD)
  184. ? STATE_READ : STATE_WRITE;
  185. } else {
  186. i2c->state = STATE_DONE;
  187. oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
  188. goto out;
  189. }
  190. }
  191. if (i2c->state == STATE_READ) {
  192. oc_setreg(i2c, OCI2C_CMD, i2c->pos == (msg->len-1) ?
  193. OCI2C_CMD_READ_NACK : OCI2C_CMD_READ_ACK);
  194. } else {
  195. oc_setreg(i2c, OCI2C_DATA, msg->buf[i2c->pos++]);
  196. oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_WRITE);
  197. }
  198. out:
  199. spin_unlock_irqrestore(&i2c->process_lock, flags);
  200. }
  201. static irqreturn_t ocores_isr(int irq, void *dev_id)
  202. {
  203. struct ocores_i2c *i2c = dev_id;
  204. u8 stat = oc_getreg(i2c, OCI2C_STATUS);
  205. if (i2c->flags & OCORES_FLAG_BROKEN_IRQ) {
  206. if ((stat & OCI2C_STAT_IF) && !(stat & OCI2C_STAT_BUSY))
  207. return IRQ_NONE;
  208. } else if (!(stat & OCI2C_STAT_IF)) {
  209. return IRQ_NONE;
  210. }
  211. ocores_process(i2c, stat);
  212. return IRQ_HANDLED;
  213. }
  214. /**
  215. * Process timeout event
  216. * @i2c: ocores I2C device instance
  217. */
  218. static void ocores_process_timeout(struct ocores_i2c *i2c)
  219. {
  220. unsigned long flags;
  221. spin_lock_irqsave(&i2c->process_lock, flags);
  222. i2c->state = STATE_ERROR;
  223. oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
  224. spin_unlock_irqrestore(&i2c->process_lock, flags);
  225. }
  226. /**
  227. * Wait until something change in a given register
  228. * @i2c: ocores I2C device instance
  229. * @reg: register to query
  230. * @mask: bitmask to apply on register value
  231. * @val: expected result
  232. * @timeout: timeout in jiffies
  233. *
  234. * Timeout is necessary to avoid to stay here forever when the chip
  235. * does not answer correctly.
  236. *
  237. * Return: 0 on success, -ETIMEDOUT on timeout
  238. */
  239. static int ocores_wait(struct ocores_i2c *i2c,
  240. int reg, u8 mask, u8 val,
  241. const unsigned long timeout)
  242. {
  243. unsigned long j;
  244. j = jiffies + timeout;
  245. while (1) {
  246. u8 status = oc_getreg(i2c, reg);
  247. if ((status & mask) == val)
  248. break;
  249. if (time_after(jiffies, j))
  250. return -ETIMEDOUT;
  251. }
  252. return 0;
  253. }
  254. /**
  255. * Wait until is possible to process some data
  256. * @i2c: ocores I2C device instance
  257. *
  258. * Used when the device is in polling mode (interrupts disabled).
  259. *
  260. * Return: 0 on success, -ETIMEDOUT on timeout
  261. */
  262. static int ocores_poll_wait(struct ocores_i2c *i2c)
  263. {
  264. u8 mask;
  265. int err;
  266. if (i2c->state == STATE_DONE || i2c->state == STATE_ERROR) {
  267. /* transfer is over */
  268. mask = OCI2C_STAT_BUSY;
  269. } else {
  270. /* on going transfer */
  271. mask = OCI2C_STAT_TIP;
  272. /*
  273. * We wait for the data to be transferred (8bit),
  274. * then we start polling on the ACK/NACK bit
  275. */
  276. udelay((8 * 1000) / i2c->bus_clock_khz);
  277. }
  278. /*
  279. * once we are here we expect to get the expected result immediately
  280. * so if after 1ms we timeout then something is broken.
  281. */
  282. err = ocores_wait(i2c, OCI2C_STATUS, mask, 0, msecs_to_jiffies(1));
  283. if (err)
  284. dev_warn(i2c->adap.dev.parent,
  285. "%s: STATUS timeout, bit 0x%x did not clear in 1ms\n",
  286. __func__, mask);
  287. return err;
  288. }
  289. /**
  290. * It handles an IRQ-less transfer
  291. * @i2c: ocores I2C device instance
  292. *
  293. * Even if IRQ are disabled, the I2C OpenCore IP behavior is exactly the same
  294. * (only that IRQ are not produced). This means that we can re-use entirely
  295. * ocores_isr(), we just add our polling code around it.
  296. *
  297. * It can run in atomic context
  298. */
  299. static void ocores_process_polling(struct ocores_i2c *i2c)
  300. {
  301. while (1) {
  302. irqreturn_t ret;
  303. int err;
  304. err = ocores_poll_wait(i2c);
  305. if (err) {
  306. i2c->state = STATE_ERROR;
  307. break; /* timeout */
  308. }
  309. ret = ocores_isr(-1, i2c);
  310. if (ret == IRQ_NONE)
  311. break; /* all messages have been transferred */
  312. else {
  313. if (i2c->flags & OCORES_FLAG_BROKEN_IRQ)
  314. if (i2c->state == STATE_DONE)
  315. break;
  316. }
  317. }
  318. }
  319. static int ocores_xfer_core(struct ocores_i2c *i2c,
  320. struct i2c_msg *msgs, int num,
  321. bool polling)
  322. {
  323. int ret;
  324. u8 ctrl;
  325. ctrl = oc_getreg(i2c, OCI2C_CONTROL);
  326. if (polling)
  327. oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~OCI2C_CTRL_IEN);
  328. else
  329. oc_setreg(i2c, OCI2C_CONTROL, ctrl | OCI2C_CTRL_IEN);
  330. i2c->msg = msgs;
  331. i2c->pos = 0;
  332. i2c->nmsgs = num;
  333. i2c->state = STATE_START;
  334. oc_setreg(i2c, OCI2C_DATA, i2c_8bit_addr_from_msg(i2c->msg));
  335. oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);
  336. if (polling) {
  337. ocores_process_polling(i2c);
  338. } else {
  339. ret = wait_event_timeout(i2c->wait,
  340. (i2c->state == STATE_ERROR) ||
  341. (i2c->state == STATE_DONE), HZ);
  342. if (ret == 0) {
  343. ocores_process_timeout(i2c);
  344. return -ETIMEDOUT;
  345. }
  346. }
  347. return (i2c->state == STATE_DONE) ? num : -EIO;
  348. }
  349. static int ocores_xfer_polling(struct i2c_adapter *adap,
  350. struct i2c_msg *msgs, int num)
  351. {
  352. return ocores_xfer_core(i2c_get_adapdata(adap), msgs, num, true);
  353. }
  354. static int ocores_xfer(struct i2c_adapter *adap,
  355. struct i2c_msg *msgs, int num)
  356. {
  357. return ocores_xfer_core(i2c_get_adapdata(adap), msgs, num, false);
  358. }
  359. static int ocores_init(struct device *dev, struct ocores_i2c *i2c)
  360. {
  361. int prescale;
  362. int diff;
  363. u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
  364. /* make sure the device is disabled */
  365. ctrl &= ~(OCI2C_CTRL_EN | OCI2C_CTRL_IEN);
  366. oc_setreg(i2c, OCI2C_CONTROL, ctrl);
  367. prescale = (i2c->ip_clock_khz / (5 * i2c->bus_clock_khz)) - 1;
  368. prescale = clamp(prescale, 0, 0xffff);
  369. diff = i2c->ip_clock_khz / (5 * (prescale + 1)) - i2c->bus_clock_khz;
  370. if (abs(diff) > i2c->bus_clock_khz / 10) {
  371. dev_err(dev,
  372. "Unsupported clock settings: core: %d KHz, bus: %d KHz\n",
  373. i2c->ip_clock_khz, i2c->bus_clock_khz);
  374. return -EINVAL;
  375. }
  376. oc_setreg(i2c, OCI2C_PRELOW, prescale & 0xff);
  377. oc_setreg(i2c, OCI2C_PREHIGH, prescale >> 8);
  378. /* Init the device */
  379. oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
  380. oc_setreg(i2c, OCI2C_CONTROL, ctrl | OCI2C_CTRL_EN);
  381. return 0;
  382. }
  383. static u32 ocores_func(struct i2c_adapter *adap)
  384. {
  385. return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
  386. }
  387. static struct i2c_algorithm ocores_algorithm = {
  388. .master_xfer = ocores_xfer,
  389. .master_xfer_atomic = ocores_xfer_polling,
  390. .functionality = ocores_func,
  391. };
  392. static const struct i2c_adapter ocores_adapter = {
  393. .owner = THIS_MODULE,
  394. .name = "i2c-ocores",
  395. .class = I2C_CLASS_DEPRECATED,
  396. .algo = &ocores_algorithm,
  397. };
  398. static const struct of_device_id ocores_i2c_match[] = {
  399. {
  400. .compatible = "opencores,i2c-ocores",
  401. .data = (void *)TYPE_OCORES,
  402. },
  403. {
  404. .compatible = "aeroflexgaisler,i2cmst",
  405. .data = (void *)TYPE_GRLIB,
  406. },
  407. {
  408. .compatible = "sifive,fu540-c000-i2c",
  409. .data = (void *)TYPE_SIFIVE_REV0,
  410. },
  411. {
  412. .compatible = "sifive,i2c0",
  413. .data = (void *)TYPE_SIFIVE_REV0,
  414. },
  415. {},
  416. };
  417. MODULE_DEVICE_TABLE(of, ocores_i2c_match);
  418. #ifdef CONFIG_OF
  419. /*
  420. * Read and write functions for the GRLIB port of the controller. Registers are
  421. * 32-bit big endian and the PRELOW and PREHIGH registers are merged into one
  422. * register. The subsequent registers have their offsets decreased accordingly.
  423. */
  424. static u8 oc_getreg_grlib(struct ocores_i2c *i2c, int reg)
  425. {
  426. u32 rd;
  427. int rreg = reg;
  428. if (reg != OCI2C_PRELOW)
  429. rreg--;
  430. rd = ioread32be(i2c->base + (rreg << i2c->reg_shift));
  431. if (reg == OCI2C_PREHIGH)
  432. return (u8)(rd >> 8);
  433. else
  434. return (u8)rd;
  435. }
  436. static void oc_setreg_grlib(struct ocores_i2c *i2c, int reg, u8 value)
  437. {
  438. u32 curr, wr;
  439. int rreg = reg;
  440. if (reg != OCI2C_PRELOW)
  441. rreg--;
  442. if (reg == OCI2C_PRELOW || reg == OCI2C_PREHIGH) {
  443. curr = ioread32be(i2c->base + (rreg << i2c->reg_shift));
  444. if (reg == OCI2C_PRELOW)
  445. wr = (curr & 0xff00) | value;
  446. else
  447. wr = (((u32)value) << 8) | (curr & 0xff);
  448. } else {
  449. wr = value;
  450. }
  451. iowrite32be(wr, i2c->base + (rreg << i2c->reg_shift));
  452. }
  453. static int ocores_i2c_of_probe(struct platform_device *pdev,
  454. struct ocores_i2c *i2c)
  455. {
  456. struct device_node *np = pdev->dev.of_node;
  457. const struct of_device_id *match;
  458. u32 val;
  459. u32 clock_frequency;
  460. bool clock_frequency_present;
  461. if (of_property_read_u32(np, "reg-shift", &i2c->reg_shift)) {
  462. /* no 'reg-shift', check for deprecated 'regstep' */
  463. if (!of_property_read_u32(np, "regstep", &val)) {
  464. if (!is_power_of_2(val)) {
  465. dev_err(&pdev->dev, "invalid regstep %d\n",
  466. val);
  467. return -EINVAL;
  468. }
  469. i2c->reg_shift = ilog2(val);
  470. dev_warn(&pdev->dev,
  471. "regstep property deprecated, use reg-shift\n");
  472. }
  473. }
  474. clock_frequency_present = !of_property_read_u32(np, "clock-frequency",
  475. &clock_frequency);
  476. i2c->bus_clock_khz = 100;
  477. i2c->clk = devm_clk_get(&pdev->dev, NULL);
  478. if (!IS_ERR(i2c->clk)) {
  479. int ret = clk_prepare_enable(i2c->clk);
  480. if (ret) {
  481. dev_err(&pdev->dev,
  482. "clk_prepare_enable failed: %d\n", ret);
  483. return ret;
  484. }
  485. i2c->ip_clock_khz = clk_get_rate(i2c->clk) / 1000;
  486. if (clock_frequency_present)
  487. i2c->bus_clock_khz = clock_frequency / 1000;
  488. }
  489. if (i2c->ip_clock_khz == 0) {
  490. if (of_property_read_u32(np, "opencores,ip-clock-frequency",
  491. &val)) {
  492. if (!clock_frequency_present) {
  493. dev_err(&pdev->dev,
  494. "Missing required parameter 'opencores,ip-clock-frequency'\n");
  495. clk_disable_unprepare(i2c->clk);
  496. return -ENODEV;
  497. }
  498. i2c->ip_clock_khz = clock_frequency / 1000;
  499. dev_warn(&pdev->dev,
  500. "Deprecated usage of the 'clock-frequency' property, please update to 'opencores,ip-clock-frequency'\n");
  501. } else {
  502. i2c->ip_clock_khz = val / 1000;
  503. if (clock_frequency_present)
  504. i2c->bus_clock_khz = clock_frequency / 1000;
  505. }
  506. }
  507. of_property_read_u32(pdev->dev.of_node, "reg-io-width",
  508. &i2c->reg_io_width);
  509. match = of_match_node(ocores_i2c_match, pdev->dev.of_node);
  510. if (match && (long)match->data == TYPE_GRLIB) {
  511. dev_dbg(&pdev->dev, "GRLIB variant of i2c-ocores\n");
  512. i2c->setreg = oc_setreg_grlib;
  513. i2c->getreg = oc_getreg_grlib;
  514. }
  515. return 0;
  516. }
  517. #else
  518. #define ocores_i2c_of_probe(pdev, i2c) -ENODEV
  519. #endif
  520. static int ocores_i2c_probe(struct platform_device *pdev)
  521. {
  522. struct ocores_i2c *i2c;
  523. struct ocores_i2c_platform_data *pdata;
  524. const struct of_device_id *match;
  525. struct resource *res;
  526. int irq;
  527. int ret;
  528. int i;
  529. i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
  530. if (!i2c)
  531. return -ENOMEM;
  532. spin_lock_init(&i2c->process_lock);
  533. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  534. if (res) {
  535. i2c->base = devm_ioremap_resource(&pdev->dev, res);
  536. if (IS_ERR(i2c->base))
  537. return PTR_ERR(i2c->base);
  538. } else {
  539. res = platform_get_resource(pdev, IORESOURCE_IO, 0);
  540. if (!res)
  541. return -EINVAL;
  542. i2c->iobase = res->start;
  543. if (!devm_request_region(&pdev->dev, res->start,
  544. resource_size(res),
  545. pdev->name)) {
  546. dev_err(&pdev->dev, "Can't get I/O resource.\n");
  547. return -EBUSY;
  548. }
  549. i2c->setreg = oc_setreg_io_8;
  550. i2c->getreg = oc_getreg_io_8;
  551. }
  552. pdata = dev_get_platdata(&pdev->dev);
  553. if (pdata) {
  554. i2c->reg_shift = pdata->reg_shift;
  555. i2c->reg_io_width = pdata->reg_io_width;
  556. i2c->ip_clock_khz = pdata->clock_khz;
  557. if (pdata->bus_khz)
  558. i2c->bus_clock_khz = pdata->bus_khz;
  559. else
  560. i2c->bus_clock_khz = 100;
  561. } else {
  562. ret = ocores_i2c_of_probe(pdev, i2c);
  563. if (ret)
  564. return ret;
  565. }
  566. if (i2c->reg_io_width == 0)
  567. i2c->reg_io_width = 1; /* Set to default value */
  568. if (!i2c->setreg || !i2c->getreg) {
  569. bool be = pdata ? pdata->big_endian :
  570. of_device_is_big_endian(pdev->dev.of_node);
  571. switch (i2c->reg_io_width) {
  572. case 1:
  573. i2c->setreg = oc_setreg_8;
  574. i2c->getreg = oc_getreg_8;
  575. break;
  576. case 2:
  577. i2c->setreg = be ? oc_setreg_16be : oc_setreg_16;
  578. i2c->getreg = be ? oc_getreg_16be : oc_getreg_16;
  579. break;
  580. case 4:
  581. i2c->setreg = be ? oc_setreg_32be : oc_setreg_32;
  582. i2c->getreg = be ? oc_getreg_32be : oc_getreg_32;
  583. break;
  584. default:
  585. dev_err(&pdev->dev, "Unsupported I/O width (%d)\n",
  586. i2c->reg_io_width);
  587. ret = -EINVAL;
  588. goto err_clk;
  589. }
  590. }
  591. init_waitqueue_head(&i2c->wait);
  592. irq = platform_get_irq(pdev, 0);
  593. if (irq == -ENXIO) {
  594. ocores_algorithm.master_xfer = ocores_xfer_polling;
  595. /*
  596. * Set in OCORES_FLAG_BROKEN_IRQ to enable workaround for
  597. * FU540-C000 SoC in polling mode.
  598. */
  599. match = of_match_node(ocores_i2c_match, pdev->dev.of_node);
  600. if (match && (long)match->data == TYPE_SIFIVE_REV0)
  601. i2c->flags |= OCORES_FLAG_BROKEN_IRQ;
  602. } else {
  603. if (irq < 0)
  604. return irq;
  605. }
  606. if (ocores_algorithm.master_xfer != ocores_xfer_polling) {
  607. ret = devm_request_any_context_irq(&pdev->dev, irq,
  608. ocores_isr, 0,
  609. pdev->name, i2c);
  610. if (ret) {
  611. dev_err(&pdev->dev, "Cannot claim IRQ\n");
  612. goto err_clk;
  613. }
  614. }
  615. ret = ocores_init(&pdev->dev, i2c);
  616. if (ret)
  617. goto err_clk;
  618. /* hook up driver to tree */
  619. platform_set_drvdata(pdev, i2c);
  620. i2c->adap = ocores_adapter;
  621. i2c_set_adapdata(&i2c->adap, i2c);
  622. i2c->adap.dev.parent = &pdev->dev;
  623. i2c->adap.dev.of_node = pdev->dev.of_node;
  624. /* add i2c adapter to i2c tree */
  625. ret = i2c_add_adapter(&i2c->adap);
  626. if (ret)
  627. goto err_clk;
  628. /* add in known devices to the bus */
  629. if (pdata) {
  630. for (i = 0; i < pdata->num_devices; i++)
  631. i2c_new_client_device(&i2c->adap, pdata->devices + i);
  632. }
  633. return 0;
  634. err_clk:
  635. clk_disable_unprepare(i2c->clk);
  636. return ret;
  637. }
  638. static int ocores_i2c_remove(struct platform_device *pdev)
  639. {
  640. struct ocores_i2c *i2c = platform_get_drvdata(pdev);
  641. u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
  642. /* disable i2c logic */
  643. ctrl &= ~(OCI2C_CTRL_EN | OCI2C_CTRL_IEN);
  644. oc_setreg(i2c, OCI2C_CONTROL, ctrl);
  645. /* remove adapter & data */
  646. i2c_del_adapter(&i2c->adap);
  647. if (!IS_ERR(i2c->clk))
  648. clk_disable_unprepare(i2c->clk);
  649. return 0;
  650. }
  651. #ifdef CONFIG_PM_SLEEP
  652. static int ocores_i2c_suspend(struct device *dev)
  653. {
  654. struct ocores_i2c *i2c = dev_get_drvdata(dev);
  655. u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
  656. /* make sure the device is disabled */
  657. ctrl &= ~(OCI2C_CTRL_EN | OCI2C_CTRL_IEN);
  658. oc_setreg(i2c, OCI2C_CONTROL, ctrl);
  659. if (!IS_ERR(i2c->clk))
  660. clk_disable_unprepare(i2c->clk);
  661. return 0;
  662. }
  663. static int ocores_i2c_resume(struct device *dev)
  664. {
  665. struct ocores_i2c *i2c = dev_get_drvdata(dev);
  666. if (!IS_ERR(i2c->clk)) {
  667. unsigned long rate;
  668. int ret = clk_prepare_enable(i2c->clk);
  669. if (ret) {
  670. dev_err(dev,
  671. "clk_prepare_enable failed: %d\n", ret);
  672. return ret;
  673. }
  674. rate = clk_get_rate(i2c->clk) / 1000;
  675. if (rate)
  676. i2c->ip_clock_khz = rate;
  677. }
  678. return ocores_init(dev, i2c);
  679. }
  680. static SIMPLE_DEV_PM_OPS(ocores_i2c_pm, ocores_i2c_suspend, ocores_i2c_resume);
  681. #define OCORES_I2C_PM (&ocores_i2c_pm)
  682. #else
  683. #define OCORES_I2C_PM NULL
  684. #endif
  685. static struct platform_driver ocores_i2c_driver = {
  686. .probe = ocores_i2c_probe,
  687. .remove = ocores_i2c_remove,
  688. .driver = {
  689. .name = "ocores-i2c",
  690. .of_match_table = ocores_i2c_match,
  691. .pm = OCORES_I2C_PM,
  692. },
  693. };
  694. module_platform_driver(ocores_i2c_driver);
  695. MODULE_AUTHOR("Peter Korsgaard <peter@korsgaard.com>");
  696. MODULE_DESCRIPTION("OpenCores I2C bus driver");
  697. MODULE_LICENSE("GPL");
  698. MODULE_ALIAS("platform:ocores-i2c");