/drivers/i2c/busses/i2c-eg20t.c

http://github.com/mirrors/linux · C · 930 lines · 646 code · 158 blank · 126 comment · 82 complexity · f9352ac4c0ad91072852175e019a1020 MD5 · raw file

  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/kernel.h>
  7. #include <linux/delay.h>
  8. #include <linux/errno.h>
  9. #include <linux/i2c.h>
  10. #include <linux/fs.h>
  11. #include <linux/io.h>
  12. #include <linux/types.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/jiffies.h>
  15. #include <linux/pci.h>
  16. #include <linux/mutex.h>
  17. #include <linux/ktime.h>
  18. #include <linux/slab.h>
  19. #define PCH_EVENT_SET 0 /* I2C Interrupt Event Set Status */
  20. #define PCH_EVENT_NONE 1 /* I2C Interrupt Event Clear Status */
  21. #define PCH_MAX_CLK 100000 /* Maximum Clock speed in MHz */
  22. #define PCH_BUFFER_MODE_ENABLE 0x0002 /* flag for Buffer mode enable */
  23. #define PCH_EEPROM_SW_RST_MODE_ENABLE 0x0008 /* EEPROM SW RST enable flag */
  24. #define PCH_I2CSADR 0x00 /* I2C slave address register */
  25. #define PCH_I2CCTL 0x04 /* I2C control register */
  26. #define PCH_I2CSR 0x08 /* I2C status register */
  27. #define PCH_I2CDR 0x0C /* I2C data register */
  28. #define PCH_I2CMON 0x10 /* I2C bus monitor register */
  29. #define PCH_I2CBC 0x14 /* I2C bus transfer rate setup counter */
  30. #define PCH_I2CMOD 0x18 /* I2C mode register */
  31. #define PCH_I2CBUFSLV 0x1C /* I2C buffer mode slave address register */
  32. #define PCH_I2CBUFSUB 0x20 /* I2C buffer mode subaddress register */
  33. #define PCH_I2CBUFFOR 0x24 /* I2C buffer mode format register */
  34. #define PCH_I2CBUFCTL 0x28 /* I2C buffer mode control register */
  35. #define PCH_I2CBUFMSK 0x2C /* I2C buffer mode interrupt mask register */
  36. #define PCH_I2CBUFSTA 0x30 /* I2C buffer mode status register */
  37. #define PCH_I2CBUFLEV 0x34 /* I2C buffer mode level register */
  38. #define PCH_I2CESRFOR 0x38 /* EEPROM software reset mode format register */
  39. #define PCH_I2CESRCTL 0x3C /* EEPROM software reset mode ctrl register */
  40. #define PCH_I2CESRMSK 0x40 /* EEPROM software reset mode */
  41. #define PCH_I2CESRSTA 0x44 /* EEPROM software reset mode status register */
  42. #define PCH_I2CTMR 0x48 /* I2C timer register */
  43. #define PCH_I2CSRST 0xFC /* I2C reset register */
  44. #define PCH_I2CNF 0xF8 /* I2C noise filter register */
  45. #define BUS_IDLE_TIMEOUT 20
  46. #define PCH_I2CCTL_I2CMEN 0x0080
  47. #define TEN_BIT_ADDR_DEFAULT 0xF000
  48. #define TEN_BIT_ADDR_MASK 0xF0
  49. #define PCH_START 0x0020
  50. #define PCH_RESTART 0x0004
  51. #define PCH_ESR_START 0x0001
  52. #define PCH_BUFF_START 0x1
  53. #define PCH_REPSTART 0x0004
  54. #define PCH_ACK 0x0008
  55. #define PCH_GETACK 0x0001
  56. #define CLR_REG 0x0
  57. #define I2C_RD 0x1
  58. #define I2CMCF_BIT 0x0080
  59. #define I2CMIF_BIT 0x0002
  60. #define I2CMAL_BIT 0x0010
  61. #define I2CBMFI_BIT 0x0001
  62. #define I2CBMAL_BIT 0x0002
  63. #define I2CBMNA_BIT 0x0004
  64. #define I2CBMTO_BIT 0x0008
  65. #define I2CBMIS_BIT 0x0010
  66. #define I2CESRFI_BIT 0X0001
  67. #define I2CESRTO_BIT 0x0002
  68. #define I2CESRFIIE_BIT 0x1
  69. #define I2CESRTOIE_BIT 0x2
  70. #define I2CBMDZ_BIT 0x0040
  71. #define I2CBMAG_BIT 0x0020
  72. #define I2CMBB_BIT 0x0020
  73. #define BUFFER_MODE_MASK (I2CBMFI_BIT | I2CBMAL_BIT | I2CBMNA_BIT | \
  74. I2CBMTO_BIT | I2CBMIS_BIT)
  75. #define I2C_ADDR_MSK 0xFF
  76. #define I2C_MSB_2B_MSK 0x300
  77. #define FAST_MODE_CLK 400
  78. #define FAST_MODE_EN 0x0001
  79. #define SUB_ADDR_LEN_MAX 4
  80. #define BUF_LEN_MAX 32
  81. #define PCH_BUFFER_MODE 0x1
  82. #define EEPROM_SW_RST_MODE 0x0002
  83. #define NORMAL_INTR_ENBL 0x0300
  84. #define EEPROM_RST_INTR_ENBL (I2CESRFIIE_BIT | I2CESRTOIE_BIT)
  85. #define EEPROM_RST_INTR_DISBL 0x0
  86. #define BUFFER_MODE_INTR_ENBL 0x001F
  87. #define BUFFER_MODE_INTR_DISBL 0x0
  88. #define NORMAL_MODE 0x0
  89. #define BUFFER_MODE 0x1
  90. #define EEPROM_SR_MODE 0x2
  91. #define I2C_TX_MODE 0x0010
  92. #define PCH_BUF_TX 0xFFF7
  93. #define PCH_BUF_RD 0x0008
  94. #define I2C_ERROR_MASK (I2CESRTO_EVENT | I2CBMIS_EVENT | I2CBMTO_EVENT | \
  95. I2CBMNA_EVENT | I2CBMAL_EVENT | I2CMAL_EVENT)
  96. #define I2CMAL_EVENT 0x0001
  97. #define I2CMCF_EVENT 0x0002
  98. #define I2CBMFI_EVENT 0x0004
  99. #define I2CBMAL_EVENT 0x0008
  100. #define I2CBMNA_EVENT 0x0010
  101. #define I2CBMTO_EVENT 0x0020
  102. #define I2CBMIS_EVENT 0x0040
  103. #define I2CESRFI_EVENT 0x0080
  104. #define I2CESRTO_EVENT 0x0100
  105. #define PCI_DEVICE_ID_PCH_I2C 0x8817
  106. #define pch_dbg(adap, fmt, arg...) \
  107. dev_dbg(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
  108. #define pch_err(adap, fmt, arg...) \
  109. dev_err(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
  110. #define pch_pci_err(pdev, fmt, arg...) \
  111. dev_err(&pdev->dev, "%s :" fmt, __func__, ##arg)
  112. #define pch_pci_dbg(pdev, fmt, arg...) \
  113. dev_dbg(&pdev->dev, "%s :" fmt, __func__, ##arg)
  114. /*
  115. Set the number of I2C instance max
  116. Intel EG20T PCH : 1ch
  117. LAPIS Semiconductor ML7213 IOH : 2ch
  118. LAPIS Semiconductor ML7831 IOH : 1ch
  119. */
  120. #define PCH_I2C_MAX_DEV 2
  121. /**
  122. * struct i2c_algo_pch_data - for I2C driver functionalities
  123. * @pch_adapter: stores the reference to i2c_adapter structure
  124. * @p_adapter_info: stores the reference to adapter_info structure
  125. * @pch_base_address: specifies the remapped base address
  126. * @pch_buff_mode_en: specifies if buffer mode is enabled
  127. * @pch_event_flag: specifies occurrence of interrupt events
  128. * @pch_i2c_xfer_in_progress: specifies whether the transfer is completed
  129. */
  130. struct i2c_algo_pch_data {
  131. struct i2c_adapter pch_adapter;
  132. struct adapter_info *p_adapter_info;
  133. void __iomem *pch_base_address;
  134. int pch_buff_mode_en;
  135. u32 pch_event_flag;
  136. bool pch_i2c_xfer_in_progress;
  137. };
  138. /**
  139. * struct adapter_info - This structure holds the adapter information for the
  140. PCH i2c controller
  141. * @pch_data: stores a list of i2c_algo_pch_data
  142. * @pch_i2c_suspended: specifies whether the system is suspended or not
  143. * perhaps with more lines and words.
  144. * @ch_num: specifies the number of i2c instance
  145. *
  146. * pch_data has as many elements as maximum I2C channels
  147. */
  148. struct adapter_info {
  149. struct i2c_algo_pch_data pch_data[PCH_I2C_MAX_DEV];
  150. bool pch_i2c_suspended;
  151. int ch_num;
  152. };
  153. static int pch_i2c_speed = 100; /* I2C bus speed in Kbps */
  154. static int pch_clk = 50000; /* specifies I2C clock speed in KHz */
  155. static wait_queue_head_t pch_event;
  156. static DEFINE_MUTEX(pch_mutex);
  157. /* Definition for ML7213 by LAPIS Semiconductor */
  158. #define PCI_DEVICE_ID_ML7213_I2C 0x802D
  159. #define PCI_DEVICE_ID_ML7223_I2C 0x8010
  160. #define PCI_DEVICE_ID_ML7831_I2C 0x8817
  161. static const struct pci_device_id pch_pcidev_id[] = {
  162. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PCH_I2C), 1, },
  163. { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_I2C), 2, },
  164. { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_I2C), 1, },
  165. { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7831_I2C), 1, },
  166. {0,}
  167. };
  168. static irqreturn_t pch_i2c_handler(int irq, void *pData);
  169. static inline void pch_setbit(void __iomem *addr, u32 offset, u32 bitmask)
  170. {
  171. u32 val;
  172. val = ioread32(addr + offset);
  173. val |= bitmask;
  174. iowrite32(val, addr + offset);
  175. }
  176. static inline void pch_clrbit(void __iomem *addr, u32 offset, u32 bitmask)
  177. {
  178. u32 val;
  179. val = ioread32(addr + offset);
  180. val &= (~bitmask);
  181. iowrite32(val, addr + offset);
  182. }
  183. /**
  184. * pch_i2c_init() - hardware initialization of I2C module
  185. * @adap: Pointer to struct i2c_algo_pch_data.
  186. */
  187. static void pch_i2c_init(struct i2c_algo_pch_data *adap)
  188. {
  189. void __iomem *p = adap->pch_base_address;
  190. u32 pch_i2cbc;
  191. u32 pch_i2ctmr;
  192. u32 reg_value;
  193. /* reset I2C controller */
  194. iowrite32(0x01, p + PCH_I2CSRST);
  195. msleep(20);
  196. iowrite32(0x0, p + PCH_I2CSRST);
  197. /* Initialize I2C registers */
  198. iowrite32(0x21, p + PCH_I2CNF);
  199. pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_I2CCTL_I2CMEN);
  200. if (pch_i2c_speed != 400)
  201. pch_i2c_speed = 100;
  202. reg_value = PCH_I2CCTL_I2CMEN;
  203. if (pch_i2c_speed == FAST_MODE_CLK) {
  204. reg_value |= FAST_MODE_EN;
  205. pch_dbg(adap, "Fast mode enabled\n");
  206. }
  207. if (pch_clk > PCH_MAX_CLK)
  208. pch_clk = 62500;
  209. pch_i2cbc = (pch_clk + (pch_i2c_speed * 4)) / (pch_i2c_speed * 8);
  210. /* Set transfer speed in I2CBC */
  211. iowrite32(pch_i2cbc, p + PCH_I2CBC);
  212. pch_i2ctmr = (pch_clk) / 8;
  213. iowrite32(pch_i2ctmr, p + PCH_I2CTMR);
  214. reg_value |= NORMAL_INTR_ENBL; /* Enable interrupts in normal mode */
  215. iowrite32(reg_value, p + PCH_I2CCTL);
  216. pch_dbg(adap,
  217. "I2CCTL=%x pch_i2cbc=%x pch_i2ctmr=%x Enable interrupts\n",
  218. ioread32(p + PCH_I2CCTL), pch_i2cbc, pch_i2ctmr);
  219. init_waitqueue_head(&pch_event);
  220. }
  221. /**
  222. * pch_i2c_wait_for_bus_idle() - check the status of bus.
  223. * @adap: Pointer to struct i2c_algo_pch_data.
  224. * @timeout: waiting time counter (ms).
  225. */
  226. static s32 pch_i2c_wait_for_bus_idle(struct i2c_algo_pch_data *adap,
  227. s32 timeout)
  228. {
  229. void __iomem *p = adap->pch_base_address;
  230. int schedule = 0;
  231. unsigned long end = jiffies + msecs_to_jiffies(timeout);
  232. while (ioread32(p + PCH_I2CSR) & I2CMBB_BIT) {
  233. if (time_after(jiffies, end)) {
  234. pch_dbg(adap, "I2CSR = %x\n", ioread32(p + PCH_I2CSR));
  235. pch_err(adap, "%s: Timeout Error.return%d\n",
  236. __func__, -ETIME);
  237. pch_i2c_init(adap);
  238. return -ETIME;
  239. }
  240. if (!schedule)
  241. /* Retry after some usecs */
  242. udelay(5);
  243. else
  244. /* Wait a bit more without consuming CPU */
  245. usleep_range(20, 1000);
  246. schedule = 1;
  247. }
  248. return 0;
  249. }
  250. /**
  251. * pch_i2c_start() - Generate I2C start condition in normal mode.
  252. * @adap: Pointer to struct i2c_algo_pch_data.
  253. *
  254. * Generate I2C start condition in normal mode by setting I2CCTL.I2CMSTA to 1.
  255. */
  256. static void pch_i2c_start(struct i2c_algo_pch_data *adap)
  257. {
  258. void __iomem *p = adap->pch_base_address;
  259. pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
  260. pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_START);
  261. }
  262. /**
  263. * pch_i2c_stop() - generate stop condition in normal mode.
  264. * @adap: Pointer to struct i2c_algo_pch_data.
  265. */
  266. static void pch_i2c_stop(struct i2c_algo_pch_data *adap)
  267. {
  268. void __iomem *p = adap->pch_base_address;
  269. pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
  270. /* clear the start bit */
  271. pch_clrbit(adap->pch_base_address, PCH_I2CCTL, PCH_START);
  272. }
  273. static int pch_i2c_wait_for_check_xfer(struct i2c_algo_pch_data *adap)
  274. {
  275. long ret;
  276. void __iomem *p = adap->pch_base_address;
  277. ret = wait_event_timeout(pch_event,
  278. (adap->pch_event_flag != 0), msecs_to_jiffies(1000));
  279. if (!ret) {
  280. pch_err(adap, "%s:wait-event timeout\n", __func__);
  281. adap->pch_event_flag = 0;
  282. pch_i2c_stop(adap);
  283. pch_i2c_init(adap);
  284. return -ETIMEDOUT;
  285. }
  286. if (adap->pch_event_flag & I2C_ERROR_MASK) {
  287. pch_err(adap, "Lost Arbitration\n");
  288. adap->pch_event_flag = 0;
  289. pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMAL_BIT);
  290. pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMIF_BIT);
  291. pch_i2c_init(adap);
  292. return -EAGAIN;
  293. }
  294. adap->pch_event_flag = 0;
  295. if (ioread32(p + PCH_I2CSR) & PCH_GETACK) {
  296. pch_dbg(adap, "Receive NACK for slave address setting\n");
  297. return -ENXIO;
  298. }
  299. return 0;
  300. }
  301. /**
  302. * pch_i2c_repstart() - generate repeated start condition in normal mode
  303. * @adap: Pointer to struct i2c_algo_pch_data.
  304. */
  305. static void pch_i2c_repstart(struct i2c_algo_pch_data *adap)
  306. {
  307. void __iomem *p = adap->pch_base_address;
  308. pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
  309. pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_REPSTART);
  310. }
  311. /**
  312. * pch_i2c_writebytes() - write data to I2C bus in normal mode
  313. * @i2c_adap: Pointer to the struct i2c_adapter.
  314. * @last: specifies whether last message or not.
  315. * In the case of compound mode it will be 1 for last message,
  316. * otherwise 0.
  317. * @first: specifies whether first message or not.
  318. * 1 for first message otherwise 0.
  319. */
  320. static s32 pch_i2c_writebytes(struct i2c_adapter *i2c_adap,
  321. struct i2c_msg *msgs, u32 last, u32 first)
  322. {
  323. struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
  324. u8 *buf;
  325. u32 length;
  326. u32 addr;
  327. u32 addr_2_msb;
  328. u32 addr_8_lsb;
  329. s32 wrcount;
  330. s32 rtn;
  331. void __iomem *p = adap->pch_base_address;
  332. length = msgs->len;
  333. buf = msgs->buf;
  334. addr = msgs->addr;
  335. /* enable master tx */
  336. pch_setbit(adap->pch_base_address, PCH_I2CCTL, I2C_TX_MODE);
  337. pch_dbg(adap, "I2CCTL = %x msgs->len = %d\n", ioread32(p + PCH_I2CCTL),
  338. length);
  339. if (first) {
  340. if (pch_i2c_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
  341. return -ETIME;
  342. }
  343. if (msgs->flags & I2C_M_TEN) {
  344. addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7) & 0x06;
  345. iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
  346. if (first)
  347. pch_i2c_start(adap);
  348. rtn = pch_i2c_wait_for_check_xfer(adap);
  349. if (rtn)
  350. return rtn;
  351. addr_8_lsb = (addr & I2C_ADDR_MSK);
  352. iowrite32(addr_8_lsb, p + PCH_I2CDR);
  353. } else {
  354. /* set 7 bit slave address and R/W bit as 0 */
  355. iowrite32(i2c_8bit_addr_from_msg(msgs), p + PCH_I2CDR);
  356. if (first)
  357. pch_i2c_start(adap);
  358. }
  359. rtn = pch_i2c_wait_for_check_xfer(adap);
  360. if (rtn)
  361. return rtn;
  362. for (wrcount = 0; wrcount < length; ++wrcount) {
  363. /* write buffer value to I2C data register */
  364. iowrite32(buf[wrcount], p + PCH_I2CDR);
  365. pch_dbg(adap, "writing %x to Data register\n", buf[wrcount]);
  366. rtn = pch_i2c_wait_for_check_xfer(adap);
  367. if (rtn)
  368. return rtn;
  369. pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMCF_BIT);
  370. pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMIF_BIT);
  371. }
  372. /* check if this is the last message */
  373. if (last)
  374. pch_i2c_stop(adap);
  375. else
  376. pch_i2c_repstart(adap);
  377. pch_dbg(adap, "return=%d\n", wrcount);
  378. return wrcount;
  379. }
  380. /**
  381. * pch_i2c_sendack() - send ACK
  382. * @adap: Pointer to struct i2c_algo_pch_data.
  383. */
  384. static void pch_i2c_sendack(struct i2c_algo_pch_data *adap)
  385. {
  386. void __iomem *p = adap->pch_base_address;
  387. pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
  388. pch_clrbit(adap->pch_base_address, PCH_I2CCTL, PCH_ACK);
  389. }
  390. /**
  391. * pch_i2c_sendnack() - send NACK
  392. * @adap: Pointer to struct i2c_algo_pch_data.
  393. */
  394. static void pch_i2c_sendnack(struct i2c_algo_pch_data *adap)
  395. {
  396. void __iomem *p = adap->pch_base_address;
  397. pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
  398. pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_ACK);
  399. }
  400. /**
  401. * pch_i2c_restart() - Generate I2C restart condition in normal mode.
  402. * @adap: Pointer to struct i2c_algo_pch_data.
  403. *
  404. * Generate I2C restart condition in normal mode by setting I2CCTL.I2CRSTA.
  405. */
  406. static void pch_i2c_restart(struct i2c_algo_pch_data *adap)
  407. {
  408. void __iomem *p = adap->pch_base_address;
  409. pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
  410. pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_RESTART);
  411. }
  412. /**
  413. * pch_i2c_readbytes() - read data from I2C bus in normal mode.
  414. * @i2c_adap: Pointer to the struct i2c_adapter.
  415. * @msgs: Pointer to i2c_msg structure.
  416. * @last: specifies whether last message or not.
  417. * @first: specifies whether first message or not.
  418. */
  419. static s32 pch_i2c_readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
  420. u32 last, u32 first)
  421. {
  422. struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
  423. u8 *buf;
  424. u32 count;
  425. u32 length;
  426. u32 addr;
  427. u32 addr_2_msb;
  428. u32 addr_8_lsb;
  429. void __iomem *p = adap->pch_base_address;
  430. s32 rtn;
  431. length = msgs->len;
  432. buf = msgs->buf;
  433. addr = msgs->addr;
  434. /* enable master reception */
  435. pch_clrbit(adap->pch_base_address, PCH_I2CCTL, I2C_TX_MODE);
  436. if (first) {
  437. if (pch_i2c_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
  438. return -ETIME;
  439. }
  440. if (msgs->flags & I2C_M_TEN) {
  441. addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7);
  442. iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
  443. if (first)
  444. pch_i2c_start(adap);
  445. rtn = pch_i2c_wait_for_check_xfer(adap);
  446. if (rtn)
  447. return rtn;
  448. addr_8_lsb = (addr & I2C_ADDR_MSK);
  449. iowrite32(addr_8_lsb, p + PCH_I2CDR);
  450. pch_i2c_restart(adap);
  451. rtn = pch_i2c_wait_for_check_xfer(adap);
  452. if (rtn)
  453. return rtn;
  454. addr_2_msb |= I2C_RD;
  455. iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
  456. } else {
  457. /* 7 address bits + R/W bit */
  458. iowrite32(i2c_8bit_addr_from_msg(msgs), p + PCH_I2CDR);
  459. }
  460. /* check if it is the first message */
  461. if (first)
  462. pch_i2c_start(adap);
  463. rtn = pch_i2c_wait_for_check_xfer(adap);
  464. if (rtn)
  465. return rtn;
  466. if (length == 0) {
  467. pch_i2c_stop(adap);
  468. ioread32(p + PCH_I2CDR); /* Dummy read needs */
  469. count = length;
  470. } else {
  471. int read_index;
  472. int loop;
  473. pch_i2c_sendack(adap);
  474. /* Dummy read */
  475. for (loop = 1, read_index = 0; loop < length; loop++) {
  476. buf[read_index] = ioread32(p + PCH_I2CDR);
  477. if (loop != 1)
  478. read_index++;
  479. rtn = pch_i2c_wait_for_check_xfer(adap);
  480. if (rtn)
  481. return rtn;
  482. } /* end for */
  483. pch_i2c_sendnack(adap);
  484. buf[read_index] = ioread32(p + PCH_I2CDR); /* Read final - 1 */
  485. if (length != 1)
  486. read_index++;
  487. rtn = pch_i2c_wait_for_check_xfer(adap);
  488. if (rtn)
  489. return rtn;
  490. if (last)
  491. pch_i2c_stop(adap);
  492. else
  493. pch_i2c_repstart(adap);
  494. buf[read_index++] = ioread32(p + PCH_I2CDR); /* Read Final */
  495. count = read_index;
  496. }
  497. return count;
  498. }
  499. /**
  500. * pch_i2c_cb() - Interrupt handler Call back function
  501. * @adap: Pointer to struct i2c_algo_pch_data.
  502. */
  503. static void pch_i2c_cb(struct i2c_algo_pch_data *adap)
  504. {
  505. u32 sts;
  506. void __iomem *p = adap->pch_base_address;
  507. sts = ioread32(p + PCH_I2CSR);
  508. sts &= (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT);
  509. if (sts & I2CMAL_BIT)
  510. adap->pch_event_flag |= I2CMAL_EVENT;
  511. if (sts & I2CMCF_BIT)
  512. adap->pch_event_flag |= I2CMCF_EVENT;
  513. /* clear the applicable bits */
  514. pch_clrbit(adap->pch_base_address, PCH_I2CSR, sts);
  515. pch_dbg(adap, "PCH_I2CSR = %x\n", ioread32(p + PCH_I2CSR));
  516. wake_up(&pch_event);
  517. }
  518. /**
  519. * pch_i2c_handler() - interrupt handler for the PCH I2C controller
  520. * @irq: irq number.
  521. * @pData: cookie passed back to the handler function.
  522. */
  523. static irqreturn_t pch_i2c_handler(int irq, void *pData)
  524. {
  525. u32 reg_val;
  526. int flag;
  527. int i;
  528. struct adapter_info *adap_info = pData;
  529. void __iomem *p;
  530. u32 mode;
  531. for (i = 0, flag = 0; i < adap_info->ch_num; i++) {
  532. p = adap_info->pch_data[i].pch_base_address;
  533. mode = ioread32(p + PCH_I2CMOD);
  534. mode &= BUFFER_MODE | EEPROM_SR_MODE;
  535. if (mode != NORMAL_MODE) {
  536. pch_err(adap_info->pch_data,
  537. "I2C-%d mode(%d) is not supported\n", mode, i);
  538. continue;
  539. }
  540. reg_val = ioread32(p + PCH_I2CSR);
  541. if (reg_val & (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT)) {
  542. pch_i2c_cb(&adap_info->pch_data[i]);
  543. flag = 1;
  544. }
  545. }
  546. return flag ? IRQ_HANDLED : IRQ_NONE;
  547. }
  548. /**
  549. * pch_i2c_xfer() - Reading adnd writing data through I2C bus
  550. * @i2c_adap: Pointer to the struct i2c_adapter.
  551. * @msgs: Pointer to i2c_msg structure.
  552. * @num: number of messages.
  553. */
  554. static s32 pch_i2c_xfer(struct i2c_adapter *i2c_adap,
  555. struct i2c_msg *msgs, s32 num)
  556. {
  557. struct i2c_msg *pmsg;
  558. u32 i = 0;
  559. u32 status;
  560. s32 ret;
  561. struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
  562. ret = mutex_lock_interruptible(&pch_mutex);
  563. if (ret)
  564. return ret;
  565. if (adap->p_adapter_info->pch_i2c_suspended) {
  566. mutex_unlock(&pch_mutex);
  567. return -EBUSY;
  568. }
  569. pch_dbg(adap, "adap->p_adapter_info->pch_i2c_suspended is %d\n",
  570. adap->p_adapter_info->pch_i2c_suspended);
  571. /* transfer not completed */
  572. adap->pch_i2c_xfer_in_progress = true;
  573. for (i = 0; i < num && ret >= 0; i++) {
  574. pmsg = &msgs[i];
  575. pmsg->flags |= adap->pch_buff_mode_en;
  576. status = pmsg->flags;
  577. pch_dbg(adap,
  578. "After invoking I2C_MODE_SEL :flag= 0x%x\n", status);
  579. if ((status & (I2C_M_RD)) != false) {
  580. ret = pch_i2c_readbytes(i2c_adap, pmsg, (i + 1 == num),
  581. (i == 0));
  582. } else {
  583. ret = pch_i2c_writebytes(i2c_adap, pmsg, (i + 1 == num),
  584. (i == 0));
  585. }
  586. }
  587. adap->pch_i2c_xfer_in_progress = false; /* transfer completed */
  588. mutex_unlock(&pch_mutex);
  589. return (ret < 0) ? ret : num;
  590. }
  591. /**
  592. * pch_i2c_func() - return the functionality of the I2C driver
  593. * @adap: Pointer to struct i2c_algo_pch_data.
  594. */
  595. static u32 pch_i2c_func(struct i2c_adapter *adap)
  596. {
  597. return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
  598. }
  599. static const struct i2c_algorithm pch_algorithm = {
  600. .master_xfer = pch_i2c_xfer,
  601. .functionality = pch_i2c_func
  602. };
  603. /**
  604. * pch_i2c_disbl_int() - Disable PCH I2C interrupts
  605. * @adap: Pointer to struct i2c_algo_pch_data.
  606. */
  607. static void pch_i2c_disbl_int(struct i2c_algo_pch_data *adap)
  608. {
  609. void __iomem *p = adap->pch_base_address;
  610. pch_clrbit(adap->pch_base_address, PCH_I2CCTL, NORMAL_INTR_ENBL);
  611. iowrite32(EEPROM_RST_INTR_DISBL, p + PCH_I2CESRMSK);
  612. iowrite32(BUFFER_MODE_INTR_DISBL, p + PCH_I2CBUFMSK);
  613. }
  614. static int pch_i2c_probe(struct pci_dev *pdev,
  615. const struct pci_device_id *id)
  616. {
  617. void __iomem *base_addr;
  618. int ret;
  619. int i, j;
  620. struct adapter_info *adap_info;
  621. struct i2c_adapter *pch_adap;
  622. pch_pci_dbg(pdev, "Entered.\n");
  623. adap_info = kzalloc((sizeof(struct adapter_info)), GFP_KERNEL);
  624. if (adap_info == NULL)
  625. return -ENOMEM;
  626. ret = pci_enable_device(pdev);
  627. if (ret) {
  628. pch_pci_err(pdev, "pci_enable_device FAILED\n");
  629. goto err_pci_enable;
  630. }
  631. ret = pci_request_regions(pdev, KBUILD_MODNAME);
  632. if (ret) {
  633. pch_pci_err(pdev, "pci_request_regions FAILED\n");
  634. goto err_pci_req;
  635. }
  636. base_addr = pci_iomap(pdev, 1, 0);
  637. if (base_addr == NULL) {
  638. pch_pci_err(pdev, "pci_iomap FAILED\n");
  639. ret = -ENOMEM;
  640. goto err_pci_iomap;
  641. }
  642. /* Set the number of I2C channel instance */
  643. adap_info->ch_num = id->driver_data;
  644. for (i = 0; i < adap_info->ch_num; i++) {
  645. pch_adap = &adap_info->pch_data[i].pch_adapter;
  646. adap_info->pch_i2c_suspended = false;
  647. adap_info->pch_data[i].p_adapter_info = adap_info;
  648. pch_adap->owner = THIS_MODULE;
  649. pch_adap->class = I2C_CLASS_HWMON;
  650. strlcpy(pch_adap->name, KBUILD_MODNAME, sizeof(pch_adap->name));
  651. pch_adap->algo = &pch_algorithm;
  652. pch_adap->algo_data = &adap_info->pch_data[i];
  653. /* base_addr + offset; */
  654. adap_info->pch_data[i].pch_base_address = base_addr + 0x100 * i;
  655. pch_adap->dev.of_node = pdev->dev.of_node;
  656. pch_adap->dev.parent = &pdev->dev;
  657. }
  658. ret = request_irq(pdev->irq, pch_i2c_handler, IRQF_SHARED,
  659. KBUILD_MODNAME, adap_info);
  660. if (ret) {
  661. pch_pci_err(pdev, "request_irq FAILED\n");
  662. goto err_request_irq;
  663. }
  664. for (i = 0; i < adap_info->ch_num; i++) {
  665. pch_adap = &adap_info->pch_data[i].pch_adapter;
  666. pch_i2c_init(&adap_info->pch_data[i]);
  667. pch_adap->nr = i;
  668. ret = i2c_add_numbered_adapter(pch_adap);
  669. if (ret) {
  670. pch_pci_err(pdev, "i2c_add_adapter[ch:%d] FAILED\n", i);
  671. goto err_add_adapter;
  672. }
  673. }
  674. pci_set_drvdata(pdev, adap_info);
  675. pch_pci_dbg(pdev, "returns %d.\n", ret);
  676. return 0;
  677. err_add_adapter:
  678. for (j = 0; j < i; j++)
  679. i2c_del_adapter(&adap_info->pch_data[j].pch_adapter);
  680. free_irq(pdev->irq, adap_info);
  681. err_request_irq:
  682. pci_iounmap(pdev, base_addr);
  683. err_pci_iomap:
  684. pci_release_regions(pdev);
  685. err_pci_req:
  686. pci_disable_device(pdev);
  687. err_pci_enable:
  688. kfree(adap_info);
  689. return ret;
  690. }
  691. static void pch_i2c_remove(struct pci_dev *pdev)
  692. {
  693. int i;
  694. struct adapter_info *adap_info = pci_get_drvdata(pdev);
  695. free_irq(pdev->irq, adap_info);
  696. for (i = 0; i < adap_info->ch_num; i++) {
  697. pch_i2c_disbl_int(&adap_info->pch_data[i]);
  698. i2c_del_adapter(&adap_info->pch_data[i].pch_adapter);
  699. }
  700. if (adap_info->pch_data[0].pch_base_address)
  701. pci_iounmap(pdev, adap_info->pch_data[0].pch_base_address);
  702. for (i = 0; i < adap_info->ch_num; i++)
  703. adap_info->pch_data[i].pch_base_address = NULL;
  704. pci_release_regions(pdev);
  705. pci_disable_device(pdev);
  706. kfree(adap_info);
  707. }
  708. #ifdef CONFIG_PM
  709. static int pch_i2c_suspend(struct pci_dev *pdev, pm_message_t state)
  710. {
  711. int ret;
  712. int i;
  713. struct adapter_info *adap_info = pci_get_drvdata(pdev);
  714. void __iomem *p = adap_info->pch_data[0].pch_base_address;
  715. adap_info->pch_i2c_suspended = true;
  716. for (i = 0; i < adap_info->ch_num; i++) {
  717. while ((adap_info->pch_data[i].pch_i2c_xfer_in_progress)) {
  718. /* Wait until all channel transfers are completed */
  719. msleep(20);
  720. }
  721. }
  722. /* Disable the i2c interrupts */
  723. for (i = 0; i < adap_info->ch_num; i++)
  724. pch_i2c_disbl_int(&adap_info->pch_data[i]);
  725. pch_pci_dbg(pdev, "I2CSR = %x I2CBUFSTA = %x I2CESRSTA = %x "
  726. "invoked function pch_i2c_disbl_int successfully\n",
  727. ioread32(p + PCH_I2CSR), ioread32(p + PCH_I2CBUFSTA),
  728. ioread32(p + PCH_I2CESRSTA));
  729. ret = pci_save_state(pdev);
  730. if (ret) {
  731. pch_pci_err(pdev, "pci_save_state\n");
  732. return ret;
  733. }
  734. pci_enable_wake(pdev, PCI_D3hot, 0);
  735. pci_disable_device(pdev);
  736. pci_set_power_state(pdev, pci_choose_state(pdev, state));
  737. return 0;
  738. }
  739. static int pch_i2c_resume(struct pci_dev *pdev)
  740. {
  741. int i;
  742. struct adapter_info *adap_info = pci_get_drvdata(pdev);
  743. pci_set_power_state(pdev, PCI_D0);
  744. pci_restore_state(pdev);
  745. if (pci_enable_device(pdev) < 0) {
  746. pch_pci_err(pdev, "pch_i2c_resume:pci_enable_device FAILED\n");
  747. return -EIO;
  748. }
  749. pci_enable_wake(pdev, PCI_D3hot, 0);
  750. for (i = 0; i < adap_info->ch_num; i++)
  751. pch_i2c_init(&adap_info->pch_data[i]);
  752. adap_info->pch_i2c_suspended = false;
  753. return 0;
  754. }
  755. #else
  756. #define pch_i2c_suspend NULL
  757. #define pch_i2c_resume NULL
  758. #endif
  759. static struct pci_driver pch_pcidriver = {
  760. .name = KBUILD_MODNAME,
  761. .id_table = pch_pcidev_id,
  762. .probe = pch_i2c_probe,
  763. .remove = pch_i2c_remove,
  764. .suspend = pch_i2c_suspend,
  765. .resume = pch_i2c_resume
  766. };
  767. module_pci_driver(pch_pcidriver);
  768. MODULE_DESCRIPTION("Intel EG20T PCH/LAPIS Semico ML7213/ML7223/ML7831 IOH I2C");
  769. MODULE_LICENSE("GPL");
  770. MODULE_AUTHOR("Tomoya MORINAGA. <tomoya.rohm@gmail.com>");
  771. module_param(pch_i2c_speed, int, (S_IRUSR | S_IWUSR));
  772. module_param(pch_clk, int, (S_IRUSR | S_IWUSR));