/drivers/i2c/busses/i2c-imx.c

http://github.com/mirrors/linux · C · 1337 lines · 982 code · 195 blank · 160 comment · 131 complexity · 7cb9942644d22ebb4f9e7f399099b630 MD5 · raw file

  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2002 Motorola GSG-China
  4. *
  5. * Author:
  6. * Darius Augulis, Teltonika Inc.
  7. *
  8. * Desc.:
  9. * Implementation of I2C Adapter/Algorithm Driver
  10. * for I2C Bus integrated in Freescale i.MX/MXC processors
  11. *
  12. * Derived from Motorola GSG China I2C example driver
  13. *
  14. * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de
  15. * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de
  16. * Copyright (C) 2007 RightHand Technologies, Inc.
  17. * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
  18. *
  19. * Copyright 2013 Freescale Semiconductor, Inc.
  20. *
  21. */
  22. #include <linux/acpi.h>
  23. #include <linux/clk.h>
  24. #include <linux/completion.h>
  25. #include <linux/delay.h>
  26. #include <linux/dma-mapping.h>
  27. #include <linux/dmaengine.h>
  28. #include <linux/dmapool.h>
  29. #include <linux/err.h>
  30. #include <linux/errno.h>
  31. #include <linux/gpio/consumer.h>
  32. #include <linux/i2c.h>
  33. #include <linux/init.h>
  34. #include <linux/interrupt.h>
  35. #include <linux/io.h>
  36. #include <linux/iopoll.h>
  37. #include <linux/kernel.h>
  38. #include <linux/module.h>
  39. #include <linux/of.h>
  40. #include <linux/of_device.h>
  41. #include <linux/of_dma.h>
  42. #include <linux/pinctrl/consumer.h>
  43. #include <linux/platform_data/i2c-imx.h>
  44. #include <linux/platform_device.h>
  45. #include <linux/pm_runtime.h>
  46. #include <linux/sched.h>
  47. #include <linux/slab.h>
  48. /* This will be the driver name the kernel reports */
  49. #define DRIVER_NAME "imx-i2c"
  50. /*
  51. * Enable DMA if transfer byte size is bigger than this threshold.
  52. * As the hardware request, it must bigger than 4 bytes.\
  53. * I have set '16' here, maybe it's not the best but I think it's
  54. * the appropriate.
  55. */
  56. #define DMA_THRESHOLD 16
  57. #define DMA_TIMEOUT 1000
  58. /* IMX I2C registers:
  59. * the I2C register offset is different between SoCs,
  60. * to provid support for all these chips, split the
  61. * register offset into a fixed base address and a
  62. * variable shift value, then the full register offset
  63. * will be calculated by
  64. * reg_off = ( reg_base_addr << reg_shift)
  65. */
  66. #define IMX_I2C_IADR 0x00 /* i2c slave address */
  67. #define IMX_I2C_IFDR 0x01 /* i2c frequency divider */
  68. #define IMX_I2C_I2CR 0x02 /* i2c control */
  69. #define IMX_I2C_I2SR 0x03 /* i2c status */
  70. #define IMX_I2C_I2DR 0x04 /* i2c transfer data */
  71. #define IMX_I2C_REGSHIFT 2
  72. #define VF610_I2C_REGSHIFT 0
  73. /* Bits of IMX I2C registers */
  74. #define I2SR_RXAK 0x01
  75. #define I2SR_IIF 0x02
  76. #define I2SR_SRW 0x04
  77. #define I2SR_IAL 0x10
  78. #define I2SR_IBB 0x20
  79. #define I2SR_IAAS 0x40
  80. #define I2SR_ICF 0x80
  81. #define I2CR_DMAEN 0x02
  82. #define I2CR_RSTA 0x04
  83. #define I2CR_TXAK 0x08
  84. #define I2CR_MTX 0x10
  85. #define I2CR_MSTA 0x20
  86. #define I2CR_IIEN 0x40
  87. #define I2CR_IEN 0x80
  88. /* register bits different operating codes definition:
  89. * 1) I2SR: Interrupt flags clear operation differ between SoCs:
  90. * - write zero to clear(w0c) INT flag on i.MX,
  91. * - but write one to clear(w1c) INT flag on Vybrid.
  92. * 2) I2CR: I2C module enable operation also differ between SoCs:
  93. * - set I2CR_IEN bit enable the module on i.MX,
  94. * - but clear I2CR_IEN bit enable the module on Vybrid.
  95. */
  96. #define I2SR_CLR_OPCODE_W0C 0x0
  97. #define I2SR_CLR_OPCODE_W1C (I2SR_IAL | I2SR_IIF)
  98. #define I2CR_IEN_OPCODE_0 0x0
  99. #define I2CR_IEN_OPCODE_1 I2CR_IEN
  100. #define I2C_PM_TIMEOUT 10 /* ms */
  101. /*
  102. * sorted list of clock divider, register value pairs
  103. * taken from table 26-5, p.26-9, Freescale i.MX
  104. * Integrated Portable System Processor Reference Manual
  105. * Document Number: MC9328MXLRM, Rev. 5.1, 06/2007
  106. *
  107. * Duplicated divider values removed from list
  108. */
  109. struct imx_i2c_clk_pair {
  110. u16 div;
  111. u16 val;
  112. };
  113. static struct imx_i2c_clk_pair imx_i2c_clk_div[] = {
  114. { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
  115. { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
  116. { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
  117. { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
  118. { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
  119. { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
  120. { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
  121. { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
  122. { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
  123. { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
  124. { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
  125. { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
  126. { 3072, 0x1E }, { 3840, 0x1F }
  127. };
  128. /* Vybrid VF610 clock divider, register value pairs */
  129. static struct imx_i2c_clk_pair vf610_i2c_clk_div[] = {
  130. { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 },
  131. { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 },
  132. { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D },
  133. { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 },
  134. { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 },
  135. { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 },
  136. { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 },
  137. { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 },
  138. { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 },
  139. { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
  140. { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 },
  141. { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
  142. { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
  143. { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
  144. { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
  145. };
  146. enum imx_i2c_type {
  147. IMX1_I2C,
  148. IMX21_I2C,
  149. VF610_I2C,
  150. };
  151. struct imx_i2c_hwdata {
  152. enum imx_i2c_type devtype;
  153. unsigned regshift;
  154. struct imx_i2c_clk_pair *clk_div;
  155. unsigned ndivs;
  156. unsigned i2sr_clr_opcode;
  157. unsigned i2cr_ien_opcode;
  158. };
  159. struct imx_i2c_dma {
  160. struct dma_chan *chan_tx;
  161. struct dma_chan *chan_rx;
  162. struct dma_chan *chan_using;
  163. struct completion cmd_complete;
  164. dma_addr_t dma_buf;
  165. unsigned int dma_len;
  166. enum dma_transfer_direction dma_transfer_dir;
  167. enum dma_data_direction dma_data_dir;
  168. };
  169. struct imx_i2c_struct {
  170. struct i2c_adapter adapter;
  171. struct clk *clk;
  172. struct notifier_block clk_change_nb;
  173. void __iomem *base;
  174. wait_queue_head_t queue;
  175. unsigned long i2csr;
  176. unsigned int disable_delay;
  177. int stopped;
  178. unsigned int ifdr; /* IMX_I2C_IFDR */
  179. unsigned int cur_clk;
  180. unsigned int bitrate;
  181. const struct imx_i2c_hwdata *hwdata;
  182. struct i2c_bus_recovery_info rinfo;
  183. struct pinctrl *pinctrl;
  184. struct pinctrl_state *pinctrl_pins_default;
  185. struct pinctrl_state *pinctrl_pins_gpio;
  186. struct imx_i2c_dma *dma;
  187. };
  188. static const struct imx_i2c_hwdata imx1_i2c_hwdata = {
  189. .devtype = IMX1_I2C,
  190. .regshift = IMX_I2C_REGSHIFT,
  191. .clk_div = imx_i2c_clk_div,
  192. .ndivs = ARRAY_SIZE(imx_i2c_clk_div),
  193. .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C,
  194. .i2cr_ien_opcode = I2CR_IEN_OPCODE_1,
  195. };
  196. static const struct imx_i2c_hwdata imx21_i2c_hwdata = {
  197. .devtype = IMX21_I2C,
  198. .regshift = IMX_I2C_REGSHIFT,
  199. .clk_div = imx_i2c_clk_div,
  200. .ndivs = ARRAY_SIZE(imx_i2c_clk_div),
  201. .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C,
  202. .i2cr_ien_opcode = I2CR_IEN_OPCODE_1,
  203. };
  204. static struct imx_i2c_hwdata vf610_i2c_hwdata = {
  205. .devtype = VF610_I2C,
  206. .regshift = VF610_I2C_REGSHIFT,
  207. .clk_div = vf610_i2c_clk_div,
  208. .ndivs = ARRAY_SIZE(vf610_i2c_clk_div),
  209. .i2sr_clr_opcode = I2SR_CLR_OPCODE_W1C,
  210. .i2cr_ien_opcode = I2CR_IEN_OPCODE_0,
  211. };
  212. static const struct platform_device_id imx_i2c_devtype[] = {
  213. {
  214. .name = "imx1-i2c",
  215. .driver_data = (kernel_ulong_t)&imx1_i2c_hwdata,
  216. }, {
  217. .name = "imx21-i2c",
  218. .driver_data = (kernel_ulong_t)&imx21_i2c_hwdata,
  219. }, {
  220. /* sentinel */
  221. }
  222. };
  223. MODULE_DEVICE_TABLE(platform, imx_i2c_devtype);
  224. static const struct of_device_id i2c_imx_dt_ids[] = {
  225. { .compatible = "fsl,imx1-i2c", .data = &imx1_i2c_hwdata, },
  226. { .compatible = "fsl,imx21-i2c", .data = &imx21_i2c_hwdata, },
  227. { .compatible = "fsl,vf610-i2c", .data = &vf610_i2c_hwdata, },
  228. { /* sentinel */ }
  229. };
  230. MODULE_DEVICE_TABLE(of, i2c_imx_dt_ids);
  231. static const struct acpi_device_id i2c_imx_acpi_ids[] = {
  232. {"NXP0001", .driver_data = (kernel_ulong_t)&vf610_i2c_hwdata},
  233. { }
  234. };
  235. MODULE_DEVICE_TABLE(acpi, i2c_imx_acpi_ids);
  236. static inline int is_imx1_i2c(struct imx_i2c_struct *i2c_imx)
  237. {
  238. return i2c_imx->hwdata->devtype == IMX1_I2C;
  239. }
  240. static inline void imx_i2c_write_reg(unsigned int val,
  241. struct imx_i2c_struct *i2c_imx, unsigned int reg)
  242. {
  243. writeb(val, i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
  244. }
  245. static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct *i2c_imx,
  246. unsigned int reg)
  247. {
  248. return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
  249. }
  250. /* Functions for DMA support */
  251. static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx,
  252. dma_addr_t phy_addr)
  253. {
  254. struct imx_i2c_dma *dma;
  255. struct dma_slave_config dma_sconfig;
  256. struct device *dev = &i2c_imx->adapter.dev;
  257. int ret;
  258. dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
  259. if (!dma)
  260. return;
  261. dma->chan_tx = dma_request_chan(dev, "tx");
  262. if (IS_ERR(dma->chan_tx)) {
  263. ret = PTR_ERR(dma->chan_tx);
  264. if (ret != -ENODEV && ret != -EPROBE_DEFER)
  265. dev_err(dev, "can't request DMA tx channel (%d)\n", ret);
  266. goto fail_al;
  267. }
  268. dma_sconfig.dst_addr = phy_addr +
  269. (IMX_I2C_I2DR << i2c_imx->hwdata->regshift);
  270. dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
  271. dma_sconfig.dst_maxburst = 1;
  272. dma_sconfig.direction = DMA_MEM_TO_DEV;
  273. ret = dmaengine_slave_config(dma->chan_tx, &dma_sconfig);
  274. if (ret < 0) {
  275. dev_err(dev, "can't configure tx channel (%d)\n", ret);
  276. goto fail_tx;
  277. }
  278. dma->chan_rx = dma_request_chan(dev, "rx");
  279. if (IS_ERR(dma->chan_rx)) {
  280. ret = PTR_ERR(dma->chan_rx);
  281. if (ret != -ENODEV && ret != -EPROBE_DEFER)
  282. dev_err(dev, "can't request DMA rx channel (%d)\n", ret);
  283. goto fail_tx;
  284. }
  285. dma_sconfig.src_addr = phy_addr +
  286. (IMX_I2C_I2DR << i2c_imx->hwdata->regshift);
  287. dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
  288. dma_sconfig.src_maxburst = 1;
  289. dma_sconfig.direction = DMA_DEV_TO_MEM;
  290. ret = dmaengine_slave_config(dma->chan_rx, &dma_sconfig);
  291. if (ret < 0) {
  292. dev_err(dev, "can't configure rx channel (%d)\n", ret);
  293. goto fail_rx;
  294. }
  295. i2c_imx->dma = dma;
  296. init_completion(&dma->cmd_complete);
  297. dev_info(dev, "using %s (tx) and %s (rx) for DMA transfers\n",
  298. dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx));
  299. return;
  300. fail_rx:
  301. dma_release_channel(dma->chan_rx);
  302. fail_tx:
  303. dma_release_channel(dma->chan_tx);
  304. fail_al:
  305. devm_kfree(dev, dma);
  306. }
  307. static void i2c_imx_dma_callback(void *arg)
  308. {
  309. struct imx_i2c_struct *i2c_imx = (struct imx_i2c_struct *)arg;
  310. struct imx_i2c_dma *dma = i2c_imx->dma;
  311. dma_unmap_single(dma->chan_using->device->dev, dma->dma_buf,
  312. dma->dma_len, dma->dma_data_dir);
  313. complete(&dma->cmd_complete);
  314. }
  315. static int i2c_imx_dma_xfer(struct imx_i2c_struct *i2c_imx,
  316. struct i2c_msg *msgs)
  317. {
  318. struct imx_i2c_dma *dma = i2c_imx->dma;
  319. struct dma_async_tx_descriptor *txdesc;
  320. struct device *dev = &i2c_imx->adapter.dev;
  321. struct device *chan_dev = dma->chan_using->device->dev;
  322. dma->dma_buf = dma_map_single(chan_dev, msgs->buf,
  323. dma->dma_len, dma->dma_data_dir);
  324. if (dma_mapping_error(chan_dev, dma->dma_buf)) {
  325. dev_err(dev, "DMA mapping failed\n");
  326. goto err_map;
  327. }
  328. txdesc = dmaengine_prep_slave_single(dma->chan_using, dma->dma_buf,
  329. dma->dma_len, dma->dma_transfer_dir,
  330. DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  331. if (!txdesc) {
  332. dev_err(dev, "Not able to get desc for DMA xfer\n");
  333. goto err_desc;
  334. }
  335. reinit_completion(&dma->cmd_complete);
  336. txdesc->callback = i2c_imx_dma_callback;
  337. txdesc->callback_param = i2c_imx;
  338. if (dma_submit_error(dmaengine_submit(txdesc))) {
  339. dev_err(dev, "DMA submit failed\n");
  340. goto err_submit;
  341. }
  342. dma_async_issue_pending(dma->chan_using);
  343. return 0;
  344. err_submit:
  345. dmaengine_terminate_all(dma->chan_using);
  346. err_desc:
  347. dma_unmap_single(chan_dev, dma->dma_buf,
  348. dma->dma_len, dma->dma_data_dir);
  349. err_map:
  350. return -EINVAL;
  351. }
  352. static void i2c_imx_dma_free(struct imx_i2c_struct *i2c_imx)
  353. {
  354. struct imx_i2c_dma *dma = i2c_imx->dma;
  355. dma->dma_buf = 0;
  356. dma->dma_len = 0;
  357. dma_release_channel(dma->chan_tx);
  358. dma->chan_tx = NULL;
  359. dma_release_channel(dma->chan_rx);
  360. dma->chan_rx = NULL;
  361. dma->chan_using = NULL;
  362. }
  363. static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy, bool atomic)
  364. {
  365. unsigned long orig_jiffies = jiffies;
  366. unsigned int temp;
  367. dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
  368. while (1) {
  369. temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
  370. /* check for arbitration lost */
  371. if (temp & I2SR_IAL) {
  372. temp &= ~I2SR_IAL;
  373. imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR);
  374. return -EAGAIN;
  375. }
  376. if (for_busy && (temp & I2SR_IBB)) {
  377. i2c_imx->stopped = 0;
  378. break;
  379. }
  380. if (!for_busy && !(temp & I2SR_IBB)) {
  381. i2c_imx->stopped = 1;
  382. break;
  383. }
  384. if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {
  385. dev_dbg(&i2c_imx->adapter.dev,
  386. "<%s> I2C bus is busy\n", __func__);
  387. return -ETIMEDOUT;
  388. }
  389. if (atomic)
  390. udelay(100);
  391. else
  392. schedule();
  393. }
  394. return 0;
  395. }
  396. static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx, bool atomic)
  397. {
  398. if (atomic) {
  399. void __iomem *addr = i2c_imx->base + (IMX_I2C_I2SR << i2c_imx->hwdata->regshift);
  400. unsigned int regval;
  401. /*
  402. * The formula for the poll timeout is documented in the RM
  403. * Rev.5 on page 1878:
  404. * T_min = 10/F_scl
  405. * Set the value hard as it is done for the non-atomic use-case.
  406. * Use 10 kHz for the calculation since this is the minimum
  407. * allowed SMBus frequency. Also add an offset of 100us since it
  408. * turned out that the I2SR_IIF bit isn't set correctly within
  409. * the minimum timeout in polling mode.
  410. */
  411. readb_poll_timeout_atomic(addr, regval, regval & I2SR_IIF, 5, 1000 + 100);
  412. i2c_imx->i2csr = regval;
  413. imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2SR);
  414. } else {
  415. wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10);
  416. }
  417. if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) {
  418. dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__);
  419. return -ETIMEDOUT;
  420. }
  421. dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__);
  422. i2c_imx->i2csr = 0;
  423. return 0;
  424. }
  425. static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx)
  426. {
  427. if (imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR) & I2SR_RXAK) {
  428. dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__);
  429. return -ENXIO; /* No ACK */
  430. }
  431. dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__);
  432. return 0;
  433. }
  434. static void i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx,
  435. unsigned int i2c_clk_rate)
  436. {
  437. struct imx_i2c_clk_pair *i2c_clk_div = i2c_imx->hwdata->clk_div;
  438. unsigned int div;
  439. int i;
  440. /* Divider value calculation */
  441. if (i2c_imx->cur_clk == i2c_clk_rate)
  442. return;
  443. i2c_imx->cur_clk = i2c_clk_rate;
  444. div = (i2c_clk_rate + i2c_imx->bitrate - 1) / i2c_imx->bitrate;
  445. if (div < i2c_clk_div[0].div)
  446. i = 0;
  447. else if (div > i2c_clk_div[i2c_imx->hwdata->ndivs - 1].div)
  448. i = i2c_imx->hwdata->ndivs - 1;
  449. else
  450. for (i = 0; i2c_clk_div[i].div < div; i++)
  451. ;
  452. /* Store divider value */
  453. i2c_imx->ifdr = i2c_clk_div[i].val;
  454. /*
  455. * There dummy delay is calculated.
  456. * It should be about one I2C clock period long.
  457. * This delay is used in I2C bus disable function
  458. * to fix chip hardware bug.
  459. */
  460. i2c_imx->disable_delay = (500000U * i2c_clk_div[i].div
  461. + (i2c_clk_rate / 2) - 1) / (i2c_clk_rate / 2);
  462. #ifdef CONFIG_I2C_DEBUG_BUS
  463. dev_dbg(&i2c_imx->adapter.dev, "I2C_CLK=%d, REQ DIV=%d\n",
  464. i2c_clk_rate, div);
  465. dev_dbg(&i2c_imx->adapter.dev, "IFDR[IC]=0x%x, REAL DIV=%d\n",
  466. i2c_clk_div[i].val, i2c_clk_div[i].div);
  467. #endif
  468. }
  469. static int i2c_imx_clk_notifier_call(struct notifier_block *nb,
  470. unsigned long action, void *data)
  471. {
  472. struct clk_notifier_data *ndata = data;
  473. struct imx_i2c_struct *i2c_imx = container_of(nb,
  474. struct imx_i2c_struct,
  475. clk_change_nb);
  476. if (action & POST_RATE_CHANGE)
  477. i2c_imx_set_clk(i2c_imx, ndata->new_rate);
  478. return NOTIFY_OK;
  479. }
  480. static int i2c_imx_start(struct imx_i2c_struct *i2c_imx, bool atomic)
  481. {
  482. unsigned int temp = 0;
  483. int result;
  484. dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
  485. imx_i2c_write_reg(i2c_imx->ifdr, i2c_imx, IMX_I2C_IFDR);
  486. /* Enable I2C controller */
  487. imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR);
  488. imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode, i2c_imx, IMX_I2C_I2CR);
  489. /* Wait controller to be stable */
  490. if (atomic)
  491. udelay(50);
  492. else
  493. usleep_range(50, 150);
  494. /* Start I2C transaction */
  495. temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
  496. temp |= I2CR_MSTA;
  497. imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
  498. result = i2c_imx_bus_busy(i2c_imx, 1, atomic);
  499. if (result)
  500. return result;
  501. temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK;
  502. if (atomic)
  503. temp &= ~I2CR_IIEN; /* Disable interrupt */
  504. temp &= ~I2CR_DMAEN;
  505. imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
  506. return result;
  507. }
  508. static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx, bool atomic)
  509. {
  510. unsigned int temp = 0;
  511. if (!i2c_imx->stopped) {
  512. /* Stop I2C transaction */
  513. dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
  514. temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
  515. temp &= ~(I2CR_MSTA | I2CR_MTX);
  516. if (i2c_imx->dma)
  517. temp &= ~I2CR_DMAEN;
  518. imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
  519. }
  520. if (is_imx1_i2c(i2c_imx)) {
  521. /*
  522. * This delay caused by an i.MXL hardware bug.
  523. * If no (or too short) delay, no "STOP" bit will be generated.
  524. */
  525. udelay(i2c_imx->disable_delay);
  526. }
  527. if (!i2c_imx->stopped)
  528. i2c_imx_bus_busy(i2c_imx, 0, atomic);
  529. /* Disable I2C controller */
  530. temp = i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
  531. imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
  532. }
  533. static irqreturn_t i2c_imx_isr(int irq, void *dev_id)
  534. {
  535. struct imx_i2c_struct *i2c_imx = dev_id;
  536. unsigned int temp;
  537. temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
  538. if (temp & I2SR_IIF) {
  539. /* save status register */
  540. i2c_imx->i2csr = temp;
  541. temp &= ~I2SR_IIF;
  542. temp |= (i2c_imx->hwdata->i2sr_clr_opcode & I2SR_IIF);
  543. imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR);
  544. wake_up(&i2c_imx->queue);
  545. return IRQ_HANDLED;
  546. }
  547. return IRQ_NONE;
  548. }
  549. static int i2c_imx_dma_write(struct imx_i2c_struct *i2c_imx,
  550. struct i2c_msg *msgs)
  551. {
  552. int result;
  553. unsigned long time_left;
  554. unsigned int temp = 0;
  555. unsigned long orig_jiffies = jiffies;
  556. struct imx_i2c_dma *dma = i2c_imx->dma;
  557. struct device *dev = &i2c_imx->adapter.dev;
  558. dma->chan_using = dma->chan_tx;
  559. dma->dma_transfer_dir = DMA_MEM_TO_DEV;
  560. dma->dma_data_dir = DMA_TO_DEVICE;
  561. dma->dma_len = msgs->len - 1;
  562. result = i2c_imx_dma_xfer(i2c_imx, msgs);
  563. if (result)
  564. return result;
  565. temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
  566. temp |= I2CR_DMAEN;
  567. imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
  568. /*
  569. * Write slave address.
  570. * The first byte must be transmitted by the CPU.
  571. */
  572. imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR);
  573. time_left = wait_for_completion_timeout(
  574. &i2c_imx->dma->cmd_complete,
  575. msecs_to_jiffies(DMA_TIMEOUT));
  576. if (time_left == 0) {
  577. dmaengine_terminate_all(dma->chan_using);
  578. return -ETIMEDOUT;
  579. }
  580. /* Waiting for transfer complete. */
  581. while (1) {
  582. temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
  583. if (temp & I2SR_ICF)
  584. break;
  585. if (time_after(jiffies, orig_jiffies +
  586. msecs_to_jiffies(DMA_TIMEOUT))) {
  587. dev_dbg(dev, "<%s> Timeout\n", __func__);
  588. return -ETIMEDOUT;
  589. }
  590. schedule();
  591. }
  592. temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
  593. temp &= ~I2CR_DMAEN;
  594. imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
  595. /* The last data byte must be transferred by the CPU. */
  596. imx_i2c_write_reg(msgs->buf[msgs->len-1],
  597. i2c_imx, IMX_I2C_I2DR);
  598. result = i2c_imx_trx_complete(i2c_imx, false);
  599. if (result)
  600. return result;
  601. return i2c_imx_acked(i2c_imx);
  602. }
  603. static int i2c_imx_dma_read(struct imx_i2c_struct *i2c_imx,
  604. struct i2c_msg *msgs, bool is_lastmsg)
  605. {
  606. int result;
  607. unsigned long time_left;
  608. unsigned int temp;
  609. unsigned long orig_jiffies = jiffies;
  610. struct imx_i2c_dma *dma = i2c_imx->dma;
  611. struct device *dev = &i2c_imx->adapter.dev;
  612. dma->chan_using = dma->chan_rx;
  613. dma->dma_transfer_dir = DMA_DEV_TO_MEM;
  614. dma->dma_data_dir = DMA_FROM_DEVICE;
  615. /* The last two data bytes must be transferred by the CPU. */
  616. dma->dma_len = msgs->len - 2;
  617. result = i2c_imx_dma_xfer(i2c_imx, msgs);
  618. if (result)
  619. return result;
  620. time_left = wait_for_completion_timeout(
  621. &i2c_imx->dma->cmd_complete,
  622. msecs_to_jiffies(DMA_TIMEOUT));
  623. if (time_left == 0) {
  624. dmaengine_terminate_all(dma->chan_using);
  625. return -ETIMEDOUT;
  626. }
  627. /* waiting for transfer complete. */
  628. while (1) {
  629. temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
  630. if (temp & I2SR_ICF)
  631. break;
  632. if (time_after(jiffies, orig_jiffies +
  633. msecs_to_jiffies(DMA_TIMEOUT))) {
  634. dev_dbg(dev, "<%s> Timeout\n", __func__);
  635. return -ETIMEDOUT;
  636. }
  637. schedule();
  638. }
  639. temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
  640. temp &= ~I2CR_DMAEN;
  641. imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
  642. /* read n-1 byte data */
  643. temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
  644. temp |= I2CR_TXAK;
  645. imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
  646. msgs->buf[msgs->len-2] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
  647. /* read n byte data */
  648. result = i2c_imx_trx_complete(i2c_imx, false);
  649. if (result)
  650. return result;
  651. if (is_lastmsg) {
  652. /*
  653. * It must generate STOP before read I2DR to prevent
  654. * controller from generating another clock cycle
  655. */
  656. dev_dbg(dev, "<%s> clear MSTA\n", __func__);
  657. temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
  658. temp &= ~(I2CR_MSTA | I2CR_MTX);
  659. imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
  660. i2c_imx_bus_busy(i2c_imx, 0, false);
  661. } else {
  662. /*
  663. * For i2c master receiver repeat restart operation like:
  664. * read -> repeat MSTA -> read/write
  665. * The controller must set MTX before read the last byte in
  666. * the first read operation, otherwise the first read cost
  667. * one extra clock cycle.
  668. */
  669. temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
  670. temp |= I2CR_MTX;
  671. imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
  672. }
  673. msgs->buf[msgs->len-1] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
  674. return 0;
  675. }
  676. static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs,
  677. bool atomic)
  678. {
  679. int i, result;
  680. dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n",
  681. __func__, i2c_8bit_addr_from_msg(msgs));
  682. /* write slave address */
  683. imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR);
  684. result = i2c_imx_trx_complete(i2c_imx, atomic);
  685. if (result)
  686. return result;
  687. result = i2c_imx_acked(i2c_imx);
  688. if (result)
  689. return result;
  690. dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__);
  691. /* write data */
  692. for (i = 0; i < msgs->len; i++) {
  693. dev_dbg(&i2c_imx->adapter.dev,
  694. "<%s> write byte: B%d=0x%X\n",
  695. __func__, i, msgs->buf[i]);
  696. imx_i2c_write_reg(msgs->buf[i], i2c_imx, IMX_I2C_I2DR);
  697. result = i2c_imx_trx_complete(i2c_imx, atomic);
  698. if (result)
  699. return result;
  700. result = i2c_imx_acked(i2c_imx);
  701. if (result)
  702. return result;
  703. }
  704. return 0;
  705. }
  706. static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs,
  707. bool is_lastmsg, bool atomic)
  708. {
  709. int i, result;
  710. unsigned int temp;
  711. int block_data = msgs->flags & I2C_M_RECV_LEN;
  712. int use_dma = i2c_imx->dma && msgs->len >= DMA_THRESHOLD && !block_data;
  713. dev_dbg(&i2c_imx->adapter.dev,
  714. "<%s> write slave address: addr=0x%x\n",
  715. __func__, i2c_8bit_addr_from_msg(msgs));
  716. /* write slave address */
  717. imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR);
  718. result = i2c_imx_trx_complete(i2c_imx, atomic);
  719. if (result)
  720. return result;
  721. result = i2c_imx_acked(i2c_imx);
  722. if (result)
  723. return result;
  724. dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__);
  725. /* setup bus to read data */
  726. temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
  727. temp &= ~I2CR_MTX;
  728. /*
  729. * Reset the I2CR_TXAK flag initially for SMBus block read since the
  730. * length is unknown
  731. */
  732. if ((msgs->len - 1) || block_data)
  733. temp &= ~I2CR_TXAK;
  734. if (use_dma)
  735. temp |= I2CR_DMAEN;
  736. imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
  737. imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); /* dummy read */
  738. dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__);
  739. if (use_dma)
  740. return i2c_imx_dma_read(i2c_imx, msgs, is_lastmsg);
  741. /* read data */
  742. for (i = 0; i < msgs->len; i++) {
  743. u8 len = 0;
  744. result = i2c_imx_trx_complete(i2c_imx, atomic);
  745. if (result)
  746. return result;
  747. /*
  748. * First byte is the length of remaining packet
  749. * in the SMBus block data read. Add it to
  750. * msgs->len.
  751. */
  752. if ((!i) && block_data) {
  753. len = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
  754. if ((len == 0) || (len > I2C_SMBUS_BLOCK_MAX))
  755. return -EPROTO;
  756. dev_dbg(&i2c_imx->adapter.dev,
  757. "<%s> read length: 0x%X\n",
  758. __func__, len);
  759. msgs->len += len;
  760. }
  761. if (i == (msgs->len - 1)) {
  762. if (is_lastmsg) {
  763. /*
  764. * It must generate STOP before read I2DR to prevent
  765. * controller from generating another clock cycle
  766. */
  767. dev_dbg(&i2c_imx->adapter.dev,
  768. "<%s> clear MSTA\n", __func__);
  769. temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
  770. temp &= ~(I2CR_MSTA | I2CR_MTX);
  771. imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
  772. i2c_imx_bus_busy(i2c_imx, 0, atomic);
  773. } else {
  774. /*
  775. * For i2c master receiver repeat restart operation like:
  776. * read -> repeat MSTA -> read/write
  777. * The controller must set MTX before read the last byte in
  778. * the first read operation, otherwise the first read cost
  779. * one extra clock cycle.
  780. */
  781. temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
  782. temp |= I2CR_MTX;
  783. imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
  784. }
  785. } else if (i == (msgs->len - 2)) {
  786. dev_dbg(&i2c_imx->adapter.dev,
  787. "<%s> set TXAK\n", __func__);
  788. temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
  789. temp |= I2CR_TXAK;
  790. imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
  791. }
  792. if ((!i) && block_data)
  793. msgs->buf[0] = len;
  794. else
  795. msgs->buf[i] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
  796. dev_dbg(&i2c_imx->adapter.dev,
  797. "<%s> read byte: B%d=0x%X\n",
  798. __func__, i, msgs->buf[i]);
  799. }
  800. return 0;
  801. }
  802. static int i2c_imx_xfer_common(struct i2c_adapter *adapter,
  803. struct i2c_msg *msgs, int num, bool atomic)
  804. {
  805. unsigned int i, temp;
  806. int result;
  807. bool is_lastmsg = false;
  808. struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);
  809. dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
  810. /* Start I2C transfer */
  811. result = i2c_imx_start(i2c_imx, atomic);
  812. if (result) {
  813. /*
  814. * Bus recovery uses gpiod_get_value_cansleep() which is not
  815. * allowed within atomic context.
  816. */
  817. if (!atomic && i2c_imx->adapter.bus_recovery_info) {
  818. i2c_recover_bus(&i2c_imx->adapter);
  819. result = i2c_imx_start(i2c_imx, atomic);
  820. }
  821. }
  822. if (result)
  823. goto fail0;
  824. /* read/write data */
  825. for (i = 0; i < num; i++) {
  826. if (i == num - 1)
  827. is_lastmsg = true;
  828. if (i) {
  829. dev_dbg(&i2c_imx->adapter.dev,
  830. "<%s> repeated start\n", __func__);
  831. temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
  832. temp |= I2CR_RSTA;
  833. imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
  834. result = i2c_imx_bus_busy(i2c_imx, 1, atomic);
  835. if (result)
  836. goto fail0;
  837. }
  838. dev_dbg(&i2c_imx->adapter.dev,
  839. "<%s> transfer message: %d\n", __func__, i);
  840. /* write/read data */
  841. #ifdef CONFIG_I2C_DEBUG_BUS
  842. temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
  843. dev_dbg(&i2c_imx->adapter.dev,
  844. "<%s> CONTROL: IEN=%d, IIEN=%d, MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n",
  845. __func__,
  846. (temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0),
  847. (temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0),
  848. (temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0));
  849. temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
  850. dev_dbg(&i2c_imx->adapter.dev,
  851. "<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n",
  852. __func__,
  853. (temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0),
  854. (temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0),
  855. (temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0),
  856. (temp & I2SR_RXAK ? 1 : 0));
  857. #endif
  858. if (msgs[i].flags & I2C_M_RD) {
  859. result = i2c_imx_read(i2c_imx, &msgs[i], is_lastmsg, atomic);
  860. } else {
  861. if (!atomic &&
  862. i2c_imx->dma && msgs[i].len >= DMA_THRESHOLD)
  863. result = i2c_imx_dma_write(i2c_imx, &msgs[i]);
  864. else
  865. result = i2c_imx_write(i2c_imx, &msgs[i], atomic);
  866. }
  867. if (result)
  868. goto fail0;
  869. }
  870. fail0:
  871. /* Stop I2C transfer */
  872. i2c_imx_stop(i2c_imx, atomic);
  873. dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__,
  874. (result < 0) ? "error" : "success msg",
  875. (result < 0) ? result : num);
  876. return (result < 0) ? result : num;
  877. }
  878. static int i2c_imx_xfer(struct i2c_adapter *adapter,
  879. struct i2c_msg *msgs, int num)
  880. {
  881. struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);
  882. int result;
  883. result = pm_runtime_get_sync(i2c_imx->adapter.dev.parent);
  884. if (result < 0)
  885. return result;
  886. result = i2c_imx_xfer_common(adapter, msgs, num, false);
  887. pm_runtime_mark_last_busy(i2c_imx->adapter.dev.parent);
  888. pm_runtime_put_autosuspend(i2c_imx->adapter.dev.parent);
  889. return result;
  890. }
  891. static int i2c_imx_xfer_atomic(struct i2c_adapter *adapter,
  892. struct i2c_msg *msgs, int num)
  893. {
  894. struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);
  895. int result;
  896. result = clk_enable(i2c_imx->clk);
  897. if (result)
  898. return result;
  899. result = i2c_imx_xfer_common(adapter, msgs, num, true);
  900. clk_disable(i2c_imx->clk);
  901. return result;
  902. }
  903. static void i2c_imx_prepare_recovery(struct i2c_adapter *adap)
  904. {
  905. struct imx_i2c_struct *i2c_imx;
  906. i2c_imx = container_of(adap, struct imx_i2c_struct, adapter);
  907. pinctrl_select_state(i2c_imx->pinctrl, i2c_imx->pinctrl_pins_gpio);
  908. }
  909. static void i2c_imx_unprepare_recovery(struct i2c_adapter *adap)
  910. {
  911. struct imx_i2c_struct *i2c_imx;
  912. i2c_imx = container_of(adap, struct imx_i2c_struct, adapter);
  913. pinctrl_select_state(i2c_imx->pinctrl, i2c_imx->pinctrl_pins_default);
  914. }
  915. /*
  916. * We switch SCL and SDA to their GPIO function and do some bitbanging
  917. * for bus recovery. These alternative pinmux settings can be
  918. * described in the device tree by a separate pinctrl state "gpio". If
  919. * this is missing this is not a big problem, the only implication is
  920. * that we can't do bus recovery.
  921. */
  922. static int i2c_imx_init_recovery_info(struct imx_i2c_struct *i2c_imx,
  923. struct platform_device *pdev)
  924. {
  925. struct i2c_bus_recovery_info *rinfo = &i2c_imx->rinfo;
  926. i2c_imx->pinctrl = devm_pinctrl_get(&pdev->dev);
  927. if (!i2c_imx->pinctrl || IS_ERR(i2c_imx->pinctrl)) {
  928. dev_info(&pdev->dev, "can't get pinctrl, bus recovery not supported\n");
  929. return PTR_ERR(i2c_imx->pinctrl);
  930. }
  931. i2c_imx->pinctrl_pins_default = pinctrl_lookup_state(i2c_imx->pinctrl,
  932. PINCTRL_STATE_DEFAULT);
  933. i2c_imx->pinctrl_pins_gpio = pinctrl_lookup_state(i2c_imx->pinctrl,
  934. "gpio");
  935. rinfo->sda_gpiod = devm_gpiod_get(&pdev->dev, "sda", GPIOD_IN);
  936. rinfo->scl_gpiod = devm_gpiod_get(&pdev->dev, "scl", GPIOD_OUT_HIGH_OPEN_DRAIN);
  937. if (PTR_ERR(rinfo->sda_gpiod) == -EPROBE_DEFER ||
  938. PTR_ERR(rinfo->scl_gpiod) == -EPROBE_DEFER) {
  939. return -EPROBE_DEFER;
  940. } else if (IS_ERR(rinfo->sda_gpiod) ||
  941. IS_ERR(rinfo->scl_gpiod) ||
  942. IS_ERR(i2c_imx->pinctrl_pins_default) ||
  943. IS_ERR(i2c_imx->pinctrl_pins_gpio)) {
  944. dev_dbg(&pdev->dev, "recovery information incomplete\n");
  945. return 0;
  946. }
  947. dev_dbg(&pdev->dev, "using scl%s for recovery\n",
  948. rinfo->sda_gpiod ? ",sda" : "");
  949. rinfo->prepare_recovery = i2c_imx_prepare_recovery;
  950. rinfo->unprepare_recovery = i2c_imx_unprepare_recovery;
  951. rinfo->recover_bus = i2c_generic_scl_recovery;
  952. i2c_imx->adapter.bus_recovery_info = rinfo;
  953. return 0;
  954. }
  955. static u32 i2c_imx_func(struct i2c_adapter *adapter)
  956. {
  957. return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL
  958. | I2C_FUNC_SMBUS_READ_BLOCK_DATA;
  959. }
  960. static const struct i2c_algorithm i2c_imx_algo = {
  961. .master_xfer = i2c_imx_xfer,
  962. .master_xfer_atomic = i2c_imx_xfer_atomic,
  963. .functionality = i2c_imx_func,
  964. };
  965. static int i2c_imx_probe(struct platform_device *pdev)
  966. {
  967. struct imx_i2c_struct *i2c_imx;
  968. struct resource *res;
  969. struct imxi2c_platform_data *pdata = dev_get_platdata(&pdev->dev);
  970. void __iomem *base;
  971. int irq, ret;
  972. dma_addr_t phy_addr;
  973. const struct imx_i2c_hwdata *match;
  974. dev_dbg(&pdev->dev, "<%s>\n", __func__);
  975. irq = platform_get_irq(pdev, 0);
  976. if (irq < 0)
  977. return irq;
  978. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  979. base = devm_ioremap_resource(&pdev->dev, res);
  980. if (IS_ERR(base))
  981. return PTR_ERR(base);
  982. phy_addr = (dma_addr_t)res->start;
  983. i2c_imx = devm_kzalloc(&pdev->dev, sizeof(*i2c_imx), GFP_KERNEL);
  984. if (!i2c_imx)
  985. return -ENOMEM;
  986. match = device_get_match_data(&pdev->dev);
  987. if (match)
  988. i2c_imx->hwdata = match;
  989. else
  990. i2c_imx->hwdata = (struct imx_i2c_hwdata *)
  991. platform_get_device_id(pdev)->driver_data;
  992. /* Setup i2c_imx driver structure */
  993. strlcpy(i2c_imx->adapter.name, pdev->name, sizeof(i2c_imx->adapter.name));
  994. i2c_imx->adapter.owner = THIS_MODULE;
  995. i2c_imx->adapter.algo = &i2c_imx_algo;
  996. i2c_imx->adapter.dev.parent = &pdev->dev;
  997. i2c_imx->adapter.nr = pdev->id;
  998. i2c_imx->adapter.dev.of_node = pdev->dev.of_node;
  999. i2c_imx->base = base;
  1000. ACPI_COMPANION_SET(&i2c_imx->adapter.dev, ACPI_COMPANION(&pdev->dev));
  1001. /* Get I2C clock */
  1002. i2c_imx->clk = devm_clk_get(&pdev->dev, NULL);
  1003. if (IS_ERR(i2c_imx->clk)) {
  1004. if (PTR_ERR(i2c_imx->clk) != -EPROBE_DEFER)
  1005. dev_err(&pdev->dev, "can't get I2C clock\n");
  1006. return PTR_ERR(i2c_imx->clk);
  1007. }
  1008. ret = clk_prepare_enable(i2c_imx->clk);
  1009. if (ret) {
  1010. dev_err(&pdev->dev, "can't enable I2C clock, ret=%d\n", ret);
  1011. return ret;
  1012. }
  1013. /* Request IRQ */
  1014. ret = devm_request_irq(&pdev->dev, irq, i2c_imx_isr, IRQF_SHARED,
  1015. pdev->name, i2c_imx);
  1016. if (ret) {
  1017. dev_err(&pdev->dev, "can't claim irq %d\n", irq);
  1018. goto clk_disable;
  1019. }
  1020. /* Init queue */
  1021. init_waitqueue_head(&i2c_imx->queue);
  1022. /* Set up adapter data */
  1023. i2c_set_adapdata(&i2c_imx->adapter, i2c_imx);
  1024. /* Set up platform driver data */
  1025. platform_set_drvdata(pdev, i2c_imx);
  1026. pm_runtime_set_autosuspend_delay(&pdev->dev, I2C_PM_TIMEOUT);
  1027. pm_runtime_use_autosuspend(&pdev->dev);
  1028. pm_runtime_set_active(&pdev->dev);
  1029. pm_runtime_enable(&pdev->dev);
  1030. ret = pm_runtime_get_sync(&pdev->dev);
  1031. if (ret < 0)
  1032. goto rpm_disable;
  1033. /* Set up clock divider */
  1034. i2c_imx->bitrate = I2C_MAX_STANDARD_MODE_FREQ;
  1035. ret = of_property_read_u32(pdev->dev.of_node,
  1036. "clock-frequency", &i2c_imx->bitrate);
  1037. if (ret < 0 && pdata && pdata->bitrate)
  1038. i2c_imx->bitrate = pdata->bitrate;
  1039. i2c_imx->clk_change_nb.notifier_call = i2c_imx_clk_notifier_call;
  1040. clk_notifier_register(i2c_imx->clk, &i2c_imx->clk_change_nb);
  1041. i2c_imx_set_clk(i2c_imx, clk_get_rate(i2c_imx->clk));
  1042. /* Set up chip registers to defaults */
  1043. imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
  1044. i2c_imx, IMX_I2C_I2CR);
  1045. imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR);
  1046. /* Init optional bus recovery function */
  1047. ret = i2c_imx_init_recovery_info(i2c_imx, pdev);
  1048. /* Give it another chance if pinctrl used is not ready yet */
  1049. if (ret == -EPROBE_DEFER)
  1050. goto clk_notifier_unregister;
  1051. /* Add I2C adapter */
  1052. ret = i2c_add_numbered_adapter(&i2c_imx->adapter);
  1053. if (ret < 0)
  1054. goto clk_notifier_unregister;
  1055. pm_runtime_mark_last_busy(&pdev->dev);
  1056. pm_runtime_put_autosuspend(&pdev->dev);
  1057. dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", irq);
  1058. dev_dbg(&i2c_imx->adapter.dev, "device resources: %pR\n", res);
  1059. dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n",
  1060. i2c_imx->adapter.name);
  1061. dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n");
  1062. /* Init DMA config if supported */
  1063. i2c_imx_dma_request(i2c_imx, phy_addr);
  1064. return 0; /* Return OK */
  1065. clk_notifier_unregister:
  1066. clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb);
  1067. rpm_disable:
  1068. pm_runtime_put_noidle(&pdev->dev);
  1069. pm_runtime_disable(&pdev->dev);
  1070. pm_runtime_set_suspended(&pdev->dev);
  1071. pm_runtime_dont_use_autosuspend(&pdev->dev);
  1072. clk_disable:
  1073. clk_disable_unprepare(i2c_imx->clk);
  1074. return ret;
  1075. }
  1076. static int i2c_imx_remove(struct platform_device *pdev)
  1077. {
  1078. struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev);
  1079. int ret;
  1080. ret = pm_runtime_get_sync(&pdev->dev);
  1081. if (ret < 0)
  1082. return ret;
  1083. /* remove adapter */
  1084. dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n");
  1085. i2c_del_adapter(&i2c_imx->adapter);
  1086. if (i2c_imx->dma)
  1087. i2c_imx_dma_free(i2c_imx);
  1088. /* setup chip registers to defaults */
  1089. imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR);
  1090. imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IFDR);
  1091. imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2CR);
  1092. imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2SR);
  1093. clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb);
  1094. clk_disable_unprepare(i2c_imx->clk);
  1095. pm_runtime_put_noidle(&pdev->dev);
  1096. pm_runtime_disable(&pdev->dev);
  1097. return 0;
  1098. }
  1099. static int __maybe_unused i2c_imx_runtime_suspend(struct device *dev)
  1100. {
  1101. struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev);
  1102. clk_disable(i2c_imx->clk);
  1103. return 0;
  1104. }
  1105. static int __maybe_unused i2c_imx_runtime_resume(struct device *dev)
  1106. {
  1107. struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev);
  1108. int ret;
  1109. ret = clk_enable(i2c_imx->clk);
  1110. if (ret)
  1111. dev_err(dev, "can't enable I2C clock, ret=%d\n", ret);
  1112. return ret;
  1113. }
  1114. static const struct dev_pm_ops i2c_imx_pm_ops = {
  1115. SET_RUNTIME_PM_OPS(i2c_imx_runtime_suspend,
  1116. i2c_imx_runtime_resume, NULL)
  1117. };
  1118. static struct platform_driver i2c_imx_driver = {
  1119. .probe = i2c_imx_probe,
  1120. .remove = i2c_imx_remove,
  1121. .driver = {
  1122. .name = DRIVER_NAME,
  1123. .pm = &i2c_imx_pm_ops,
  1124. .of_match_table = i2c_imx_dt_ids,
  1125. .acpi_match_table = i2c_imx_acpi_ids,
  1126. },
  1127. .id_table = imx_i2c_devtype,
  1128. };
  1129. static int __init i2c_adap_imx_init(void)
  1130. {
  1131. return platform_driver_register(&i2c_imx_driver);
  1132. }
  1133. subsys_initcall(i2c_adap_imx_init);
  1134. static void __exit i2c_adap_imx_exit(void)
  1135. {
  1136. platform_driver_unregister(&i2c_imx_driver);
  1137. }
  1138. module_exit(i2c_adap_imx_exit);
  1139. MODULE_LICENSE("GPL");
  1140. MODULE_AUTHOR("Darius Augulis");
  1141. MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus");
  1142. MODULE_ALIAS("platform:" DRIVER_NAME);