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/drivers/i2c/busses/i2c-imx.c

http://github.com/mirrors/linux
C | 1337 lines | 982 code | 195 blank | 160 comment | 131 complexity | 7cb9942644d22ebb4f9e7f399099b630 MD5 | raw file
   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 *	Copyright (C) 2002 Motorola GSG-China
   4 *
   5 * Author:
   6 *	Darius Augulis, Teltonika Inc.
   7 *
   8 * Desc.:
   9 *	Implementation of I2C Adapter/Algorithm Driver
  10 *	for I2C Bus integrated in Freescale i.MX/MXC processors
  11 *
  12 *	Derived from Motorola GSG China I2C example driver
  13 *
  14 *	Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de
  15 *	Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de
  16 *	Copyright (C) 2007 RightHand Technologies, Inc.
  17 *	Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
  18 *
  19 *	Copyright 2013 Freescale Semiconductor, Inc.
  20 *
  21 */
  22
  23#include <linux/acpi.h>
  24#include <linux/clk.h>
  25#include <linux/completion.h>
  26#include <linux/delay.h>
  27#include <linux/dma-mapping.h>
  28#include <linux/dmaengine.h>
  29#include <linux/dmapool.h>
  30#include <linux/err.h>
  31#include <linux/errno.h>
  32#include <linux/gpio/consumer.h>
  33#include <linux/i2c.h>
  34#include <linux/init.h>
  35#include <linux/interrupt.h>
  36#include <linux/io.h>
  37#include <linux/iopoll.h>
  38#include <linux/kernel.h>
  39#include <linux/module.h>
  40#include <linux/of.h>
  41#include <linux/of_device.h>
  42#include <linux/of_dma.h>
  43#include <linux/pinctrl/consumer.h>
  44#include <linux/platform_data/i2c-imx.h>
  45#include <linux/platform_device.h>
  46#include <linux/pm_runtime.h>
  47#include <linux/sched.h>
  48#include <linux/slab.h>
  49
  50/* This will be the driver name the kernel reports */
  51#define DRIVER_NAME "imx-i2c"
  52
  53/*
  54 * Enable DMA if transfer byte size is bigger than this threshold.
  55 * As the hardware request, it must bigger than 4 bytes.\
  56 * I have set '16' here, maybe it's not the best but I think it's
  57 * the appropriate.
  58 */
  59#define DMA_THRESHOLD	16
  60#define DMA_TIMEOUT	1000
  61
  62/* IMX I2C registers:
  63 * the I2C register offset is different between SoCs,
  64 * to provid support for all these chips, split the
  65 * register offset into a fixed base address and a
  66 * variable shift value, then the full register offset
  67 * will be calculated by
  68 * reg_off = ( reg_base_addr << reg_shift)
  69 */
  70#define IMX_I2C_IADR	0x00	/* i2c slave address */
  71#define IMX_I2C_IFDR	0x01	/* i2c frequency divider */
  72#define IMX_I2C_I2CR	0x02	/* i2c control */
  73#define IMX_I2C_I2SR	0x03	/* i2c status */
  74#define IMX_I2C_I2DR	0x04	/* i2c transfer data */
  75
  76#define IMX_I2C_REGSHIFT	2
  77#define VF610_I2C_REGSHIFT	0
  78
  79/* Bits of IMX I2C registers */
  80#define I2SR_RXAK	0x01
  81#define I2SR_IIF	0x02
  82#define I2SR_SRW	0x04
  83#define I2SR_IAL	0x10
  84#define I2SR_IBB	0x20
  85#define I2SR_IAAS	0x40
  86#define I2SR_ICF	0x80
  87#define I2CR_DMAEN	0x02
  88#define I2CR_RSTA	0x04
  89#define I2CR_TXAK	0x08
  90#define I2CR_MTX	0x10
  91#define I2CR_MSTA	0x20
  92#define I2CR_IIEN	0x40
  93#define I2CR_IEN	0x80
  94
  95/* register bits different operating codes definition:
  96 * 1) I2SR: Interrupt flags clear operation differ between SoCs:
  97 * - write zero to clear(w0c) INT flag on i.MX,
  98 * - but write one to clear(w1c) INT flag on Vybrid.
  99 * 2) I2CR: I2C module enable operation also differ between SoCs:
 100 * - set I2CR_IEN bit enable the module on i.MX,
 101 * - but clear I2CR_IEN bit enable the module on Vybrid.
 102 */
 103#define I2SR_CLR_OPCODE_W0C	0x0
 104#define I2SR_CLR_OPCODE_W1C	(I2SR_IAL | I2SR_IIF)
 105#define I2CR_IEN_OPCODE_0	0x0
 106#define I2CR_IEN_OPCODE_1	I2CR_IEN
 107
 108#define I2C_PM_TIMEOUT		10 /* ms */
 109
 110/*
 111 * sorted list of clock divider, register value pairs
 112 * taken from table 26-5, p.26-9, Freescale i.MX
 113 * Integrated Portable System Processor Reference Manual
 114 * Document Number: MC9328MXLRM, Rev. 5.1, 06/2007
 115 *
 116 * Duplicated divider values removed from list
 117 */
 118struct imx_i2c_clk_pair {
 119	u16	div;
 120	u16	val;
 121};
 122
 123static struct imx_i2c_clk_pair imx_i2c_clk_div[] = {
 124	{ 22,	0x20 }, { 24,	0x21 }, { 26,	0x22 }, { 28,	0x23 },
 125	{ 30,	0x00 },	{ 32,	0x24 }, { 36,	0x25 }, { 40,	0x26 },
 126	{ 42,	0x03 }, { 44,	0x27 },	{ 48,	0x28 }, { 52,	0x05 },
 127	{ 56,	0x29 }, { 60,	0x06 }, { 64,	0x2A },	{ 72,	0x2B },
 128	{ 80,	0x2C }, { 88,	0x09 }, { 96,	0x2D }, { 104,	0x0A },
 129	{ 112,	0x2E }, { 128,	0x2F }, { 144,	0x0C }, { 160,	0x30 },
 130	{ 192,	0x31 },	{ 224,	0x32 }, { 240,	0x0F }, { 256,	0x33 },
 131	{ 288,	0x10 }, { 320,	0x34 },	{ 384,	0x35 }, { 448,	0x36 },
 132	{ 480,	0x13 }, { 512,	0x37 }, { 576,	0x14 },	{ 640,	0x38 },
 133	{ 768,	0x39 }, { 896,	0x3A }, { 960,	0x17 }, { 1024,	0x3B },
 134	{ 1152,	0x18 }, { 1280,	0x3C }, { 1536,	0x3D }, { 1792,	0x3E },
 135	{ 1920,	0x1B },	{ 2048,	0x3F }, { 2304,	0x1C }, { 2560,	0x1D },
 136	{ 3072,	0x1E }, { 3840,	0x1F }
 137};
 138
 139/* Vybrid VF610 clock divider, register value pairs */
 140static struct imx_i2c_clk_pair vf610_i2c_clk_div[] = {
 141	{ 20,   0x00 }, { 22,   0x01 }, { 24,   0x02 }, { 26,   0x03 },
 142	{ 28,   0x04 }, { 30,   0x05 }, { 32,   0x09 }, { 34,   0x06 },
 143	{ 36,   0x0A }, { 40,   0x07 }, { 44,   0x0C }, { 48,   0x0D },
 144	{ 52,   0x43 }, { 56,   0x0E }, { 60,   0x45 }, { 64,   0x12 },
 145	{ 68,   0x0F }, { 72,   0x13 }, { 80,   0x14 }, { 88,   0x15 },
 146	{ 96,   0x19 }, { 104,  0x16 }, { 112,  0x1A }, { 128,  0x17 },
 147	{ 136,  0x4F }, { 144,  0x1C }, { 160,  0x1D }, { 176,  0x55 },
 148	{ 192,  0x1E }, { 208,  0x56 }, { 224,  0x22 }, { 228,  0x24 },
 149	{ 240,  0x1F }, { 256,  0x23 }, { 288,  0x5C }, { 320,  0x25 },
 150	{ 384,  0x26 }, { 448,  0x2A }, { 480,  0x27 }, { 512,  0x2B },
 151	{ 576,  0x2C }, { 640,  0x2D }, { 768,  0x31 }, { 896,  0x32 },
 152	{ 960,  0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
 153	{ 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
 154	{ 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
 155	{ 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
 156};
 157
 158enum imx_i2c_type {
 159	IMX1_I2C,
 160	IMX21_I2C,
 161	VF610_I2C,
 162};
 163
 164struct imx_i2c_hwdata {
 165	enum imx_i2c_type	devtype;
 166	unsigned		regshift;
 167	struct imx_i2c_clk_pair	*clk_div;
 168	unsigned		ndivs;
 169	unsigned		i2sr_clr_opcode;
 170	unsigned		i2cr_ien_opcode;
 171};
 172
 173struct imx_i2c_dma {
 174	struct dma_chan		*chan_tx;
 175	struct dma_chan		*chan_rx;
 176	struct dma_chan		*chan_using;
 177	struct completion	cmd_complete;
 178	dma_addr_t		dma_buf;
 179	unsigned int		dma_len;
 180	enum dma_transfer_direction dma_transfer_dir;
 181	enum dma_data_direction dma_data_dir;
 182};
 183
 184struct imx_i2c_struct {
 185	struct i2c_adapter	adapter;
 186	struct clk		*clk;
 187	struct notifier_block	clk_change_nb;
 188	void __iomem		*base;
 189	wait_queue_head_t	queue;
 190	unsigned long		i2csr;
 191	unsigned int		disable_delay;
 192	int			stopped;
 193	unsigned int		ifdr; /* IMX_I2C_IFDR */
 194	unsigned int		cur_clk;
 195	unsigned int		bitrate;
 196	const struct imx_i2c_hwdata	*hwdata;
 197	struct i2c_bus_recovery_info rinfo;
 198
 199	struct pinctrl *pinctrl;
 200	struct pinctrl_state *pinctrl_pins_default;
 201	struct pinctrl_state *pinctrl_pins_gpio;
 202
 203	struct imx_i2c_dma	*dma;
 204};
 205
 206static const struct imx_i2c_hwdata imx1_i2c_hwdata = {
 207	.devtype		= IMX1_I2C,
 208	.regshift		= IMX_I2C_REGSHIFT,
 209	.clk_div		= imx_i2c_clk_div,
 210	.ndivs			= ARRAY_SIZE(imx_i2c_clk_div),
 211	.i2sr_clr_opcode	= I2SR_CLR_OPCODE_W0C,
 212	.i2cr_ien_opcode	= I2CR_IEN_OPCODE_1,
 213
 214};
 215
 216static const struct imx_i2c_hwdata imx21_i2c_hwdata = {
 217	.devtype		= IMX21_I2C,
 218	.regshift		= IMX_I2C_REGSHIFT,
 219	.clk_div		= imx_i2c_clk_div,
 220	.ndivs			= ARRAY_SIZE(imx_i2c_clk_div),
 221	.i2sr_clr_opcode	= I2SR_CLR_OPCODE_W0C,
 222	.i2cr_ien_opcode	= I2CR_IEN_OPCODE_1,
 223
 224};
 225
 226static struct imx_i2c_hwdata vf610_i2c_hwdata = {
 227	.devtype		= VF610_I2C,
 228	.regshift		= VF610_I2C_REGSHIFT,
 229	.clk_div		= vf610_i2c_clk_div,
 230	.ndivs			= ARRAY_SIZE(vf610_i2c_clk_div),
 231	.i2sr_clr_opcode	= I2SR_CLR_OPCODE_W1C,
 232	.i2cr_ien_opcode	= I2CR_IEN_OPCODE_0,
 233
 234};
 235
 236static const struct platform_device_id imx_i2c_devtype[] = {
 237	{
 238		.name = "imx1-i2c",
 239		.driver_data = (kernel_ulong_t)&imx1_i2c_hwdata,
 240	}, {
 241		.name = "imx21-i2c",
 242		.driver_data = (kernel_ulong_t)&imx21_i2c_hwdata,
 243	}, {
 244		/* sentinel */
 245	}
 246};
 247MODULE_DEVICE_TABLE(platform, imx_i2c_devtype);
 248
 249static const struct of_device_id i2c_imx_dt_ids[] = {
 250	{ .compatible = "fsl,imx1-i2c", .data = &imx1_i2c_hwdata, },
 251	{ .compatible = "fsl,imx21-i2c", .data = &imx21_i2c_hwdata, },
 252	{ .compatible = "fsl,vf610-i2c", .data = &vf610_i2c_hwdata, },
 253	{ /* sentinel */ }
 254};
 255MODULE_DEVICE_TABLE(of, i2c_imx_dt_ids);
 256
 257static const struct acpi_device_id i2c_imx_acpi_ids[] = {
 258	{"NXP0001", .driver_data = (kernel_ulong_t)&vf610_i2c_hwdata},
 259	{ }
 260};
 261MODULE_DEVICE_TABLE(acpi, i2c_imx_acpi_ids);
 262
 263static inline int is_imx1_i2c(struct imx_i2c_struct *i2c_imx)
 264{
 265	return i2c_imx->hwdata->devtype == IMX1_I2C;
 266}
 267
 268static inline void imx_i2c_write_reg(unsigned int val,
 269		struct imx_i2c_struct *i2c_imx, unsigned int reg)
 270{
 271	writeb(val, i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
 272}
 273
 274static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct *i2c_imx,
 275		unsigned int reg)
 276{
 277	return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
 278}
 279
 280/* Functions for DMA support */
 281static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx,
 282						dma_addr_t phy_addr)
 283{
 284	struct imx_i2c_dma *dma;
 285	struct dma_slave_config dma_sconfig;
 286	struct device *dev = &i2c_imx->adapter.dev;
 287	int ret;
 288
 289	dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
 290	if (!dma)
 291		return;
 292
 293	dma->chan_tx = dma_request_chan(dev, "tx");
 294	if (IS_ERR(dma->chan_tx)) {
 295		ret = PTR_ERR(dma->chan_tx);
 296		if (ret != -ENODEV && ret != -EPROBE_DEFER)
 297			dev_err(dev, "can't request DMA tx channel (%d)\n", ret);
 298		goto fail_al;
 299	}
 300
 301	dma_sconfig.dst_addr = phy_addr +
 302				(IMX_I2C_I2DR << i2c_imx->hwdata->regshift);
 303	dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 304	dma_sconfig.dst_maxburst = 1;
 305	dma_sconfig.direction = DMA_MEM_TO_DEV;
 306	ret = dmaengine_slave_config(dma->chan_tx, &dma_sconfig);
 307	if (ret < 0) {
 308		dev_err(dev, "can't configure tx channel (%d)\n", ret);
 309		goto fail_tx;
 310	}
 311
 312	dma->chan_rx = dma_request_chan(dev, "rx");
 313	if (IS_ERR(dma->chan_rx)) {
 314		ret = PTR_ERR(dma->chan_rx);
 315		if (ret != -ENODEV && ret != -EPROBE_DEFER)
 316			dev_err(dev, "can't request DMA rx channel (%d)\n", ret);
 317		goto fail_tx;
 318	}
 319
 320	dma_sconfig.src_addr = phy_addr +
 321				(IMX_I2C_I2DR << i2c_imx->hwdata->regshift);
 322	dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 323	dma_sconfig.src_maxburst = 1;
 324	dma_sconfig.direction = DMA_DEV_TO_MEM;
 325	ret = dmaengine_slave_config(dma->chan_rx, &dma_sconfig);
 326	if (ret < 0) {
 327		dev_err(dev, "can't configure rx channel (%d)\n", ret);
 328		goto fail_rx;
 329	}
 330
 331	i2c_imx->dma = dma;
 332	init_completion(&dma->cmd_complete);
 333	dev_info(dev, "using %s (tx) and %s (rx) for DMA transfers\n",
 334		dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx));
 335
 336	return;
 337
 338fail_rx:
 339	dma_release_channel(dma->chan_rx);
 340fail_tx:
 341	dma_release_channel(dma->chan_tx);
 342fail_al:
 343	devm_kfree(dev, dma);
 344}
 345
 346static void i2c_imx_dma_callback(void *arg)
 347{
 348	struct imx_i2c_struct *i2c_imx = (struct imx_i2c_struct *)arg;
 349	struct imx_i2c_dma *dma = i2c_imx->dma;
 350
 351	dma_unmap_single(dma->chan_using->device->dev, dma->dma_buf,
 352			dma->dma_len, dma->dma_data_dir);
 353	complete(&dma->cmd_complete);
 354}
 355
 356static int i2c_imx_dma_xfer(struct imx_i2c_struct *i2c_imx,
 357					struct i2c_msg *msgs)
 358{
 359	struct imx_i2c_dma *dma = i2c_imx->dma;
 360	struct dma_async_tx_descriptor *txdesc;
 361	struct device *dev = &i2c_imx->adapter.dev;
 362	struct device *chan_dev = dma->chan_using->device->dev;
 363
 364	dma->dma_buf = dma_map_single(chan_dev, msgs->buf,
 365					dma->dma_len, dma->dma_data_dir);
 366	if (dma_mapping_error(chan_dev, dma->dma_buf)) {
 367		dev_err(dev, "DMA mapping failed\n");
 368		goto err_map;
 369	}
 370
 371	txdesc = dmaengine_prep_slave_single(dma->chan_using, dma->dma_buf,
 372					dma->dma_len, dma->dma_transfer_dir,
 373					DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 374	if (!txdesc) {
 375		dev_err(dev, "Not able to get desc for DMA xfer\n");
 376		goto err_desc;
 377	}
 378
 379	reinit_completion(&dma->cmd_complete);
 380	txdesc->callback = i2c_imx_dma_callback;
 381	txdesc->callback_param = i2c_imx;
 382	if (dma_submit_error(dmaengine_submit(txdesc))) {
 383		dev_err(dev, "DMA submit failed\n");
 384		goto err_submit;
 385	}
 386
 387	dma_async_issue_pending(dma->chan_using);
 388	return 0;
 389
 390err_submit:
 391	dmaengine_terminate_all(dma->chan_using);
 392err_desc:
 393	dma_unmap_single(chan_dev, dma->dma_buf,
 394			dma->dma_len, dma->dma_data_dir);
 395err_map:
 396	return -EINVAL;
 397}
 398
 399static void i2c_imx_dma_free(struct imx_i2c_struct *i2c_imx)
 400{
 401	struct imx_i2c_dma *dma = i2c_imx->dma;
 402
 403	dma->dma_buf = 0;
 404	dma->dma_len = 0;
 405
 406	dma_release_channel(dma->chan_tx);
 407	dma->chan_tx = NULL;
 408
 409	dma_release_channel(dma->chan_rx);
 410	dma->chan_rx = NULL;
 411
 412	dma->chan_using = NULL;
 413}
 414
 415static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy, bool atomic)
 416{
 417	unsigned long orig_jiffies = jiffies;
 418	unsigned int temp;
 419
 420	dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
 421
 422	while (1) {
 423		temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
 424
 425		/* check for arbitration lost */
 426		if (temp & I2SR_IAL) {
 427			temp &= ~I2SR_IAL;
 428			imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR);
 429			return -EAGAIN;
 430		}
 431
 432		if (for_busy && (temp & I2SR_IBB)) {
 433			i2c_imx->stopped = 0;
 434			break;
 435		}
 436		if (!for_busy && !(temp & I2SR_IBB)) {
 437			i2c_imx->stopped = 1;
 438			break;
 439		}
 440		if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {
 441			dev_dbg(&i2c_imx->adapter.dev,
 442				"<%s> I2C bus is busy\n", __func__);
 443			return -ETIMEDOUT;
 444		}
 445		if (atomic)
 446			udelay(100);
 447		else
 448			schedule();
 449	}
 450
 451	return 0;
 452}
 453
 454static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx, bool atomic)
 455{
 456	if (atomic) {
 457		void __iomem *addr = i2c_imx->base + (IMX_I2C_I2SR << i2c_imx->hwdata->regshift);
 458		unsigned int regval;
 459
 460		/*
 461		 * The formula for the poll timeout is documented in the RM
 462		 * Rev.5 on page 1878:
 463		 *     T_min = 10/F_scl
 464		 * Set the value hard as it is done for the non-atomic use-case.
 465		 * Use 10 kHz for the calculation since this is the minimum
 466		 * allowed SMBus frequency. Also add an offset of 100us since it
 467		 * turned out that the I2SR_IIF bit isn't set correctly within
 468		 * the minimum timeout in polling mode.
 469		 */
 470		readb_poll_timeout_atomic(addr, regval, regval & I2SR_IIF, 5, 1000 + 100);
 471		i2c_imx->i2csr = regval;
 472		imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2SR);
 473	} else {
 474		wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10);
 475	}
 476
 477	if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) {
 478		dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__);
 479		return -ETIMEDOUT;
 480	}
 481	dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__);
 482	i2c_imx->i2csr = 0;
 483	return 0;
 484}
 485
 486static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx)
 487{
 488	if (imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR) & I2SR_RXAK) {
 489		dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__);
 490		return -ENXIO;  /* No ACK */
 491	}
 492
 493	dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__);
 494	return 0;
 495}
 496
 497static void i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx,
 498			    unsigned int i2c_clk_rate)
 499{
 500	struct imx_i2c_clk_pair *i2c_clk_div = i2c_imx->hwdata->clk_div;
 501	unsigned int div;
 502	int i;
 503
 504	/* Divider value calculation */
 505	if (i2c_imx->cur_clk == i2c_clk_rate)
 506		return;
 507
 508	i2c_imx->cur_clk = i2c_clk_rate;
 509
 510	div = (i2c_clk_rate + i2c_imx->bitrate - 1) / i2c_imx->bitrate;
 511	if (div < i2c_clk_div[0].div)
 512		i = 0;
 513	else if (div > i2c_clk_div[i2c_imx->hwdata->ndivs - 1].div)
 514		i = i2c_imx->hwdata->ndivs - 1;
 515	else
 516		for (i = 0; i2c_clk_div[i].div < div; i++)
 517			;
 518
 519	/* Store divider value */
 520	i2c_imx->ifdr = i2c_clk_div[i].val;
 521
 522	/*
 523	 * There dummy delay is calculated.
 524	 * It should be about one I2C clock period long.
 525	 * This delay is used in I2C bus disable function
 526	 * to fix chip hardware bug.
 527	 */
 528	i2c_imx->disable_delay = (500000U * i2c_clk_div[i].div
 529		+ (i2c_clk_rate / 2) - 1) / (i2c_clk_rate / 2);
 530
 531#ifdef CONFIG_I2C_DEBUG_BUS
 532	dev_dbg(&i2c_imx->adapter.dev, "I2C_CLK=%d, REQ DIV=%d\n",
 533		i2c_clk_rate, div);
 534	dev_dbg(&i2c_imx->adapter.dev, "IFDR[IC]=0x%x, REAL DIV=%d\n",
 535		i2c_clk_div[i].val, i2c_clk_div[i].div);
 536#endif
 537}
 538
 539static int i2c_imx_clk_notifier_call(struct notifier_block *nb,
 540				     unsigned long action, void *data)
 541{
 542	struct clk_notifier_data *ndata = data;
 543	struct imx_i2c_struct *i2c_imx = container_of(nb,
 544						      struct imx_i2c_struct,
 545						      clk_change_nb);
 546
 547	if (action & POST_RATE_CHANGE)
 548		i2c_imx_set_clk(i2c_imx, ndata->new_rate);
 549
 550	return NOTIFY_OK;
 551}
 552
 553static int i2c_imx_start(struct imx_i2c_struct *i2c_imx, bool atomic)
 554{
 555	unsigned int temp = 0;
 556	int result;
 557
 558	dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
 559
 560	imx_i2c_write_reg(i2c_imx->ifdr, i2c_imx, IMX_I2C_IFDR);
 561	/* Enable I2C controller */
 562	imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR);
 563	imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode, i2c_imx, IMX_I2C_I2CR);
 564
 565	/* Wait controller to be stable */
 566	if (atomic)
 567		udelay(50);
 568	else
 569		usleep_range(50, 150);
 570
 571	/* Start I2C transaction */
 572	temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 573	temp |= I2CR_MSTA;
 574	imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 575	result = i2c_imx_bus_busy(i2c_imx, 1, atomic);
 576	if (result)
 577		return result;
 578
 579	temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK;
 580	if (atomic)
 581		temp &= ~I2CR_IIEN; /* Disable interrupt */
 582
 583	temp &= ~I2CR_DMAEN;
 584	imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 585	return result;
 586}
 587
 588static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx, bool atomic)
 589{
 590	unsigned int temp = 0;
 591
 592	if (!i2c_imx->stopped) {
 593		/* Stop I2C transaction */
 594		dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
 595		temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 596		temp &= ~(I2CR_MSTA | I2CR_MTX);
 597		if (i2c_imx->dma)
 598			temp &= ~I2CR_DMAEN;
 599		imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 600	}
 601	if (is_imx1_i2c(i2c_imx)) {
 602		/*
 603		 * This delay caused by an i.MXL hardware bug.
 604		 * If no (or too short) delay, no "STOP" bit will be generated.
 605		 */
 606		udelay(i2c_imx->disable_delay);
 607	}
 608
 609	if (!i2c_imx->stopped)
 610		i2c_imx_bus_busy(i2c_imx, 0, atomic);
 611
 612	/* Disable I2C controller */
 613	temp = i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
 614	imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 615}
 616
 617static irqreturn_t i2c_imx_isr(int irq, void *dev_id)
 618{
 619	struct imx_i2c_struct *i2c_imx = dev_id;
 620	unsigned int temp;
 621
 622	temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
 623	if (temp & I2SR_IIF) {
 624		/* save status register */
 625		i2c_imx->i2csr = temp;
 626		temp &= ~I2SR_IIF;
 627		temp |= (i2c_imx->hwdata->i2sr_clr_opcode & I2SR_IIF);
 628		imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR);
 629		wake_up(&i2c_imx->queue);
 630		return IRQ_HANDLED;
 631	}
 632
 633	return IRQ_NONE;
 634}
 635
 636static int i2c_imx_dma_write(struct imx_i2c_struct *i2c_imx,
 637					struct i2c_msg *msgs)
 638{
 639	int result;
 640	unsigned long time_left;
 641	unsigned int temp = 0;
 642	unsigned long orig_jiffies = jiffies;
 643	struct imx_i2c_dma *dma = i2c_imx->dma;
 644	struct device *dev = &i2c_imx->adapter.dev;
 645
 646	dma->chan_using = dma->chan_tx;
 647	dma->dma_transfer_dir = DMA_MEM_TO_DEV;
 648	dma->dma_data_dir = DMA_TO_DEVICE;
 649	dma->dma_len = msgs->len - 1;
 650	result = i2c_imx_dma_xfer(i2c_imx, msgs);
 651	if (result)
 652		return result;
 653
 654	temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 655	temp |= I2CR_DMAEN;
 656	imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 657
 658	/*
 659	 * Write slave address.
 660	 * The first byte must be transmitted by the CPU.
 661	 */
 662	imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR);
 663	time_left = wait_for_completion_timeout(
 664				&i2c_imx->dma->cmd_complete,
 665				msecs_to_jiffies(DMA_TIMEOUT));
 666	if (time_left == 0) {
 667		dmaengine_terminate_all(dma->chan_using);
 668		return -ETIMEDOUT;
 669	}
 670
 671	/* Waiting for transfer complete. */
 672	while (1) {
 673		temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
 674		if (temp & I2SR_ICF)
 675			break;
 676		if (time_after(jiffies, orig_jiffies +
 677				msecs_to_jiffies(DMA_TIMEOUT))) {
 678			dev_dbg(dev, "<%s> Timeout\n", __func__);
 679			return -ETIMEDOUT;
 680		}
 681		schedule();
 682	}
 683
 684	temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 685	temp &= ~I2CR_DMAEN;
 686	imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 687
 688	/* The last data byte must be transferred by the CPU. */
 689	imx_i2c_write_reg(msgs->buf[msgs->len-1],
 690				i2c_imx, IMX_I2C_I2DR);
 691	result = i2c_imx_trx_complete(i2c_imx, false);
 692	if (result)
 693		return result;
 694
 695	return i2c_imx_acked(i2c_imx);
 696}
 697
 698static int i2c_imx_dma_read(struct imx_i2c_struct *i2c_imx,
 699			struct i2c_msg *msgs, bool is_lastmsg)
 700{
 701	int result;
 702	unsigned long time_left;
 703	unsigned int temp;
 704	unsigned long orig_jiffies = jiffies;
 705	struct imx_i2c_dma *dma = i2c_imx->dma;
 706	struct device *dev = &i2c_imx->adapter.dev;
 707
 708
 709	dma->chan_using = dma->chan_rx;
 710	dma->dma_transfer_dir = DMA_DEV_TO_MEM;
 711	dma->dma_data_dir = DMA_FROM_DEVICE;
 712	/* The last two data bytes must be transferred by the CPU. */
 713	dma->dma_len = msgs->len - 2;
 714	result = i2c_imx_dma_xfer(i2c_imx, msgs);
 715	if (result)
 716		return result;
 717
 718	time_left = wait_for_completion_timeout(
 719				&i2c_imx->dma->cmd_complete,
 720				msecs_to_jiffies(DMA_TIMEOUT));
 721	if (time_left == 0) {
 722		dmaengine_terminate_all(dma->chan_using);
 723		return -ETIMEDOUT;
 724	}
 725
 726	/* waiting for transfer complete. */
 727	while (1) {
 728		temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
 729		if (temp & I2SR_ICF)
 730			break;
 731		if (time_after(jiffies, orig_jiffies +
 732				msecs_to_jiffies(DMA_TIMEOUT))) {
 733			dev_dbg(dev, "<%s> Timeout\n", __func__);
 734			return -ETIMEDOUT;
 735		}
 736		schedule();
 737	}
 738
 739	temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 740	temp &= ~I2CR_DMAEN;
 741	imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 742
 743	/* read n-1 byte data */
 744	temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 745	temp |= I2CR_TXAK;
 746	imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 747
 748	msgs->buf[msgs->len-2] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
 749	/* read n byte data */
 750	result = i2c_imx_trx_complete(i2c_imx, false);
 751	if (result)
 752		return result;
 753
 754	if (is_lastmsg) {
 755		/*
 756		 * It must generate STOP before read I2DR to prevent
 757		 * controller from generating another clock cycle
 758		 */
 759		dev_dbg(dev, "<%s> clear MSTA\n", __func__);
 760		temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 761		temp &= ~(I2CR_MSTA | I2CR_MTX);
 762		imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 763		i2c_imx_bus_busy(i2c_imx, 0, false);
 764	} else {
 765		/*
 766		 * For i2c master receiver repeat restart operation like:
 767		 * read -> repeat MSTA -> read/write
 768		 * The controller must set MTX before read the last byte in
 769		 * the first read operation, otherwise the first read cost
 770		 * one extra clock cycle.
 771		 */
 772		temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 773		temp |= I2CR_MTX;
 774		imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 775	}
 776	msgs->buf[msgs->len-1] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
 777
 778	return 0;
 779}
 780
 781static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs,
 782			 bool atomic)
 783{
 784	int i, result;
 785
 786	dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n",
 787		__func__, i2c_8bit_addr_from_msg(msgs));
 788
 789	/* write slave address */
 790	imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR);
 791	result = i2c_imx_trx_complete(i2c_imx, atomic);
 792	if (result)
 793		return result;
 794	result = i2c_imx_acked(i2c_imx);
 795	if (result)
 796		return result;
 797	dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__);
 798
 799	/* write data */
 800	for (i = 0; i < msgs->len; i++) {
 801		dev_dbg(&i2c_imx->adapter.dev,
 802			"<%s> write byte: B%d=0x%X\n",
 803			__func__, i, msgs->buf[i]);
 804		imx_i2c_write_reg(msgs->buf[i], i2c_imx, IMX_I2C_I2DR);
 805		result = i2c_imx_trx_complete(i2c_imx, atomic);
 806		if (result)
 807			return result;
 808		result = i2c_imx_acked(i2c_imx);
 809		if (result)
 810			return result;
 811	}
 812	return 0;
 813}
 814
 815static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs,
 816			bool is_lastmsg, bool atomic)
 817{
 818	int i, result;
 819	unsigned int temp;
 820	int block_data = msgs->flags & I2C_M_RECV_LEN;
 821	int use_dma = i2c_imx->dma && msgs->len >= DMA_THRESHOLD && !block_data;
 822
 823	dev_dbg(&i2c_imx->adapter.dev,
 824		"<%s> write slave address: addr=0x%x\n",
 825		__func__, i2c_8bit_addr_from_msg(msgs));
 826
 827	/* write slave address */
 828	imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR);
 829	result = i2c_imx_trx_complete(i2c_imx, atomic);
 830	if (result)
 831		return result;
 832	result = i2c_imx_acked(i2c_imx);
 833	if (result)
 834		return result;
 835
 836	dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__);
 837
 838	/* setup bus to read data */
 839	temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 840	temp &= ~I2CR_MTX;
 841
 842	/*
 843	 * Reset the I2CR_TXAK flag initially for SMBus block read since the
 844	 * length is unknown
 845	 */
 846	if ((msgs->len - 1) || block_data)
 847		temp &= ~I2CR_TXAK;
 848	if (use_dma)
 849		temp |= I2CR_DMAEN;
 850	imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 851	imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); /* dummy read */
 852
 853	dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__);
 854
 855	if (use_dma)
 856		return i2c_imx_dma_read(i2c_imx, msgs, is_lastmsg);
 857
 858	/* read data */
 859	for (i = 0; i < msgs->len; i++) {
 860		u8 len = 0;
 861
 862		result = i2c_imx_trx_complete(i2c_imx, atomic);
 863		if (result)
 864			return result;
 865		/*
 866		 * First byte is the length of remaining packet
 867		 * in the SMBus block data read. Add it to
 868		 * msgs->len.
 869		 */
 870		if ((!i) && block_data) {
 871			len = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
 872			if ((len == 0) || (len > I2C_SMBUS_BLOCK_MAX))
 873				return -EPROTO;
 874			dev_dbg(&i2c_imx->adapter.dev,
 875				"<%s> read length: 0x%X\n",
 876				__func__, len);
 877			msgs->len += len;
 878		}
 879		if (i == (msgs->len - 1)) {
 880			if (is_lastmsg) {
 881				/*
 882				 * It must generate STOP before read I2DR to prevent
 883				 * controller from generating another clock cycle
 884				 */
 885				dev_dbg(&i2c_imx->adapter.dev,
 886					"<%s> clear MSTA\n", __func__);
 887				temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 888				temp &= ~(I2CR_MSTA | I2CR_MTX);
 889				imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 890				i2c_imx_bus_busy(i2c_imx, 0, atomic);
 891			} else {
 892				/*
 893				 * For i2c master receiver repeat restart operation like:
 894				 * read -> repeat MSTA -> read/write
 895				 * The controller must set MTX before read the last byte in
 896				 * the first read operation, otherwise the first read cost
 897				 * one extra clock cycle.
 898				 */
 899				temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 900				temp |= I2CR_MTX;
 901				imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 902			}
 903		} else if (i == (msgs->len - 2)) {
 904			dev_dbg(&i2c_imx->adapter.dev,
 905				"<%s> set TXAK\n", __func__);
 906			temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 907			temp |= I2CR_TXAK;
 908			imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 909		}
 910		if ((!i) && block_data)
 911			msgs->buf[0] = len;
 912		else
 913			msgs->buf[i] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
 914		dev_dbg(&i2c_imx->adapter.dev,
 915			"<%s> read byte: B%d=0x%X\n",
 916			__func__, i, msgs->buf[i]);
 917	}
 918	return 0;
 919}
 920
 921static int i2c_imx_xfer_common(struct i2c_adapter *adapter,
 922			       struct i2c_msg *msgs, int num, bool atomic)
 923{
 924	unsigned int i, temp;
 925	int result;
 926	bool is_lastmsg = false;
 927	struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);
 928
 929	dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
 930
 931	/* Start I2C transfer */
 932	result = i2c_imx_start(i2c_imx, atomic);
 933	if (result) {
 934		/*
 935		 * Bus recovery uses gpiod_get_value_cansleep() which is not
 936		 * allowed within atomic context.
 937		 */
 938		if (!atomic && i2c_imx->adapter.bus_recovery_info) {
 939			i2c_recover_bus(&i2c_imx->adapter);
 940			result = i2c_imx_start(i2c_imx, atomic);
 941		}
 942	}
 943
 944	if (result)
 945		goto fail0;
 946
 947	/* read/write data */
 948	for (i = 0; i < num; i++) {
 949		if (i == num - 1)
 950			is_lastmsg = true;
 951
 952		if (i) {
 953			dev_dbg(&i2c_imx->adapter.dev,
 954				"<%s> repeated start\n", __func__);
 955			temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 956			temp |= I2CR_RSTA;
 957			imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 958			result = i2c_imx_bus_busy(i2c_imx, 1, atomic);
 959			if (result)
 960				goto fail0;
 961		}
 962		dev_dbg(&i2c_imx->adapter.dev,
 963			"<%s> transfer message: %d\n", __func__, i);
 964		/* write/read data */
 965#ifdef CONFIG_I2C_DEBUG_BUS
 966		temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 967		dev_dbg(&i2c_imx->adapter.dev,
 968			"<%s> CONTROL: IEN=%d, IIEN=%d, MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n",
 969			__func__,
 970			(temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0),
 971			(temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0),
 972			(temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0));
 973		temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
 974		dev_dbg(&i2c_imx->adapter.dev,
 975			"<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n",
 976			__func__,
 977			(temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0),
 978			(temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0),
 979			(temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0),
 980			(temp & I2SR_RXAK ? 1 : 0));
 981#endif
 982		if (msgs[i].flags & I2C_M_RD) {
 983			result = i2c_imx_read(i2c_imx, &msgs[i], is_lastmsg, atomic);
 984		} else {
 985			if (!atomic &&
 986			    i2c_imx->dma && msgs[i].len >= DMA_THRESHOLD)
 987				result = i2c_imx_dma_write(i2c_imx, &msgs[i]);
 988			else
 989				result = i2c_imx_write(i2c_imx, &msgs[i], atomic);
 990		}
 991		if (result)
 992			goto fail0;
 993	}
 994
 995fail0:
 996	/* Stop I2C transfer */
 997	i2c_imx_stop(i2c_imx, atomic);
 998
 999	dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__,
1000		(result < 0) ? "error" : "success msg",
1001			(result < 0) ? result : num);
1002	return (result < 0) ? result : num;
1003}
1004
1005static int i2c_imx_xfer(struct i2c_adapter *adapter,
1006			struct i2c_msg *msgs, int num)
1007{
1008	struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);
1009	int result;
1010
1011	result = pm_runtime_get_sync(i2c_imx->adapter.dev.parent);
1012	if (result < 0)
1013		return result;
1014
1015	result = i2c_imx_xfer_common(adapter, msgs, num, false);
1016
1017	pm_runtime_mark_last_busy(i2c_imx->adapter.dev.parent);
1018	pm_runtime_put_autosuspend(i2c_imx->adapter.dev.parent);
1019
1020	return result;
1021}
1022
1023static int i2c_imx_xfer_atomic(struct i2c_adapter *adapter,
1024			       struct i2c_msg *msgs, int num)
1025{
1026	struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);
1027	int result;
1028
1029	result = clk_enable(i2c_imx->clk);
1030	if (result)
1031		return result;
1032
1033	result = i2c_imx_xfer_common(adapter, msgs, num, true);
1034
1035	clk_disable(i2c_imx->clk);
1036
1037	return result;
1038}
1039
1040static void i2c_imx_prepare_recovery(struct i2c_adapter *adap)
1041{
1042	struct imx_i2c_struct *i2c_imx;
1043
1044	i2c_imx = container_of(adap, struct imx_i2c_struct, adapter);
1045
1046	pinctrl_select_state(i2c_imx->pinctrl, i2c_imx->pinctrl_pins_gpio);
1047}
1048
1049static void i2c_imx_unprepare_recovery(struct i2c_adapter *adap)
1050{
1051	struct imx_i2c_struct *i2c_imx;
1052
1053	i2c_imx = container_of(adap, struct imx_i2c_struct, adapter);
1054
1055	pinctrl_select_state(i2c_imx->pinctrl, i2c_imx->pinctrl_pins_default);
1056}
1057
1058/*
1059 * We switch SCL and SDA to their GPIO function and do some bitbanging
1060 * for bus recovery. These alternative pinmux settings can be
1061 * described in the device tree by a separate pinctrl state "gpio". If
1062 * this is missing this is not a big problem, the only implication is
1063 * that we can't do bus recovery.
1064 */
1065static int i2c_imx_init_recovery_info(struct imx_i2c_struct *i2c_imx,
1066		struct platform_device *pdev)
1067{
1068	struct i2c_bus_recovery_info *rinfo = &i2c_imx->rinfo;
1069
1070	i2c_imx->pinctrl = devm_pinctrl_get(&pdev->dev);
1071	if (!i2c_imx->pinctrl || IS_ERR(i2c_imx->pinctrl)) {
1072		dev_info(&pdev->dev, "can't get pinctrl, bus recovery not supported\n");
1073		return PTR_ERR(i2c_imx->pinctrl);
1074	}
1075
1076	i2c_imx->pinctrl_pins_default = pinctrl_lookup_state(i2c_imx->pinctrl,
1077			PINCTRL_STATE_DEFAULT);
1078	i2c_imx->pinctrl_pins_gpio = pinctrl_lookup_state(i2c_imx->pinctrl,
1079			"gpio");
1080	rinfo->sda_gpiod = devm_gpiod_get(&pdev->dev, "sda", GPIOD_IN);
1081	rinfo->scl_gpiod = devm_gpiod_get(&pdev->dev, "scl", GPIOD_OUT_HIGH_OPEN_DRAIN);
1082
1083	if (PTR_ERR(rinfo->sda_gpiod) == -EPROBE_DEFER ||
1084	    PTR_ERR(rinfo->scl_gpiod) == -EPROBE_DEFER) {
1085		return -EPROBE_DEFER;
1086	} else if (IS_ERR(rinfo->sda_gpiod) ||
1087		   IS_ERR(rinfo->scl_gpiod) ||
1088		   IS_ERR(i2c_imx->pinctrl_pins_default) ||
1089		   IS_ERR(i2c_imx->pinctrl_pins_gpio)) {
1090		dev_dbg(&pdev->dev, "recovery information incomplete\n");
1091		return 0;
1092	}
1093
1094	dev_dbg(&pdev->dev, "using scl%s for recovery\n",
1095		rinfo->sda_gpiod ? ",sda" : "");
1096
1097	rinfo->prepare_recovery = i2c_imx_prepare_recovery;
1098	rinfo->unprepare_recovery = i2c_imx_unprepare_recovery;
1099	rinfo->recover_bus = i2c_generic_scl_recovery;
1100	i2c_imx->adapter.bus_recovery_info = rinfo;
1101
1102	return 0;
1103}
1104
1105static u32 i2c_imx_func(struct i2c_adapter *adapter)
1106{
1107	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL
1108		| I2C_FUNC_SMBUS_READ_BLOCK_DATA;
1109}
1110
1111static const struct i2c_algorithm i2c_imx_algo = {
1112	.master_xfer = i2c_imx_xfer,
1113	.master_xfer_atomic = i2c_imx_xfer_atomic,
1114	.functionality = i2c_imx_func,
1115};
1116
1117static int i2c_imx_probe(struct platform_device *pdev)
1118{
1119	struct imx_i2c_struct *i2c_imx;
1120	struct resource *res;
1121	struct imxi2c_platform_data *pdata = dev_get_platdata(&pdev->dev);
1122	void __iomem *base;
1123	int irq, ret;
1124	dma_addr_t phy_addr;
1125	const struct imx_i2c_hwdata *match;
1126
1127	dev_dbg(&pdev->dev, "<%s>\n", __func__);
1128
1129	irq = platform_get_irq(pdev, 0);
1130	if (irq < 0)
1131		return irq;
1132
1133	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1134	base = devm_ioremap_resource(&pdev->dev, res);
1135	if (IS_ERR(base))
1136		return PTR_ERR(base);
1137
1138	phy_addr = (dma_addr_t)res->start;
1139	i2c_imx = devm_kzalloc(&pdev->dev, sizeof(*i2c_imx), GFP_KERNEL);
1140	if (!i2c_imx)
1141		return -ENOMEM;
1142
1143	match = device_get_match_data(&pdev->dev);
1144	if (match)
1145		i2c_imx->hwdata = match;
1146	else
1147		i2c_imx->hwdata = (struct imx_i2c_hwdata *)
1148				platform_get_device_id(pdev)->driver_data;
1149
1150	/* Setup i2c_imx driver structure */
1151	strlcpy(i2c_imx->adapter.name, pdev->name, sizeof(i2c_imx->adapter.name));
1152	i2c_imx->adapter.owner		= THIS_MODULE;
1153	i2c_imx->adapter.algo		= &i2c_imx_algo;
1154	i2c_imx->adapter.dev.parent	= &pdev->dev;
1155	i2c_imx->adapter.nr		= pdev->id;
1156	i2c_imx->adapter.dev.of_node	= pdev->dev.of_node;
1157	i2c_imx->base			= base;
1158	ACPI_COMPANION_SET(&i2c_imx->adapter.dev, ACPI_COMPANION(&pdev->dev));
1159
1160	/* Get I2C clock */
1161	i2c_imx->clk = devm_clk_get(&pdev->dev, NULL);
1162	if (IS_ERR(i2c_imx->clk)) {
1163		if (PTR_ERR(i2c_imx->clk) != -EPROBE_DEFER)
1164			dev_err(&pdev->dev, "can't get I2C clock\n");
1165		return PTR_ERR(i2c_imx->clk);
1166	}
1167
1168	ret = clk_prepare_enable(i2c_imx->clk);
1169	if (ret) {
1170		dev_err(&pdev->dev, "can't enable I2C clock, ret=%d\n", ret);
1171		return ret;
1172	}
1173
1174	/* Request IRQ */
1175	ret = devm_request_irq(&pdev->dev, irq, i2c_imx_isr, IRQF_SHARED,
1176				pdev->name, i2c_imx);
1177	if (ret) {
1178		dev_err(&pdev->dev, "can't claim irq %d\n", irq);
1179		goto clk_disable;
1180	}
1181
1182	/* Init queue */
1183	init_waitqueue_head(&i2c_imx->queue);
1184
1185	/* Set up adapter data */
1186	i2c_set_adapdata(&i2c_imx->adapter, i2c_imx);
1187
1188	/* Set up platform driver data */
1189	platform_set_drvdata(pdev, i2c_imx);
1190
1191	pm_runtime_set_autosuspend_delay(&pdev->dev, I2C_PM_TIMEOUT);
1192	pm_runtime_use_autosuspend(&pdev->dev);
1193	pm_runtime_set_active(&pdev->dev);
1194	pm_runtime_enable(&pdev->dev);
1195
1196	ret = pm_runtime_get_sync(&pdev->dev);
1197	if (ret < 0)
1198		goto rpm_disable;
1199
1200	/* Set up clock divider */
1201	i2c_imx->bitrate = I2C_MAX_STANDARD_MODE_FREQ;
1202	ret = of_property_read_u32(pdev->dev.of_node,
1203				   "clock-frequency", &i2c_imx->bitrate);
1204	if (ret < 0 && pdata && pdata->bitrate)
1205		i2c_imx->bitrate = pdata->bitrate;
1206	i2c_imx->clk_change_nb.notifier_call = i2c_imx_clk_notifier_call;
1207	clk_notifier_register(i2c_imx->clk, &i2c_imx->clk_change_nb);
1208	i2c_imx_set_clk(i2c_imx, clk_get_rate(i2c_imx->clk));
1209
1210	/* Set up chip registers to defaults */
1211	imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
1212			i2c_imx, IMX_I2C_I2CR);
1213	imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR);
1214
1215	/* Init optional bus recovery function */
1216	ret = i2c_imx_init_recovery_info(i2c_imx, pdev);
1217	/* Give it another chance if pinctrl used is not ready yet */
1218	if (ret == -EPROBE_DEFER)
1219		goto clk_notifier_unregister;
1220
1221	/* Add I2C adapter */
1222	ret = i2c_add_numbered_adapter(&i2c_imx->adapter);
1223	if (ret < 0)
1224		goto clk_notifier_unregister;
1225
1226	pm_runtime_mark_last_busy(&pdev->dev);
1227	pm_runtime_put_autosuspend(&pdev->dev);
1228
1229	dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", irq);
1230	dev_dbg(&i2c_imx->adapter.dev, "device resources: %pR\n", res);
1231	dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n",
1232		i2c_imx->adapter.name);
1233	dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n");
1234
1235	/* Init DMA config if supported */
1236	i2c_imx_dma_request(i2c_imx, phy_addr);
1237
1238	return 0;   /* Return OK */
1239
1240clk_notifier_unregister:
1241	clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb);
1242rpm_disable:
1243	pm_runtime_put_noidle(&pdev->dev);
1244	pm_runtime_disable(&pdev->dev);
1245	pm_runtime_set_suspended(&pdev->dev);
1246	pm_runtime_dont_use_autosuspend(&pdev->dev);
1247
1248clk_disable:
1249	clk_disable_unprepare(i2c_imx->clk);
1250	return ret;
1251}
1252
1253static int i2c_imx_remove(struct platform_device *pdev)
1254{
1255	struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev);
1256	int ret;
1257
1258	ret = pm_runtime_get_sync(&pdev->dev);
1259	if (ret < 0)
1260		return ret;
1261
1262	/* remove adapter */
1263	dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n");
1264	i2c_del_adapter(&i2c_imx->adapter);
1265
1266	if (i2c_imx->dma)
1267		i2c_imx_dma_free(i2c_imx);
1268
1269	/* setup chip registers to defaults */
1270	imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR);
1271	imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IFDR);
1272	imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2CR);
1273	imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2SR);
1274
1275	clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb);
1276	clk_disable_unprepare(i2c_imx->clk);
1277
1278	pm_runtime_put_noidle(&pdev->dev);
1279	pm_runtime_disable(&pdev->dev);
1280
1281	return 0;
1282}
1283
1284static int __maybe_unused i2c_imx_runtime_suspend(struct device *dev)
1285{
1286	struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev);
1287
1288	clk_disable(i2c_imx->clk);
1289
1290	return 0;
1291}
1292
1293static int __maybe_unused i2c_imx_runtime_resume(struct device *dev)
1294{
1295	struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev);
1296	int ret;
1297
1298	ret = clk_enable(i2c_imx->clk);
1299	if (ret)
1300		dev_err(dev, "can't enable I2C clock, ret=%d\n", ret);
1301
1302	return ret;
1303}
1304
1305static const struct dev_pm_ops i2c_imx_pm_ops = {
1306	SET_RUNTIME_PM_OPS(i2c_imx_runtime_suspend,
1307			   i2c_imx_runtime_resume, NULL)
1308};
1309
1310static struct platform_driver i2c_imx_driver = {
1311	.probe = i2c_imx_probe,
1312	.remove = i2c_imx_remove,
1313	.driver = {
1314		.name = DRIVER_NAME,
1315		.pm = &i2c_imx_pm_ops,
1316		.of_match_table = i2c_imx_dt_ids,
1317		.acpi_match_table = i2c_imx_acpi_ids,
1318	},
1319	.id_table = imx_i2c_devtype,
1320};
1321
1322static int __init i2c_adap_imx_init(void)
1323{
1324	return platform_driver_register(&i2c_imx_driver);
1325}
1326subsys_initcall(i2c_adap_imx_init);
1327
1328static void __exit i2c_adap_imx_exit(void)
1329{
1330	platform_driver_unregister(&i2c_imx_driver);
1331}
1332module_exit(i2c_adap_imx_exit);
1333
1334MODULE_LICENSE("GPL");
1335MODULE_AUTHOR("Darius Augulis");
1336MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus");
1337MODULE_ALIAS("platform:" DRIVER_NAME);