/drivers/i2c/busses/i2c-omap.c

http://github.com/mirrors/linux · C · 1616 lines · 1125 code · 260 blank · 231 comment · 148 complexity · 17ba4b50099313bb68b82879b52e923f MD5 · raw file

  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * TI OMAP I2C master mode driver
  4. *
  5. * Copyright (C) 2003 MontaVista Software, Inc.
  6. * Copyright (C) 2005 Nokia Corporation
  7. * Copyright (C) 2004 - 2007 Texas Instruments.
  8. *
  9. * Originally written by MontaVista Software, Inc.
  10. * Additional contributions by:
  11. * Tony Lindgren <tony@atomide.com>
  12. * Imre Deak <imre.deak@nokia.com>
  13. * Juha Yrjölä <juha.yrjola@solidboot.com>
  14. * Syed Khasim <x0khasim@ti.com>
  15. * Nishant Menon <nm@ti.com>
  16. */
  17. #include <linux/module.h>
  18. #include <linux/delay.h>
  19. #include <linux/i2c.h>
  20. #include <linux/err.h>
  21. #include <linux/interrupt.h>
  22. #include <linux/completion.h>
  23. #include <linux/platform_device.h>
  24. #include <linux/clk.h>
  25. #include <linux/io.h>
  26. #include <linux/of.h>
  27. #include <linux/of_device.h>
  28. #include <linux/slab.h>
  29. #include <linux/platform_data/i2c-omap.h>
  30. #include <linux/pm_runtime.h>
  31. #include <linux/pinctrl/consumer.h>
  32. /* I2C controller revisions */
  33. #define OMAP_I2C_OMAP1_REV_2 0x20
  34. /* I2C controller revisions present on specific hardware */
  35. #define OMAP_I2C_REV_ON_2430 0x00000036
  36. #define OMAP_I2C_REV_ON_3430_3530 0x0000003C
  37. #define OMAP_I2C_REV_ON_3630 0x00000040
  38. #define OMAP_I2C_REV_ON_4430_PLUS 0x50400002
  39. /* timeout waiting for the controller to respond */
  40. #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
  41. /* timeout for pm runtime autosuspend */
  42. #define OMAP_I2C_PM_TIMEOUT 1000 /* ms */
  43. /* timeout for making decision on bus free status */
  44. #define OMAP_I2C_BUS_FREE_TIMEOUT (msecs_to_jiffies(10))
  45. /* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */
  46. enum {
  47. OMAP_I2C_REV_REG = 0,
  48. OMAP_I2C_IE_REG,
  49. OMAP_I2C_STAT_REG,
  50. OMAP_I2C_IV_REG,
  51. OMAP_I2C_WE_REG,
  52. OMAP_I2C_SYSS_REG,
  53. OMAP_I2C_BUF_REG,
  54. OMAP_I2C_CNT_REG,
  55. OMAP_I2C_DATA_REG,
  56. OMAP_I2C_SYSC_REG,
  57. OMAP_I2C_CON_REG,
  58. OMAP_I2C_OA_REG,
  59. OMAP_I2C_SA_REG,
  60. OMAP_I2C_PSC_REG,
  61. OMAP_I2C_SCLL_REG,
  62. OMAP_I2C_SCLH_REG,
  63. OMAP_I2C_SYSTEST_REG,
  64. OMAP_I2C_BUFSTAT_REG,
  65. /* only on OMAP4430 */
  66. OMAP_I2C_IP_V2_REVNB_LO,
  67. OMAP_I2C_IP_V2_REVNB_HI,
  68. OMAP_I2C_IP_V2_IRQSTATUS_RAW,
  69. OMAP_I2C_IP_V2_IRQENABLE_SET,
  70. OMAP_I2C_IP_V2_IRQENABLE_CLR,
  71. };
  72. /* I2C Interrupt Enable Register (OMAP_I2C_IE): */
  73. #define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */
  74. #define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */
  75. #define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */
  76. #define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */
  77. #define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */
  78. #define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */
  79. #define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */
  80. /* I2C Status Register (OMAP_I2C_STAT): */
  81. #define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */
  82. #define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */
  83. #define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */
  84. #define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */
  85. #define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
  86. #define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */
  87. #define OMAP_I2C_STAT_BF (1 << 8) /* Bus Free */
  88. #define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
  89. #define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */
  90. #define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */
  91. #define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */
  92. #define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */
  93. /* I2C WE wakeup enable register */
  94. #define OMAP_I2C_WE_XDR_WE (1 << 14) /* TX drain wakup */
  95. #define OMAP_I2C_WE_RDR_WE (1 << 13) /* RX drain wakeup */
  96. #define OMAP_I2C_WE_AAS_WE (1 << 9) /* Address as slave wakeup*/
  97. #define OMAP_I2C_WE_BF_WE (1 << 8) /* Bus free wakeup */
  98. #define OMAP_I2C_WE_STC_WE (1 << 6) /* Start condition wakeup */
  99. #define OMAP_I2C_WE_GC_WE (1 << 5) /* General call wakeup */
  100. #define OMAP_I2C_WE_DRDY_WE (1 << 3) /* TX/RX data ready wakeup */
  101. #define OMAP_I2C_WE_ARDY_WE (1 << 2) /* Reg access ready wakeup */
  102. #define OMAP_I2C_WE_NACK_WE (1 << 1) /* No acknowledgment wakeup */
  103. #define OMAP_I2C_WE_AL_WE (1 << 0) /* Arbitration lost wakeup */
  104. #define OMAP_I2C_WE_ALL (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \
  105. OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \
  106. OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \
  107. OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \
  108. OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE)
  109. /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
  110. #define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */
  111. #define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */
  112. #define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */
  113. #define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */
  114. /* I2C Configuration Register (OMAP_I2C_CON): */
  115. #define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */
  116. #define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */
  117. #define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */
  118. #define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */
  119. #define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */
  120. #define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */
  121. #define OMAP_I2C_CON_XA (1 << 8) /* Expand address */
  122. #define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */
  123. #define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */
  124. #define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */
  125. /* I2C SCL time value when Master */
  126. #define OMAP_I2C_SCLL_HSSCLL 8
  127. #define OMAP_I2C_SCLH_HSSCLH 8
  128. /* I2C System Test Register (OMAP_I2C_SYSTEST): */
  129. #define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
  130. #define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */
  131. #define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
  132. #define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
  133. /* Functional mode */
  134. #define OMAP_I2C_SYSTEST_SCL_I_FUNC (1 << 8) /* SCL line input value */
  135. #define OMAP_I2C_SYSTEST_SCL_O_FUNC (1 << 7) /* SCL line output value */
  136. #define OMAP_I2C_SYSTEST_SDA_I_FUNC (1 << 6) /* SDA line input value */
  137. #define OMAP_I2C_SYSTEST_SDA_O_FUNC (1 << 5) /* SDA line output value */
  138. /* SDA/SCL IO mode */
  139. #define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */
  140. #define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */
  141. #define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */
  142. #define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */
  143. /* OCP_SYSSTATUS bit definitions */
  144. #define SYSS_RESETDONE_MASK (1 << 0)
  145. /* OCP_SYSCONFIG bit definitions */
  146. #define SYSC_CLOCKACTIVITY_MASK (0x3 << 8)
  147. #define SYSC_SIDLEMODE_MASK (0x3 << 3)
  148. #define SYSC_ENAWAKEUP_MASK (1 << 2)
  149. #define SYSC_SOFTRESET_MASK (1 << 1)
  150. #define SYSC_AUTOIDLE_MASK (1 << 0)
  151. #define SYSC_IDLEMODE_SMART 0x2
  152. #define SYSC_CLOCKACTIVITY_FCLK 0x2
  153. /* Errata definitions */
  154. #define I2C_OMAP_ERRATA_I207 (1 << 0)
  155. #define I2C_OMAP_ERRATA_I462 (1 << 1)
  156. #define OMAP_I2C_IP_V2_INTERRUPTS_MASK 0x6FFF
  157. struct omap_i2c_dev {
  158. struct device *dev;
  159. void __iomem *base; /* virtual */
  160. int irq;
  161. int reg_shift; /* bit shift for I2C register addresses */
  162. struct completion cmd_complete;
  163. struct resource *ioarea;
  164. u32 latency; /* maximum mpu wkup latency */
  165. void (*set_mpu_wkup_lat)(struct device *dev,
  166. long latency);
  167. u32 speed; /* Speed of bus in kHz */
  168. u32 flags;
  169. u16 scheme;
  170. u16 cmd_err;
  171. u8 *buf;
  172. u8 *regs;
  173. size_t buf_len;
  174. struct i2c_adapter adapter;
  175. u8 threshold;
  176. u8 fifo_size; /* use as flag and value
  177. * fifo_size==0 implies no fifo
  178. * if set, should be trsh+1
  179. */
  180. u32 rev;
  181. unsigned b_hw:1; /* bad h/w fixes */
  182. unsigned bb_valid:1; /* true when BB-bit reflects
  183. * the I2C bus state
  184. */
  185. unsigned receiver:1; /* true when we're in receiver mode */
  186. u16 iestate; /* Saved interrupt register */
  187. u16 pscstate;
  188. u16 scllstate;
  189. u16 sclhstate;
  190. u16 syscstate;
  191. u16 westate;
  192. u16 errata;
  193. };
  194. static const u8 reg_map_ip_v1[] = {
  195. [OMAP_I2C_REV_REG] = 0x00,
  196. [OMAP_I2C_IE_REG] = 0x01,
  197. [OMAP_I2C_STAT_REG] = 0x02,
  198. [OMAP_I2C_IV_REG] = 0x03,
  199. [OMAP_I2C_WE_REG] = 0x03,
  200. [OMAP_I2C_SYSS_REG] = 0x04,
  201. [OMAP_I2C_BUF_REG] = 0x05,
  202. [OMAP_I2C_CNT_REG] = 0x06,
  203. [OMAP_I2C_DATA_REG] = 0x07,
  204. [OMAP_I2C_SYSC_REG] = 0x08,
  205. [OMAP_I2C_CON_REG] = 0x09,
  206. [OMAP_I2C_OA_REG] = 0x0a,
  207. [OMAP_I2C_SA_REG] = 0x0b,
  208. [OMAP_I2C_PSC_REG] = 0x0c,
  209. [OMAP_I2C_SCLL_REG] = 0x0d,
  210. [OMAP_I2C_SCLH_REG] = 0x0e,
  211. [OMAP_I2C_SYSTEST_REG] = 0x0f,
  212. [OMAP_I2C_BUFSTAT_REG] = 0x10,
  213. };
  214. static const u8 reg_map_ip_v2[] = {
  215. [OMAP_I2C_REV_REG] = 0x04,
  216. [OMAP_I2C_IE_REG] = 0x2c,
  217. [OMAP_I2C_STAT_REG] = 0x28,
  218. [OMAP_I2C_IV_REG] = 0x34,
  219. [OMAP_I2C_WE_REG] = 0x34,
  220. [OMAP_I2C_SYSS_REG] = 0x90,
  221. [OMAP_I2C_BUF_REG] = 0x94,
  222. [OMAP_I2C_CNT_REG] = 0x98,
  223. [OMAP_I2C_DATA_REG] = 0x9c,
  224. [OMAP_I2C_SYSC_REG] = 0x10,
  225. [OMAP_I2C_CON_REG] = 0xa4,
  226. [OMAP_I2C_OA_REG] = 0xa8,
  227. [OMAP_I2C_SA_REG] = 0xac,
  228. [OMAP_I2C_PSC_REG] = 0xb0,
  229. [OMAP_I2C_SCLL_REG] = 0xb4,
  230. [OMAP_I2C_SCLH_REG] = 0xb8,
  231. [OMAP_I2C_SYSTEST_REG] = 0xbC,
  232. [OMAP_I2C_BUFSTAT_REG] = 0xc0,
  233. [OMAP_I2C_IP_V2_REVNB_LO] = 0x00,
  234. [OMAP_I2C_IP_V2_REVNB_HI] = 0x04,
  235. [OMAP_I2C_IP_V2_IRQSTATUS_RAW] = 0x24,
  236. [OMAP_I2C_IP_V2_IRQENABLE_SET] = 0x2c,
  237. [OMAP_I2C_IP_V2_IRQENABLE_CLR] = 0x30,
  238. };
  239. static int omap_i2c_xfer_data(struct omap_i2c_dev *omap);
  240. static inline void omap_i2c_write_reg(struct omap_i2c_dev *omap,
  241. int reg, u16 val)
  242. {
  243. writew_relaxed(val, omap->base +
  244. (omap->regs[reg] << omap->reg_shift));
  245. }
  246. static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *omap, int reg)
  247. {
  248. return readw_relaxed(omap->base +
  249. (omap->regs[reg] << omap->reg_shift));
  250. }
  251. static void __omap_i2c_init(struct omap_i2c_dev *omap)
  252. {
  253. omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, 0);
  254. /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
  255. omap_i2c_write_reg(omap, OMAP_I2C_PSC_REG, omap->pscstate);
  256. /* SCL low and high time values */
  257. omap_i2c_write_reg(omap, OMAP_I2C_SCLL_REG, omap->scllstate);
  258. omap_i2c_write_reg(omap, OMAP_I2C_SCLH_REG, omap->sclhstate);
  259. if (omap->rev >= OMAP_I2C_REV_ON_3430_3530)
  260. omap_i2c_write_reg(omap, OMAP_I2C_WE_REG, omap->westate);
  261. /* Take the I2C module out of reset: */
  262. omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
  263. /*
  264. * NOTE: right after setting CON_EN, STAT_BB could be 0 while the
  265. * bus is busy. It will be changed to 1 on the next IP FCLK clock.
  266. * udelay(1) will be enough to fix that.
  267. */
  268. /*
  269. * Don't write to this register if the IE state is 0 as it can
  270. * cause deadlock.
  271. */
  272. if (omap->iestate)
  273. omap_i2c_write_reg(omap, OMAP_I2C_IE_REG, omap->iestate);
  274. }
  275. static int omap_i2c_reset(struct omap_i2c_dev *omap)
  276. {
  277. unsigned long timeout;
  278. u16 sysc;
  279. if (omap->rev >= OMAP_I2C_OMAP1_REV_2) {
  280. sysc = omap_i2c_read_reg(omap, OMAP_I2C_SYSC_REG);
  281. /* Disable I2C controller before soft reset */
  282. omap_i2c_write_reg(omap, OMAP_I2C_CON_REG,
  283. omap_i2c_read_reg(omap, OMAP_I2C_CON_REG) &
  284. ~(OMAP_I2C_CON_EN));
  285. omap_i2c_write_reg(omap, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK);
  286. /* For some reason we need to set the EN bit before the
  287. * reset done bit gets set. */
  288. timeout = jiffies + OMAP_I2C_TIMEOUT;
  289. omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
  290. while (!(omap_i2c_read_reg(omap, OMAP_I2C_SYSS_REG) &
  291. SYSS_RESETDONE_MASK)) {
  292. if (time_after(jiffies, timeout)) {
  293. dev_warn(omap->dev, "timeout waiting "
  294. "for controller reset\n");
  295. return -ETIMEDOUT;
  296. }
  297. msleep(1);
  298. }
  299. /* SYSC register is cleared by the reset; rewrite it */
  300. omap_i2c_write_reg(omap, OMAP_I2C_SYSC_REG, sysc);
  301. if (omap->rev > OMAP_I2C_REV_ON_3430_3530) {
  302. /* Schedule I2C-bus monitoring on the next transfer */
  303. omap->bb_valid = 0;
  304. }
  305. }
  306. return 0;
  307. }
  308. static int omap_i2c_init(struct omap_i2c_dev *omap)
  309. {
  310. u16 psc = 0, scll = 0, sclh = 0;
  311. u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
  312. unsigned long fclk_rate = 12000000;
  313. unsigned long internal_clk = 0;
  314. struct clk *fclk;
  315. int error;
  316. if (omap->rev >= OMAP_I2C_REV_ON_3430_3530) {
  317. /*
  318. * Enabling all wakup sources to stop I2C freezing on
  319. * WFI instruction.
  320. * REVISIT: Some wkup sources might not be needed.
  321. */
  322. omap->westate = OMAP_I2C_WE_ALL;
  323. }
  324. if (omap->flags & OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK) {
  325. /*
  326. * The I2C functional clock is the armxor_ck, so there's
  327. * no need to get "armxor_ck" separately. Now, if OMAP2420
  328. * always returns 12MHz for the functional clock, we can
  329. * do this bit unconditionally.
  330. */
  331. fclk = clk_get(omap->dev, "fck");
  332. if (IS_ERR(fclk)) {
  333. error = PTR_ERR(fclk);
  334. dev_err(omap->dev, "could not get fck: %i\n", error);
  335. return error;
  336. }
  337. fclk_rate = clk_get_rate(fclk);
  338. clk_put(fclk);
  339. /* TRM for 5912 says the I2C clock must be prescaled to be
  340. * between 7 - 12 MHz. The XOR input clock is typically
  341. * 12, 13 or 19.2 MHz. So we should have code that produces:
  342. *
  343. * XOR MHz Divider Prescaler
  344. * 12 1 0
  345. * 13 2 1
  346. * 19.2 2 1
  347. */
  348. if (fclk_rate > 12000000)
  349. psc = fclk_rate / 12000000;
  350. }
  351. if (!(omap->flags & OMAP_I2C_FLAG_SIMPLE_CLOCK)) {
  352. /*
  353. * HSI2C controller internal clk rate should be 19.2 Mhz for
  354. * HS and for all modes on 2430. On 34xx we can use lower rate
  355. * to get longer filter period for better noise suppression.
  356. * The filter is iclk (fclk for HS) period.
  357. */
  358. if (omap->speed > 400 ||
  359. omap->flags & OMAP_I2C_FLAG_FORCE_19200_INT_CLK)
  360. internal_clk = 19200;
  361. else if (omap->speed > 100)
  362. internal_clk = 9600;
  363. else
  364. internal_clk = 4000;
  365. fclk = clk_get(omap->dev, "fck");
  366. if (IS_ERR(fclk)) {
  367. error = PTR_ERR(fclk);
  368. dev_err(omap->dev, "could not get fck: %i\n", error);
  369. return error;
  370. }
  371. fclk_rate = clk_get_rate(fclk) / 1000;
  372. clk_put(fclk);
  373. /* Compute prescaler divisor */
  374. psc = fclk_rate / internal_clk;
  375. psc = psc - 1;
  376. /* If configured for High Speed */
  377. if (omap->speed > 400) {
  378. unsigned long scl;
  379. /* For first phase of HS mode */
  380. scl = internal_clk / 400;
  381. fsscll = scl - (scl / 3) - 7;
  382. fssclh = (scl / 3) - 5;
  383. /* For second phase of HS mode */
  384. scl = fclk_rate / omap->speed;
  385. hsscll = scl - (scl / 3) - 7;
  386. hssclh = (scl / 3) - 5;
  387. } else if (omap->speed > 100) {
  388. unsigned long scl;
  389. /* Fast mode */
  390. scl = internal_clk / omap->speed;
  391. fsscll = scl - (scl / 3) - 7;
  392. fssclh = (scl / 3) - 5;
  393. } else {
  394. /* Standard mode */
  395. fsscll = internal_clk / (omap->speed * 2) - 7;
  396. fssclh = internal_clk / (omap->speed * 2) - 5;
  397. }
  398. scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
  399. sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
  400. } else {
  401. /* Program desired operating rate */
  402. fclk_rate /= (psc + 1) * 1000;
  403. if (psc > 2)
  404. psc = 2;
  405. scll = fclk_rate / (omap->speed * 2) - 7 + psc;
  406. sclh = fclk_rate / (omap->speed * 2) - 7 + psc;
  407. }
  408. omap->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
  409. OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
  410. OMAP_I2C_IE_AL) | ((omap->fifo_size) ?
  411. (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0);
  412. omap->pscstate = psc;
  413. omap->scllstate = scll;
  414. omap->sclhstate = sclh;
  415. if (omap->rev <= OMAP_I2C_REV_ON_3430_3530) {
  416. /* Not implemented */
  417. omap->bb_valid = 1;
  418. }
  419. __omap_i2c_init(omap);
  420. return 0;
  421. }
  422. /*
  423. * Try bus recovery, but only if SDA is actually low.
  424. */
  425. static int omap_i2c_recover_bus(struct omap_i2c_dev *omap)
  426. {
  427. u16 systest;
  428. systest = omap_i2c_read_reg(omap, OMAP_I2C_SYSTEST_REG);
  429. if ((systest & OMAP_I2C_SYSTEST_SCL_I_FUNC) &&
  430. (systest & OMAP_I2C_SYSTEST_SDA_I_FUNC))
  431. return 0; /* bus seems to already be fine */
  432. if (!(systest & OMAP_I2C_SYSTEST_SCL_I_FUNC))
  433. return -EBUSY; /* recovery would not fix SCL */
  434. return i2c_recover_bus(&omap->adapter);
  435. }
  436. /*
  437. * Waiting on Bus Busy
  438. */
  439. static int omap_i2c_wait_for_bb(struct omap_i2c_dev *omap)
  440. {
  441. unsigned long timeout;
  442. timeout = jiffies + OMAP_I2C_TIMEOUT;
  443. while (omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
  444. if (time_after(jiffies, timeout))
  445. return omap_i2c_recover_bus(omap);
  446. msleep(1);
  447. }
  448. return 0;
  449. }
  450. /*
  451. * Wait while BB-bit doesn't reflect the I2C bus state
  452. *
  453. * In a multimaster environment, after IP software reset, BB-bit value doesn't
  454. * correspond to the current bus state. It may happen what BB-bit will be 0,
  455. * while the bus is busy due to another I2C master activity.
  456. * Here are BB-bit values after reset:
  457. * SDA SCL BB NOTES
  458. * 0 0 0 1, 2
  459. * 1 0 0 1, 2
  460. * 0 1 1
  461. * 1 1 0 3
  462. * Later, if IP detect SDA=0 and SCL=1 (ACK) or SDA 1->0 while SCL=1 (START)
  463. * combinations on the bus, it set BB-bit to 1.
  464. * If IP detect SDA 0->1 while SCL=1 (STOP) combination on the bus,
  465. * it set BB-bit to 0 and BF to 1.
  466. * BB and BF bits correctly tracks the bus state while IP is suspended
  467. * BB bit became valid on the next FCLK clock after CON_EN bit set
  468. *
  469. * NOTES:
  470. * 1. Any transfer started when BB=0 and bus is busy wouldn't be
  471. * completed by IP and results in controller timeout.
  472. * 2. Any transfer started when BB=0 and SCL=0 results in IP
  473. * starting to drive SDA low. In that case IP corrupt data
  474. * on the bus.
  475. * 3. Any transfer started in the middle of another master's transfer
  476. * results in unpredictable results and data corruption
  477. */
  478. static int omap_i2c_wait_for_bb_valid(struct omap_i2c_dev *omap)
  479. {
  480. unsigned long bus_free_timeout = 0;
  481. unsigned long timeout;
  482. int bus_free = 0;
  483. u16 stat, systest;
  484. if (omap->bb_valid)
  485. return 0;
  486. timeout = jiffies + OMAP_I2C_TIMEOUT;
  487. while (1) {
  488. stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);
  489. /*
  490. * We will see BB or BF event in a case IP had detected any
  491. * activity on the I2C bus. Now IP correctly tracks the bus
  492. * state. BB-bit value is valid.
  493. */
  494. if (stat & (OMAP_I2C_STAT_BB | OMAP_I2C_STAT_BF))
  495. break;
  496. /*
  497. * Otherwise, we must look signals on the bus to make
  498. * the right decision.
  499. */
  500. systest = omap_i2c_read_reg(omap, OMAP_I2C_SYSTEST_REG);
  501. if ((systest & OMAP_I2C_SYSTEST_SCL_I_FUNC) &&
  502. (systest & OMAP_I2C_SYSTEST_SDA_I_FUNC)) {
  503. if (!bus_free) {
  504. bus_free_timeout = jiffies +
  505. OMAP_I2C_BUS_FREE_TIMEOUT;
  506. bus_free = 1;
  507. }
  508. /*
  509. * SDA and SCL lines was high for 10 ms without bus
  510. * activity detected. The bus is free. Consider
  511. * BB-bit value is valid.
  512. */
  513. if (time_after(jiffies, bus_free_timeout))
  514. break;
  515. } else {
  516. bus_free = 0;
  517. }
  518. if (time_after(jiffies, timeout)) {
  519. /*
  520. * SDA or SCL were low for the entire timeout without
  521. * any activity detected. Most likely, a slave is
  522. * locking up the bus with no master driving the clock.
  523. */
  524. dev_warn(omap->dev, "timeout waiting for bus ready\n");
  525. return omap_i2c_recover_bus(omap);
  526. }
  527. msleep(1);
  528. }
  529. omap->bb_valid = 1;
  530. return 0;
  531. }
  532. static void omap_i2c_resize_fifo(struct omap_i2c_dev *omap, u8 size, bool is_rx)
  533. {
  534. u16 buf;
  535. if (omap->flags & OMAP_I2C_FLAG_NO_FIFO)
  536. return;
  537. /*
  538. * Set up notification threshold based on message size. We're doing
  539. * this to try and avoid draining feature as much as possible. Whenever
  540. * we have big messages to transfer (bigger than our total fifo size)
  541. * then we might use draining feature to transfer the remaining bytes.
  542. */
  543. omap->threshold = clamp(size, (u8) 1, omap->fifo_size);
  544. buf = omap_i2c_read_reg(omap, OMAP_I2C_BUF_REG);
  545. if (is_rx) {
  546. /* Clear RX Threshold */
  547. buf &= ~(0x3f << 8);
  548. buf |= ((omap->threshold - 1) << 8) | OMAP_I2C_BUF_RXFIF_CLR;
  549. } else {
  550. /* Clear TX Threshold */
  551. buf &= ~0x3f;
  552. buf |= (omap->threshold - 1) | OMAP_I2C_BUF_TXFIF_CLR;
  553. }
  554. omap_i2c_write_reg(omap, OMAP_I2C_BUF_REG, buf);
  555. if (omap->rev < OMAP_I2C_REV_ON_3630)
  556. omap->b_hw = 1; /* Enable hardware fixes */
  557. /* calculate wakeup latency constraint for MPU */
  558. if (omap->set_mpu_wkup_lat != NULL)
  559. omap->latency = (1000000 * omap->threshold) /
  560. (1000 * omap->speed / 8);
  561. }
  562. static void omap_i2c_wait(struct omap_i2c_dev *omap)
  563. {
  564. u16 stat;
  565. u16 mask = omap_i2c_read_reg(omap, OMAP_I2C_IE_REG);
  566. int count = 0;
  567. do {
  568. stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);
  569. count++;
  570. } while (!(stat & mask) && count < 5);
  571. }
  572. /*
  573. * Low level master read/write transaction.
  574. */
  575. static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
  576. struct i2c_msg *msg, int stop, bool polling)
  577. {
  578. struct omap_i2c_dev *omap = i2c_get_adapdata(adap);
  579. unsigned long timeout;
  580. u16 w;
  581. int ret;
  582. dev_dbg(omap->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
  583. msg->addr, msg->len, msg->flags, stop);
  584. omap->receiver = !!(msg->flags & I2C_M_RD);
  585. omap_i2c_resize_fifo(omap, msg->len, omap->receiver);
  586. omap_i2c_write_reg(omap, OMAP_I2C_SA_REG, msg->addr);
  587. /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
  588. omap->buf = msg->buf;
  589. omap->buf_len = msg->len;
  590. /* make sure writes to omap->buf_len are ordered */
  591. barrier();
  592. omap_i2c_write_reg(omap, OMAP_I2C_CNT_REG, omap->buf_len);
  593. /* Clear the FIFO Buffers */
  594. w = omap_i2c_read_reg(omap, OMAP_I2C_BUF_REG);
  595. w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
  596. omap_i2c_write_reg(omap, OMAP_I2C_BUF_REG, w);
  597. if (!polling)
  598. reinit_completion(&omap->cmd_complete);
  599. omap->cmd_err = 0;
  600. w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
  601. /* High speed configuration */
  602. if (omap->speed > 400)
  603. w |= OMAP_I2C_CON_OPMODE_HS;
  604. if (msg->flags & I2C_M_STOP)
  605. stop = 1;
  606. if (msg->flags & I2C_M_TEN)
  607. w |= OMAP_I2C_CON_XA;
  608. if (!(msg->flags & I2C_M_RD))
  609. w |= OMAP_I2C_CON_TRX;
  610. if (!omap->b_hw && stop)
  611. w |= OMAP_I2C_CON_STP;
  612. /*
  613. * NOTE: STAT_BB bit could became 1 here if another master occupy
  614. * the bus. IP successfully complete transfer when the bus will be
  615. * free again (BB reset to 0).
  616. */
  617. omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, w);
  618. /*
  619. * Don't write stt and stp together on some hardware.
  620. */
  621. if (omap->b_hw && stop) {
  622. unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
  623. u16 con = omap_i2c_read_reg(omap, OMAP_I2C_CON_REG);
  624. while (con & OMAP_I2C_CON_STT) {
  625. con = omap_i2c_read_reg(omap, OMAP_I2C_CON_REG);
  626. /* Let the user know if i2c is in a bad state */
  627. if (time_after(jiffies, delay)) {
  628. dev_err(omap->dev, "controller timed out "
  629. "waiting for start condition to finish\n");
  630. return -ETIMEDOUT;
  631. }
  632. cpu_relax();
  633. }
  634. w |= OMAP_I2C_CON_STP;
  635. w &= ~OMAP_I2C_CON_STT;
  636. omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, w);
  637. }
  638. /*
  639. * REVISIT: We should abort the transfer on signals, but the bus goes
  640. * into arbitration and we're currently unable to recover from it.
  641. */
  642. if (!polling) {
  643. timeout = wait_for_completion_timeout(&omap->cmd_complete,
  644. OMAP_I2C_TIMEOUT);
  645. } else {
  646. do {
  647. omap_i2c_wait(omap);
  648. ret = omap_i2c_xfer_data(omap);
  649. } while (ret == -EAGAIN);
  650. timeout = !ret;
  651. }
  652. if (timeout == 0) {
  653. dev_err(omap->dev, "controller timed out\n");
  654. omap_i2c_reset(omap);
  655. __omap_i2c_init(omap);
  656. return -ETIMEDOUT;
  657. }
  658. if (likely(!omap->cmd_err))
  659. return 0;
  660. /* We have an error */
  661. if (omap->cmd_err & (OMAP_I2C_STAT_ROVR | OMAP_I2C_STAT_XUDF)) {
  662. omap_i2c_reset(omap);
  663. __omap_i2c_init(omap);
  664. return -EIO;
  665. }
  666. if (omap->cmd_err & OMAP_I2C_STAT_AL)
  667. return -EAGAIN;
  668. if (omap->cmd_err & OMAP_I2C_STAT_NACK) {
  669. if (msg->flags & I2C_M_IGNORE_NAK)
  670. return 0;
  671. w = omap_i2c_read_reg(omap, OMAP_I2C_CON_REG);
  672. w |= OMAP_I2C_CON_STP;
  673. omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, w);
  674. return -EREMOTEIO;
  675. }
  676. return -EIO;
  677. }
  678. /*
  679. * Prepare controller for a transaction and call omap_i2c_xfer_msg
  680. * to do the work during IRQ processing.
  681. */
  682. static int
  683. omap_i2c_xfer_common(struct i2c_adapter *adap, struct i2c_msg msgs[], int num,
  684. bool polling)
  685. {
  686. struct omap_i2c_dev *omap = i2c_get_adapdata(adap);
  687. int i;
  688. int r;
  689. r = pm_runtime_get_sync(omap->dev);
  690. if (r < 0)
  691. goto out;
  692. r = omap_i2c_wait_for_bb_valid(omap);
  693. if (r < 0)
  694. goto out;
  695. r = omap_i2c_wait_for_bb(omap);
  696. if (r < 0)
  697. goto out;
  698. if (omap->set_mpu_wkup_lat != NULL)
  699. omap->set_mpu_wkup_lat(omap->dev, omap->latency);
  700. for (i = 0; i < num; i++) {
  701. r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)),
  702. polling);
  703. if (r != 0)
  704. break;
  705. }
  706. if (r == 0)
  707. r = num;
  708. omap_i2c_wait_for_bb(omap);
  709. if (omap->set_mpu_wkup_lat != NULL)
  710. omap->set_mpu_wkup_lat(omap->dev, -1);
  711. out:
  712. pm_runtime_mark_last_busy(omap->dev);
  713. pm_runtime_put_autosuspend(omap->dev);
  714. return r;
  715. }
  716. static int
  717. omap_i2c_xfer_irq(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
  718. {
  719. return omap_i2c_xfer_common(adap, msgs, num, false);
  720. }
  721. static int
  722. omap_i2c_xfer_polling(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
  723. {
  724. return omap_i2c_xfer_common(adap, msgs, num, true);
  725. }
  726. static u32
  727. omap_i2c_func(struct i2c_adapter *adap)
  728. {
  729. return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
  730. I2C_FUNC_PROTOCOL_MANGLING;
  731. }
  732. static inline void
  733. omap_i2c_complete_cmd(struct omap_i2c_dev *omap, u16 err)
  734. {
  735. omap->cmd_err |= err;
  736. complete(&omap->cmd_complete);
  737. }
  738. static inline void
  739. omap_i2c_ack_stat(struct omap_i2c_dev *omap, u16 stat)
  740. {
  741. omap_i2c_write_reg(omap, OMAP_I2C_STAT_REG, stat);
  742. }
  743. static inline void i2c_omap_errata_i207(struct omap_i2c_dev *omap, u16 stat)
  744. {
  745. /*
  746. * I2C Errata(Errata Nos. OMAP2: 1.67, OMAP3: 1.8)
  747. * Not applicable for OMAP4.
  748. * Under certain rare conditions, RDR could be set again
  749. * when the bus is busy, then ignore the interrupt and
  750. * clear the interrupt.
  751. */
  752. if (stat & OMAP_I2C_STAT_RDR) {
  753. /* Step 1: If RDR is set, clear it */
  754. omap_i2c_ack_stat(omap, OMAP_I2C_STAT_RDR);
  755. /* Step 2: */
  756. if (!(omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG)
  757. & OMAP_I2C_STAT_BB)) {
  758. /* Step 3: */
  759. if (omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG)
  760. & OMAP_I2C_STAT_RDR) {
  761. omap_i2c_ack_stat(omap, OMAP_I2C_STAT_RDR);
  762. dev_dbg(omap->dev, "RDR when bus is busy.\n");
  763. }
  764. }
  765. }
  766. }
  767. /* rev1 devices are apparently only on some 15xx */
  768. #ifdef CONFIG_ARCH_OMAP15XX
  769. static irqreturn_t
  770. omap_i2c_omap1_isr(int this_irq, void *dev_id)
  771. {
  772. struct omap_i2c_dev *omap = dev_id;
  773. u16 iv, w;
  774. if (pm_runtime_suspended(omap->dev))
  775. return IRQ_NONE;
  776. iv = omap_i2c_read_reg(omap, OMAP_I2C_IV_REG);
  777. switch (iv) {
  778. case 0x00: /* None */
  779. break;
  780. case 0x01: /* Arbitration lost */
  781. dev_err(omap->dev, "Arbitration lost\n");
  782. omap_i2c_complete_cmd(omap, OMAP_I2C_STAT_AL);
  783. break;
  784. case 0x02: /* No acknowledgement */
  785. omap_i2c_complete_cmd(omap, OMAP_I2C_STAT_NACK);
  786. omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
  787. break;
  788. case 0x03: /* Register access ready */
  789. omap_i2c_complete_cmd(omap, 0);
  790. break;
  791. case 0x04: /* Receive data ready */
  792. if (omap->buf_len) {
  793. w = omap_i2c_read_reg(omap, OMAP_I2C_DATA_REG);
  794. *omap->buf++ = w;
  795. omap->buf_len--;
  796. if (omap->buf_len) {
  797. *omap->buf++ = w >> 8;
  798. omap->buf_len--;
  799. }
  800. } else
  801. dev_err(omap->dev, "RRDY IRQ while no data requested\n");
  802. break;
  803. case 0x05: /* Transmit data ready */
  804. if (omap->buf_len) {
  805. w = *omap->buf++;
  806. omap->buf_len--;
  807. if (omap->buf_len) {
  808. w |= *omap->buf++ << 8;
  809. omap->buf_len--;
  810. }
  811. omap_i2c_write_reg(omap, OMAP_I2C_DATA_REG, w);
  812. } else
  813. dev_err(omap->dev, "XRDY IRQ while no data to send\n");
  814. break;
  815. default:
  816. return IRQ_NONE;
  817. }
  818. return IRQ_HANDLED;
  819. }
  820. #else
  821. #define omap_i2c_omap1_isr NULL
  822. #endif
  823. /*
  824. * OMAP3430 Errata i462: When an XRDY/XDR is hit, wait for XUDF before writing
  825. * data to DATA_REG. Otherwise some data bytes can be lost while transferring
  826. * them from the memory to the I2C interface.
  827. */
  828. static int errata_omap3_i462(struct omap_i2c_dev *omap)
  829. {
  830. unsigned long timeout = 10000;
  831. u16 stat;
  832. do {
  833. stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);
  834. if (stat & OMAP_I2C_STAT_XUDF)
  835. break;
  836. if (stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
  837. omap_i2c_ack_stat(omap, (OMAP_I2C_STAT_XRDY |
  838. OMAP_I2C_STAT_XDR));
  839. if (stat & OMAP_I2C_STAT_NACK) {
  840. omap->cmd_err |= OMAP_I2C_STAT_NACK;
  841. omap_i2c_ack_stat(omap, OMAP_I2C_STAT_NACK);
  842. }
  843. if (stat & OMAP_I2C_STAT_AL) {
  844. dev_err(omap->dev, "Arbitration lost\n");
  845. omap->cmd_err |= OMAP_I2C_STAT_AL;
  846. omap_i2c_ack_stat(omap, OMAP_I2C_STAT_AL);
  847. }
  848. return -EIO;
  849. }
  850. cpu_relax();
  851. } while (--timeout);
  852. if (!timeout) {
  853. dev_err(omap->dev, "timeout waiting on XUDF bit\n");
  854. return 0;
  855. }
  856. return 0;
  857. }
  858. static void omap_i2c_receive_data(struct omap_i2c_dev *omap, u8 num_bytes,
  859. bool is_rdr)
  860. {
  861. u16 w;
  862. while (num_bytes--) {
  863. w = omap_i2c_read_reg(omap, OMAP_I2C_DATA_REG);
  864. *omap->buf++ = w;
  865. omap->buf_len--;
  866. /*
  867. * Data reg in 2430, omap3 and
  868. * omap4 is 8 bit wide
  869. */
  870. if (omap->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
  871. *omap->buf++ = w >> 8;
  872. omap->buf_len--;
  873. }
  874. }
  875. }
  876. static int omap_i2c_transmit_data(struct omap_i2c_dev *omap, u8 num_bytes,
  877. bool is_xdr)
  878. {
  879. u16 w;
  880. while (num_bytes--) {
  881. w = *omap->buf++;
  882. omap->buf_len--;
  883. /*
  884. * Data reg in 2430, omap3 and
  885. * omap4 is 8 bit wide
  886. */
  887. if (omap->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
  888. w |= *omap->buf++ << 8;
  889. omap->buf_len--;
  890. }
  891. if (omap->errata & I2C_OMAP_ERRATA_I462) {
  892. int ret;
  893. ret = errata_omap3_i462(omap);
  894. if (ret < 0)
  895. return ret;
  896. }
  897. omap_i2c_write_reg(omap, OMAP_I2C_DATA_REG, w);
  898. }
  899. return 0;
  900. }
  901. static irqreturn_t
  902. omap_i2c_isr(int irq, void *dev_id)
  903. {
  904. struct omap_i2c_dev *omap = dev_id;
  905. irqreturn_t ret = IRQ_HANDLED;
  906. u16 mask;
  907. u16 stat;
  908. stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);
  909. mask = omap_i2c_read_reg(omap, OMAP_I2C_IE_REG);
  910. if (stat & mask)
  911. ret = IRQ_WAKE_THREAD;
  912. return ret;
  913. }
  914. static int omap_i2c_xfer_data(struct omap_i2c_dev *omap)
  915. {
  916. u16 bits;
  917. u16 stat;
  918. int err = 0, count = 0;
  919. do {
  920. bits = omap_i2c_read_reg(omap, OMAP_I2C_IE_REG);
  921. stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);
  922. stat &= bits;
  923. /* If we're in receiver mode, ignore XDR/XRDY */
  924. if (omap->receiver)
  925. stat &= ~(OMAP_I2C_STAT_XDR | OMAP_I2C_STAT_XRDY);
  926. else
  927. stat &= ~(OMAP_I2C_STAT_RDR | OMAP_I2C_STAT_RRDY);
  928. if (!stat) {
  929. /* my work here is done */
  930. err = -EAGAIN;
  931. break;
  932. }
  933. dev_dbg(omap->dev, "IRQ (ISR = 0x%04x)\n", stat);
  934. if (count++ == 100) {
  935. dev_warn(omap->dev, "Too much work in one IRQ\n");
  936. break;
  937. }
  938. if (stat & OMAP_I2C_STAT_NACK) {
  939. err |= OMAP_I2C_STAT_NACK;
  940. omap_i2c_ack_stat(omap, OMAP_I2C_STAT_NACK);
  941. }
  942. if (stat & OMAP_I2C_STAT_AL) {
  943. dev_err(omap->dev, "Arbitration lost\n");
  944. err |= OMAP_I2C_STAT_AL;
  945. omap_i2c_ack_stat(omap, OMAP_I2C_STAT_AL);
  946. }
  947. /*
  948. * ProDB0017052: Clear ARDY bit twice
  949. */
  950. if (stat & OMAP_I2C_STAT_ARDY)
  951. omap_i2c_ack_stat(omap, OMAP_I2C_STAT_ARDY);
  952. if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
  953. OMAP_I2C_STAT_AL)) {
  954. omap_i2c_ack_stat(omap, (OMAP_I2C_STAT_RRDY |
  955. OMAP_I2C_STAT_RDR |
  956. OMAP_I2C_STAT_XRDY |
  957. OMAP_I2C_STAT_XDR |
  958. OMAP_I2C_STAT_ARDY));
  959. break;
  960. }
  961. if (stat & OMAP_I2C_STAT_RDR) {
  962. u8 num_bytes = 1;
  963. if (omap->fifo_size)
  964. num_bytes = omap->buf_len;
  965. if (omap->errata & I2C_OMAP_ERRATA_I207) {
  966. i2c_omap_errata_i207(omap, stat);
  967. num_bytes = (omap_i2c_read_reg(omap,
  968. OMAP_I2C_BUFSTAT_REG) >> 8) & 0x3F;
  969. }
  970. omap_i2c_receive_data(omap, num_bytes, true);
  971. omap_i2c_ack_stat(omap, OMAP_I2C_STAT_RDR);
  972. continue;
  973. }
  974. if (stat & OMAP_I2C_STAT_RRDY) {
  975. u8 num_bytes = 1;
  976. if (omap->threshold)
  977. num_bytes = omap->threshold;
  978. omap_i2c_receive_data(omap, num_bytes, false);
  979. omap_i2c_ack_stat(omap, OMAP_I2C_STAT_RRDY);
  980. continue;
  981. }
  982. if (stat & OMAP_I2C_STAT_XDR) {
  983. u8 num_bytes = 1;
  984. int ret;
  985. if (omap->fifo_size)
  986. num_bytes = omap->buf_len;
  987. ret = omap_i2c_transmit_data(omap, num_bytes, true);
  988. if (ret < 0)
  989. break;
  990. omap_i2c_ack_stat(omap, OMAP_I2C_STAT_XDR);
  991. continue;
  992. }
  993. if (stat & OMAP_I2C_STAT_XRDY) {
  994. u8 num_bytes = 1;
  995. int ret;
  996. if (omap->threshold)
  997. num_bytes = omap->threshold;
  998. ret = omap_i2c_transmit_data(omap, num_bytes, false);
  999. if (ret < 0)
  1000. break;
  1001. omap_i2c_ack_stat(omap, OMAP_I2C_STAT_XRDY);
  1002. continue;
  1003. }
  1004. if (stat & OMAP_I2C_STAT_ROVR) {
  1005. dev_err(omap->dev, "Receive overrun\n");
  1006. err |= OMAP_I2C_STAT_ROVR;
  1007. omap_i2c_ack_stat(omap, OMAP_I2C_STAT_ROVR);
  1008. break;
  1009. }
  1010. if (stat & OMAP_I2C_STAT_XUDF) {
  1011. dev_err(omap->dev, "Transmit underflow\n");
  1012. err |= OMAP_I2C_STAT_XUDF;
  1013. omap_i2c_ack_stat(omap, OMAP_I2C_STAT_XUDF);
  1014. break;
  1015. }
  1016. } while (stat);
  1017. return err;
  1018. }
  1019. static irqreturn_t
  1020. omap_i2c_isr_thread(int this_irq, void *dev_id)
  1021. {
  1022. int ret;
  1023. struct omap_i2c_dev *omap = dev_id;
  1024. ret = omap_i2c_xfer_data(omap);
  1025. if (ret != -EAGAIN)
  1026. omap_i2c_complete_cmd(omap, ret);
  1027. return IRQ_HANDLED;
  1028. }
  1029. static const struct i2c_algorithm omap_i2c_algo = {
  1030. .master_xfer = omap_i2c_xfer_irq,
  1031. .master_xfer_atomic = omap_i2c_xfer_polling,
  1032. .functionality = omap_i2c_func,
  1033. };
  1034. static const struct i2c_adapter_quirks omap_i2c_quirks = {
  1035. .flags = I2C_AQ_NO_ZERO_LEN,
  1036. };
  1037. #ifdef CONFIG_OF
  1038. static struct omap_i2c_bus_platform_data omap2420_pdata = {
  1039. .rev = OMAP_I2C_IP_VERSION_1,
  1040. .flags = OMAP_I2C_FLAG_NO_FIFO |
  1041. OMAP_I2C_FLAG_SIMPLE_CLOCK |
  1042. OMAP_I2C_FLAG_16BIT_DATA_REG |
  1043. OMAP_I2C_FLAG_BUS_SHIFT_2,
  1044. };
  1045. static struct omap_i2c_bus_platform_data omap2430_pdata = {
  1046. .rev = OMAP_I2C_IP_VERSION_1,
  1047. .flags = OMAP_I2C_FLAG_BUS_SHIFT_2 |
  1048. OMAP_I2C_FLAG_FORCE_19200_INT_CLK,
  1049. };
  1050. static struct omap_i2c_bus_platform_data omap3_pdata = {
  1051. .rev = OMAP_I2C_IP_VERSION_1,
  1052. .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
  1053. };
  1054. static struct omap_i2c_bus_platform_data omap4_pdata = {
  1055. .rev = OMAP_I2C_IP_VERSION_2,
  1056. };
  1057. static const struct of_device_id omap_i2c_of_match[] = {
  1058. {
  1059. .compatible = "ti,omap4-i2c",
  1060. .data = &omap4_pdata,
  1061. },
  1062. {
  1063. .compatible = "ti,omap3-i2c",
  1064. .data = &omap3_pdata,
  1065. },
  1066. {
  1067. .compatible = "ti,omap2430-i2c",
  1068. .data = &omap2430_pdata,
  1069. },
  1070. {
  1071. .compatible = "ti,omap2420-i2c",
  1072. .data = &omap2420_pdata,
  1073. },
  1074. { },
  1075. };
  1076. MODULE_DEVICE_TABLE(of, omap_i2c_of_match);
  1077. #endif
  1078. #define OMAP_I2C_SCHEME(rev) ((rev & 0xc000) >> 14)
  1079. #define OMAP_I2C_REV_SCHEME_0_MAJOR(rev) (rev >> 4)
  1080. #define OMAP_I2C_REV_SCHEME_0_MINOR(rev) (rev & 0xf)
  1081. #define OMAP_I2C_REV_SCHEME_1_MAJOR(rev) ((rev & 0x0700) >> 7)
  1082. #define OMAP_I2C_REV_SCHEME_1_MINOR(rev) (rev & 0x1f)
  1083. #define OMAP_I2C_SCHEME_0 0
  1084. #define OMAP_I2C_SCHEME_1 1
  1085. static int omap_i2c_get_scl(struct i2c_adapter *adap)
  1086. {
  1087. struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
  1088. u32 reg;
  1089. reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
  1090. return reg & OMAP_I2C_SYSTEST_SCL_I_FUNC;
  1091. }
  1092. static int omap_i2c_get_sda(struct i2c_adapter *adap)
  1093. {
  1094. struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
  1095. u32 reg;
  1096. reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
  1097. return reg & OMAP_I2C_SYSTEST_SDA_I_FUNC;
  1098. }
  1099. static void omap_i2c_set_scl(struct i2c_adapter *adap, int val)
  1100. {
  1101. struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
  1102. u32 reg;
  1103. reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
  1104. if (val)
  1105. reg |= OMAP_I2C_SYSTEST_SCL_O;
  1106. else
  1107. reg &= ~OMAP_I2C_SYSTEST_SCL_O;
  1108. omap_i2c_write_reg(dev, OMAP_I2C_SYSTEST_REG, reg);
  1109. }
  1110. static void omap_i2c_prepare_recovery(struct i2c_adapter *adap)
  1111. {
  1112. struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
  1113. u32 reg;
  1114. reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
  1115. /* enable test mode */
  1116. reg |= OMAP_I2C_SYSTEST_ST_EN;
  1117. /* select SDA/SCL IO mode */
  1118. reg |= 3 << OMAP_I2C_SYSTEST_TMODE_SHIFT;
  1119. /* set SCL to high-impedance state (reset value is 0) */
  1120. reg |= OMAP_I2C_SYSTEST_SCL_O;
  1121. /* set SDA to high-impedance state (reset value is 0) */
  1122. reg |= OMAP_I2C_SYSTEST_SDA_O;
  1123. omap_i2c_write_reg(dev, OMAP_I2C_SYSTEST_REG, reg);
  1124. }
  1125. static void omap_i2c_unprepare_recovery(struct i2c_adapter *adap)
  1126. {
  1127. struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
  1128. u32 reg;
  1129. reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
  1130. /* restore reset values */
  1131. reg &= ~OMAP_I2C_SYSTEST_ST_EN;
  1132. reg &= ~OMAP_I2C_SYSTEST_TMODE_MASK;
  1133. reg &= ~OMAP_I2C_SYSTEST_SCL_O;
  1134. reg &= ~OMAP_I2C_SYSTEST_SDA_O;
  1135. omap_i2c_write_reg(dev, OMAP_I2C_SYSTEST_REG, reg);
  1136. }
  1137. static struct i2c_bus_recovery_info omap_i2c_bus_recovery_info = {
  1138. .get_scl = omap_i2c_get_scl,
  1139. .get_sda = omap_i2c_get_sda,
  1140. .set_scl = omap_i2c_set_scl,
  1141. .prepare_recovery = omap_i2c_prepare_recovery,
  1142. .unprepare_recovery = omap_i2c_unprepare_recovery,
  1143. .recover_bus = i2c_generic_scl_recovery,
  1144. };
  1145. static int
  1146. omap_i2c_probe(struct platform_device *pdev)
  1147. {
  1148. struct omap_i2c_dev *omap;
  1149. struct i2c_adapter *adap;
  1150. const struct omap_i2c_bus_platform_data *pdata =
  1151. dev_get_platdata(&pdev->dev);
  1152. struct device_node *node = pdev->dev.of_node;
  1153. const struct of_device_id *match;
  1154. int irq;
  1155. int r;
  1156. u32 rev;
  1157. u16 minor, major;
  1158. irq = platform_get_irq(pdev, 0);
  1159. if (irq < 0) {
  1160. dev_err(&pdev->dev, "no irq resource?\n");
  1161. return irq;
  1162. }
  1163. omap = devm_kzalloc(&pdev->dev, sizeof(struct omap_i2c_dev), GFP_KERNEL);
  1164. if (!omap)
  1165. return -ENOMEM;
  1166. omap->base = devm_platform_ioremap_resource(pdev, 0);
  1167. if (IS_ERR(omap->base))
  1168. return PTR_ERR(omap->base);
  1169. match = of_match_device(of_match_ptr(omap_i2c_of_match), &pdev->dev);
  1170. if (match) {
  1171. u32 freq = I2C_MAX_STANDARD_MODE_FREQ;
  1172. pdata = match->data;
  1173. omap->flags = pdata->flags;
  1174. of_property_read_u32(node, "clock-frequency", &freq);
  1175. /* convert DT freq value in Hz into kHz for speed */
  1176. omap->speed = freq / 1000;
  1177. } else if (pdata != NULL) {
  1178. omap->speed = pdata->clkrate;
  1179. omap->flags = pdata->flags;
  1180. omap->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat;
  1181. }
  1182. omap->dev = &pdev->dev;
  1183. omap->irq = irq;
  1184. platform_set_drvdata(pdev, omap);
  1185. init_completion(&omap->cmd_complete);
  1186. omap->reg_shift = (omap->flags >> OMAP_I2C_FLAG_BUS_SHIFT__SHIFT) & 3;
  1187. pm_runtime_enable(omap->dev);
  1188. pm_runtime_set_autosuspend_delay(omap->dev, OMAP_I2C_PM_TIMEOUT);
  1189. pm_runtime_use_autosuspend(omap->dev);
  1190. r = pm_runtime_get_sync(omap->dev);
  1191. if (r < 0)
  1192. goto err_free_mem;
  1193. /*
  1194. * Read the Rev hi bit-[15:14] ie scheme this is 1 indicates ver2.
  1195. * On omap1/3/2 Offset 4 is IE Reg the bit [15:14] is 0 at reset.
  1196. * Also since the omap_i2c_read_reg uses reg_map_ip_* a
  1197. * readw_relaxed is done.
  1198. */
  1199. rev = readw_relaxed(omap->base + 0x04);
  1200. omap->scheme = OMAP_I2C_SCHEME(rev);
  1201. switch (omap->scheme) {
  1202. case OMAP_I2C_SCHEME_0:
  1203. omap->regs = (u8 *)reg_map_ip_v1;
  1204. omap->rev = omap_i2c_read_reg(omap, OMAP_I2C_REV_REG);
  1205. minor = OMAP_I2C_REV_SCHEME_0_MAJOR(omap->rev);
  1206. major = OMAP_I2C_REV_SCHEME_0_MAJOR(omap->rev);
  1207. break;
  1208. case OMAP_I2C_SCHEME_1:
  1209. /* FALLTHROUGH */
  1210. default:
  1211. omap->regs = (u8 *)reg_map_ip_v2;
  1212. rev = (rev << 16) |
  1213. omap_i2c_read_reg(omap, OMAP_I2C_IP_V2_REVNB_LO);
  1214. minor = OMAP_I2C_REV_SCHEME_1_MINOR(rev);
  1215. major = OMAP_I2C_REV_SCHEME_1_MAJOR(rev);
  1216. omap->rev = rev;
  1217. }
  1218. omap->errata = 0;
  1219. if (omap->rev >= OMAP_I2C_REV_ON_2430 &&
  1220. omap->rev < OMAP_I2C_REV_ON_4430_PLUS)
  1221. omap->errata |= I2C_OMAP_ERRATA_I207;
  1222. if (omap->rev <= OMAP_I2C_REV_ON_3430_3530)
  1223. omap->errata |= I2C_OMAP_ERRATA_I462;
  1224. if (!(omap->flags & OMAP_I2C_FLAG_NO_FIFO)) {
  1225. u16 s;
  1226. /* Set up the fifo size - Get total size */
  1227. s = (omap_i2c_read_reg(omap, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
  1228. omap->fifo_size = 0x8 << s;
  1229. /*
  1230. * Set up notification threshold as half the total available
  1231. * size. This is to ensure that we can handle the status on int
  1232. * call back latencies.
  1233. */
  1234. omap->fifo_size = (omap->fifo_size / 2);
  1235. if (omap->rev < OMAP_I2C_REV_ON_3630)
  1236. omap->b_hw = 1; /* Enable hardware fixes */
  1237. /* calculate wakeup latency constraint for MPU */
  1238. if (omap->set_mpu_wkup_lat != NULL)
  1239. omap->latency = (1000000 * omap->fifo_size) /
  1240. (1000 * omap->speed / 8);
  1241. }
  1242. /* reset ASAP, clearing any IRQs */
  1243. omap_i2c_init(omap);
  1244. if (omap->rev < OMAP_I2C_OMAP1_REV_2)
  1245. r = devm_request_irq(&pdev->dev, omap->irq, omap_i2c_omap1_isr,
  1246. IRQF_NO_SUSPEND, pdev->name, omap);
  1247. else
  1248. r = devm_request_threaded_irq(&pdev->dev, omap->irq,
  1249. omap_i2c_isr, omap_i2c_isr_thread,
  1250. IRQF_NO_SUSPEND | IRQF_ONESHOT,
  1251. pdev->name, omap);
  1252. if (r) {
  1253. dev_err(omap->dev, "failure requesting irq %i\n", omap->irq);
  1254. goto err_unuse_clocks;
  1255. }
  1256. adap = &omap->adapter;
  1257. i2c_set_adapdata(adap, omap);
  1258. adap->owner = THIS_MODULE;
  1259. adap->class = I2C_CLASS_DEPRECATED;
  1260. strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
  1261. adap->algo = &omap_i2c_algo;
  1262. adap->quirks = &omap_i2c_quirks;
  1263. adap->dev.parent = &pdev->dev;
  1264. adap->dev.of_node = pdev->dev.of_node;
  1265. adap->bus_recovery_info = &omap_i2c_bus_recovery_info;
  1266. /* i2c device drivers may be active on return from add_adapter() */
  1267. adap->nr = pdev->id;
  1268. r = i2c_add_numbered_adapter(adap);
  1269. if (r)
  1270. goto err_unuse_clocks;
  1271. dev_info(omap->dev, "bus %d rev%d.%d at %d kHz\n", adap->nr,
  1272. major, minor, omap->speed);
  1273. pm_runtime_mark_last_busy(omap->dev);
  1274. pm_runtime_put_autosuspend(omap->dev);
  1275. return 0;
  1276. err_unuse_clocks:
  1277. omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, 0);
  1278. pm_runtime_dont_use_autosuspend(omap->dev);
  1279. pm_runtime_put_sync(omap->dev);
  1280. pm_runtime_disable(&pdev->dev);
  1281. err_free_mem:
  1282. return r;
  1283. }
  1284. static int omap_i2c_remove(struct platform_device *pdev)
  1285. {
  1286. struct omap_i2c_dev *omap = platform_get_drvdata(pdev);
  1287. int ret;
  1288. i2c_del_adapter(&omap->adapter);
  1289. ret = pm_runtime_get_sync(&pdev->dev);
  1290. if (ret < 0)
  1291. return ret;
  1292. omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, 0);
  1293. pm_runtime_dont_use_autosuspend(&pdev->dev);
  1294. pm_runtime_put_sync(&pdev->dev);
  1295. pm_runtime_disable(&pdev->dev);
  1296. return 0;
  1297. }
  1298. static int __maybe_unused omap_i2c_runtime_suspend(struct device *dev)
  1299. {
  1300. struct omap_i2c_dev *omap = dev_get_drvdata(dev);
  1301. omap->iestate = omap_i2c_read_reg(omap, OMAP_I2C_IE_REG);
  1302. if (omap->scheme == OMAP_I2C_SCHEME_0)
  1303. omap_i2c_write_reg(omap, OMAP_I2C_IE_REG, 0);
  1304. else
  1305. omap_i2c_write_reg(omap, OMAP_I2C_IP_V2_IRQENABLE_CLR,
  1306. OMAP_I2C_IP_V2_INTERRUPTS_MASK);
  1307. if (omap->rev < OMAP_I2C_OMAP1_REV_2) {
  1308. omap_i2c_read_reg(omap, OMAP_I2C_IV_REG); /* Read clears */
  1309. } else {
  1310. omap_i2c_write_reg(omap, OMAP_I2C_STAT_REG, omap->iestate);
  1311. /* Flush posted write */
  1312. omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);
  1313. }
  1314. pinctrl_pm_select_sleep_state(dev);
  1315. return 0;
  1316. }
  1317. static int __maybe_unused omap_i2c_runtime_resume(struct device *dev)
  1318. {
  1319. struct omap_i2c_dev *omap = dev_get_drvdata(dev);
  1320. pinctrl_pm_select_default_state(dev);
  1321. if (!omap->regs)
  1322. return 0;
  1323. __omap_i2c_init(omap);
  1324. return 0;
  1325. }
  1326. static const struct dev_pm_ops omap_i2c_pm_ops = {
  1327. SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
  1328. pm_runtime_force_resume)
  1329. SET_RUNTIME_PM_OPS(omap_i2c_runtime_suspend,
  1330. omap_i2c_runtime_resume, NULL)
  1331. };
  1332. static struct platform_driver omap_i2c_driver = {
  1333. .probe = omap_i2c_probe,
  1334. .remove = omap_i2c_remove,
  1335. .driver = {
  1336. .name = "omap_i2c",
  1337. .pm = &omap_i2c_pm_ops,
  1338. .of_match_table = of_match_ptr(omap_i2c_of_match),
  1339. },
  1340. };
  1341. /* I2C may be needed to bring up other drivers */
  1342. static int __init
  1343. omap_i2c_init_driver(void)
  1344. {
  1345. return platform_driver_register(&omap_i2c_driver);
  1346. }
  1347. subsys_initcall(omap_i2c_init_driver);
  1348. static void __exit omap_i2c_exit_driver(void)
  1349. {
  1350. platform_driver_unregister(&omap_i2c_driver);
  1351. }
  1352. module_exit(omap_i2c_exit_driver);
  1353. MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
  1354. MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
  1355. MODULE_LICENSE("GPL");
  1356. MODULE_ALIAS("platform:omap_i2c");