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/drivers/input/touchscreen/intel-mid-touch.c

http://github.com/mirrors/linux
C | 654 lines | 430 code | 131 blank | 93 comment | 57 complexity | e0343caa866cfe33e5140cf784f1bdb2 MD5 | raw file
  1/*
  2 * Intel MID Resistive Touch Screen Driver
  3 *
  4 * Copyright (C) 2008 Intel Corp
  5 *
  6 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  7 *
  8 * This program is free software; you can redistribute it and/or modify
  9 * it under the terms of the GNU General Public License as published by
 10 * the Free Software Foundation; version 2 of the License.
 11 *
 12 * This program is distributed in the hope that it will be useful, but
 13 * WITHOUT ANY WARRANTY; without even the implied warranty of
 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the GNU
 15 * General Public License for more details.
 16 *
 17 * You should have received a copy of the GNU General Public License along
 18 * with this program; if not, write to the Free Software Foundation, Inc.,
 19 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
 20 *
 21 * Questions/Comments/Bug fixes to Sreedhara (sreedhara.ds@intel.com)
 22 *			    Ramesh Agarwal (ramesh.agarwal@intel.com)
 23 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 24 *
 25 * TODO:
 26 *	review conversion of r/m/w sequences
 27 */
 28
 29#include <linux/module.h>
 30#include <linux/input.h>
 31#include <linux/interrupt.h>
 32#include <linux/err.h>
 33#include <linux/param.h>
 34#include <linux/slab.h>
 35#include <linux/platform_device.h>
 36#include <linux/irq.h>
 37#include <linux/delay.h>
 38#include <asm/intel_scu_ipc.h>
 39#include <linux/device.h>
 40
 41/* PMIC Interrupt registers */
 42#define PMIC_REG_ID1		0x00 /* PMIC ID1 register */
 43
 44/* PMIC Interrupt registers */
 45#define PMIC_REG_INT		0x04 /* PMIC interrupt register */
 46#define PMIC_REG_MINT		0x05 /* PMIC interrupt mask register */
 47
 48/* ADC Interrupt registers */
 49#define PMIC_REG_ADCINT		0x5F /* ADC interrupt register */
 50#define PMIC_REG_MADCINT	0x60 /* ADC interrupt mask register */
 51
 52/* ADC Control registers */
 53#define PMIC_REG_ADCCNTL1	0x61 /* ADC control register */
 54
 55/* ADC Channel Selection registers */
 56#define PMICADDR0		0xA4
 57#define END_OF_CHANNEL		0x1F
 58
 59/* ADC Result register */
 60#define PMIC_REG_ADCSNS0H	0x64
 61
 62/* ADC channels for touch screen */
 63#define MRST_TS_CHAN10		0xA /* Touch screen X+ connection */
 64#define MRST_TS_CHAN11		0xB /* Touch screen X- connection */
 65#define MRST_TS_CHAN12		0xC /* Touch screen Y+ connection */
 66#define MRST_TS_CHAN13		0xD /* Touch screen Y- connection */
 67
 68/* Touch screen channel BIAS constants */
 69#define MRST_XBIAS		0x20
 70#define MRST_YBIAS		0x40
 71#define MRST_ZBIAS		0x80
 72
 73/* Touch screen coordinates */
 74#define MRST_X_MIN		10
 75#define MRST_X_MAX		1024
 76#define MRST_X_FUZZ		5
 77#define MRST_Y_MIN		10
 78#define MRST_Y_MAX		1024
 79#define MRST_Y_FUZZ		5
 80#define MRST_PRESSURE_MIN	0
 81#define MRST_PRESSURE_NOMINAL	50
 82#define MRST_PRESSURE_MAX	100
 83
 84#define WAIT_ADC_COMPLETION	10 /* msec */
 85
 86/* PMIC ADC round robin delays */
 87#define ADC_LOOP_DELAY0		0x0 /* Continuous loop */
 88#define ADC_LOOP_DELAY1		0x1 /* 4.5  ms approximate */
 89
 90/* PMIC Vendor Identifiers */
 91#define PMIC_VENDOR_FS		0 /* PMIC vendor FreeScale */
 92#define PMIC_VENDOR_MAXIM	1 /* PMIC vendor MAXIM */
 93#define PMIC_VENDOR_NEC		2 /* PMIC vendor NEC */
 94#define MRSTOUCH_MAX_CHANNELS	32 /* Maximum ADC channels */
 95
 96/* Touch screen device structure */
 97struct mrstouch_dev {
 98	struct device *dev; /* device associated with touch screen */
 99	struct input_dev *input;
100	char phys[32];
101	u16 asr;		/* Address selection register */
102	int irq;
103	unsigned int vendor;	/* PMIC vendor */
104	unsigned int rev;	/* PMIC revision */
105
106	int (*read_prepare)(struct mrstouch_dev *tsdev);
107	int (*read)(struct mrstouch_dev *tsdev, u16 *x, u16 *y, u16 *z);
108	int (*read_finish)(struct mrstouch_dev *tsdev);
109};
110
111
112/*************************** NEC and Maxim Interface ************************/
113
114static int mrstouch_nec_adc_read_prepare(struct mrstouch_dev *tsdev)
115{
116	return intel_scu_ipc_update_register(PMIC_REG_MADCINT, 0, 0x20);
117}
118
119/*
120 * Enables PENDET interrupt.
121 */
122static int mrstouch_nec_adc_read_finish(struct mrstouch_dev *tsdev)
123{
124	int err;
125
126	err = intel_scu_ipc_update_register(PMIC_REG_MADCINT, 0x20, 0x20);
127	if (!err)
128		err = intel_scu_ipc_update_register(PMIC_REG_ADCCNTL1, 0, 0x05);
129
130	return err;
131}
132
133/*
134 * Reads PMIC ADC touch screen result
135 * Reads ADC storage registers for higher 7 and lower 3 bits and
136 * converts the two readings into a single value and turns off gain bit
137 */
138static int mrstouch_ts_chan_read(u16 offset, u16 chan, u16 *vp, u16 *vm)
139{
140	int err;
141	u16 result;
142	u32 res;
143
144	result = PMIC_REG_ADCSNS0H + offset;
145
146	if (chan == MRST_TS_CHAN12)
147		result += 4;
148
149	err = intel_scu_ipc_ioread32(result, &res);
150	if (err)
151		return err;
152
153	/* Mash the bits up */
154
155	*vp = (res & 0xFF) << 3;	/* Highest 7 bits */
156	*vp |= (res >> 8) & 0x07;	/* Lower 3 bits */
157	*vp &= 0x3FF;
158
159	res >>= 16;
160
161	*vm = (res & 0xFF) << 3;	/* Highest 7 bits */
162	*vm |= (res >> 8) & 0x07;	/* Lower 3 bits */
163	*vm &= 0x3FF;
164
165	return 0;
166}
167
168/*
169 * Enables X, Y and Z bias values
170 * Enables YPYM for X channels and XPXM for Y channels
171 */
172static int mrstouch_ts_bias_set(uint offset, uint bias)
173{
174	int count;
175	u16 chan, start;
176	u16 reg[4];
177	u8 data[4];
178
179	chan = PMICADDR0 + offset;
180	start = MRST_TS_CHAN10;
181
182	for (count = 0; count <= 3; count++) {
183		reg[count] = chan++;
184		data[count] = bias | (start + count);
185	}
186
187	return intel_scu_ipc_writev(reg, data, 4);
188}
189
190/* To read touch screen channel values */
191static int mrstouch_nec_adc_read(struct mrstouch_dev *tsdev,
192				 u16 *x, u16 *y, u16 *z)
193{
194	int err;
195	u16 xm, ym, zm;
196
197	/* configure Y bias for X channels */
198	err = mrstouch_ts_bias_set(tsdev->asr, MRST_YBIAS);
199	if (err)
200		goto ipc_error;
201
202	msleep(WAIT_ADC_COMPLETION);
203
204	/* read x+ and x- channels */
205	err = mrstouch_ts_chan_read(tsdev->asr, MRST_TS_CHAN10, x, &xm);
206	if (err)
207		goto ipc_error;
208
209	/* configure x bias for y channels */
210	err = mrstouch_ts_bias_set(tsdev->asr, MRST_XBIAS);
211	if (err)
212		goto ipc_error;
213
214	msleep(WAIT_ADC_COMPLETION);
215
216	/* read y+ and y- channels */
217	err = mrstouch_ts_chan_read(tsdev->asr, MRST_TS_CHAN12, y, &ym);
218	if (err)
219		goto ipc_error;
220
221	/* configure z bias for x and y channels */
222	err = mrstouch_ts_bias_set(tsdev->asr, MRST_ZBIAS);
223	if (err)
224		goto ipc_error;
225
226	msleep(WAIT_ADC_COMPLETION);
227
228	/* read z+ and z- channels */
229	err = mrstouch_ts_chan_read(tsdev->asr, MRST_TS_CHAN10, z, &zm);
230	if (err)
231		goto ipc_error;
232
233	return 0;
234
235ipc_error:
236	dev_err(tsdev->dev, "ipc error during adc read\n");
237	return err;
238}
239
240
241/*************************** Freescale Interface ************************/
242
243static int mrstouch_fs_adc_read_prepare(struct mrstouch_dev *tsdev)
244{
245	int err, count;
246	u16 chan;
247	u16 reg[5];
248	u8 data[5];
249
250	/* Stop the ADC */
251	err = intel_scu_ipc_update_register(PMIC_REG_MADCINT, 0x00, 0x02);
252	if (err)
253		goto ipc_error;
254
255	chan = PMICADDR0 + tsdev->asr;
256
257	/* Set X BIAS */
258	for (count = 0; count <= 3; count++) {
259		reg[count] = chan++;
260		data[count] = 0x2A;
261	}
262	reg[count] =  chan++; /* Dummy */
263	data[count] = 0;
264
265	err = intel_scu_ipc_writev(reg, data, 5);
266	if (err)
267		goto ipc_error;
268
269	msleep(WAIT_ADC_COMPLETION);
270
271	/* Set Y BIAS */
272	for (count = 0; count <= 3; count++) {
273		reg[count] = chan++;
274		data[count] = 0x4A;
275	}
276	reg[count] = chan++; /* Dummy */
277	data[count] = 0;
278
279	err = intel_scu_ipc_writev(reg, data, 5);
280	if (err)
281		goto ipc_error;
282
283	msleep(WAIT_ADC_COMPLETION);
284
285	/* Set Z BIAS */
286	err = intel_scu_ipc_iowrite32(chan + 2, 0x8A8A8A8A);
287	if (err)
288		goto ipc_error;
289
290	msleep(WAIT_ADC_COMPLETION);
291
292	return 0;
293
294ipc_error:
295	dev_err(tsdev->dev, "ipc error during %s\n", __func__);
296	return err;
297}
298
299static int mrstouch_fs_adc_read(struct mrstouch_dev *tsdev,
300				u16 *x, u16 *y, u16 *z)
301{
302	int err;
303	u16 result;
304	u16 reg[4];
305	u8 data[4];
306
307	result = PMIC_REG_ADCSNS0H + tsdev->asr;
308
309	reg[0] = result + 4;
310	reg[1] = result + 5;
311	reg[2] = result + 16;
312	reg[3] = result + 17;
313
314	err = intel_scu_ipc_readv(reg, data, 4);
315	if (err)
316		goto ipc_error;
317
318	*x = data[0] << 3; /* Higher 7 bits */
319	*x |= data[1] & 0x7; /* Lower 3 bits */
320	*x &= 0x3FF;
321
322	*y = data[2] << 3; /* Higher 7 bits */
323	*y |= data[3] & 0x7; /* Lower 3 bits */
324	*y &= 0x3FF;
325
326	/* Read Z value */
327	reg[0] = result + 28;
328	reg[1] = result + 29;
329
330	err = intel_scu_ipc_readv(reg, data, 4);
331	if (err)
332		goto ipc_error;
333
334	*z = data[0] << 3; /* Higher 7 bits */
335	*z |= data[1] & 0x7; /* Lower 3 bits */
336	*z &= 0x3FF;
337
338	return 0;
339
340ipc_error:
341	dev_err(tsdev->dev, "ipc error during %s\n", __func__);
342	return err;
343}
344
345static int mrstouch_fs_adc_read_finish(struct mrstouch_dev *tsdev)
346{
347	int err, count;
348	u16 chan;
349	u16 reg[5];
350	u8 data[5];
351
352	/* Clear all TS channels */
353	chan = PMICADDR0 + tsdev->asr;
354	for (count = 0; count <= 4; count++) {
355		reg[count] = chan++;
356		data[count] = 0;
357	}
358	err = intel_scu_ipc_writev(reg, data, 5);
359	if (err)
360		goto ipc_error;
361
362	for (count = 0; count <= 4; count++) {
363		reg[count] = chan++;
364		data[count] = 0;
365	}
366	err = intel_scu_ipc_writev(reg, data, 5);
367	if (err)
368		goto ipc_error;
369
370	err = intel_scu_ipc_iowrite32(chan + 2, 0x00000000);
371	if (err)
372		goto ipc_error;
373
374	/* Start ADC */
375	err = intel_scu_ipc_update_register(PMIC_REG_MADCINT, 0x02, 0x02);
376	if (err)
377		goto ipc_error;
378
379	return 0;
380
381ipc_error:
382	dev_err(tsdev->dev, "ipc error during %s\n", __func__);
383	return err;
384}
385
386static void mrstouch_report_event(struct input_dev *input,
387			unsigned int x, unsigned int y, unsigned int z)
388{
389	if (z > MRST_PRESSURE_NOMINAL) {
390		/* Pen touched, report button touch and coordinates */
391		input_report_key(input, BTN_TOUCH, 1);
392		input_report_abs(input, ABS_X, x);
393		input_report_abs(input, ABS_Y, y);
394	} else {
395		input_report_key(input, BTN_TOUCH, 0);
396	}
397
398	input_report_abs(input, ABS_PRESSURE, z);
399	input_sync(input);
400}
401
402/* PENDET interrupt handler */
403static irqreturn_t mrstouch_pendet_irq(int irq, void *dev_id)
404{
405	struct mrstouch_dev *tsdev = dev_id;
406	u16 x, y, z;
407
408	/*
409	 * Should we lower thread priority? Probably not, since we are
410	 * not spinning but sleeping...
411	 */
412
413	if (tsdev->read_prepare(tsdev))
414		goto out;
415
416	do {
417		if (tsdev->read(tsdev, &x, &y, &z))
418			break;
419
420		mrstouch_report_event(tsdev->input, x, y, z);
421	} while (z > MRST_PRESSURE_NOMINAL);
422
423	tsdev->read_finish(tsdev);
424
425out:
426	return IRQ_HANDLED;
427}
428
429/* Utility to read PMIC ID */
430static int mrstouch_read_pmic_id(uint *vendor, uint *rev)
431{
432	int err;
433	u8 r;
434
435	err = intel_scu_ipc_ioread8(PMIC_REG_ID1, &r);
436	if (err)
437		return err;
438
439	*vendor = r & 0x7;
440	*rev = (r >> 3) & 0x7;
441
442	return 0;
443}
444
445/*
446 * Parse ADC channels to find end of the channel configured by other ADC user
447 * NEC and MAXIM requires 4 channels and FreeScale needs 18 channels
448 */
449static int mrstouch_chan_parse(struct mrstouch_dev *tsdev)
450{
451	int found = 0;
452	int err, i;
453	u8 r8;
454
455	for (i = 0; i < MRSTOUCH_MAX_CHANNELS; i++) {
456		err = intel_scu_ipc_ioread8(PMICADDR0 + i, &r8);
457		if (err)
458			return err;
459
460		if (r8 == END_OF_CHANNEL) {
461			found = i;
462			break;
463		}
464	}
465
466	if (tsdev->vendor == PMIC_VENDOR_FS) {
467		if (found > MRSTOUCH_MAX_CHANNELS - 18)
468			return -ENOSPC;
469	} else {
470		if (found > MRSTOUCH_MAX_CHANNELS - 4)
471			return -ENOSPC;
472	}
473
474	return found;
475}
476
477
478/*
479 * Writes touch screen channels to ADC address selection registers
480 */
481static int mrstouch_ts_chan_set(uint offset)
482{
483	u16 chan;
484
485	int ret, count;
486
487	chan = PMICADDR0 + offset;
488	for (count = 0; count <= 3; count++) {
489		ret = intel_scu_ipc_iowrite8(chan++, MRST_TS_CHAN10 + count);
490		if (ret)
491			return ret;
492	}
493	return intel_scu_ipc_iowrite8(chan++, END_OF_CHANNEL);
494}
495
496/* Initialize ADC */
497static int mrstouch_adc_init(struct mrstouch_dev *tsdev)
498{
499	int err, start;
500	u8 ra, rm;
501
502	err = mrstouch_read_pmic_id(&tsdev->vendor, &tsdev->rev);
503	if (err) {
504		dev_err(tsdev->dev, "Unable to read PMIC id\n");
505		return err;
506	}
507
508	switch (tsdev->vendor) {
509	case PMIC_VENDOR_NEC:
510	case PMIC_VENDOR_MAXIM:
511		tsdev->read_prepare = mrstouch_nec_adc_read_prepare;
512		tsdev->read = mrstouch_nec_adc_read;
513		tsdev->read_finish = mrstouch_nec_adc_read_finish;
514		break;
515
516	case PMIC_VENDOR_FS:
517		tsdev->read_prepare = mrstouch_fs_adc_read_prepare;
518		tsdev->read = mrstouch_fs_adc_read;
519		tsdev->read_finish = mrstouch_fs_adc_read_finish;
520		break;
521
522	default:
523		dev_err(tsdev->dev,
524			"Unsupported touchscreen: %d\n", tsdev->vendor);
525		return -ENXIO;
526	}
527
528	start = mrstouch_chan_parse(tsdev);
529	if (start < 0) {
530		dev_err(tsdev->dev, "Unable to parse channels\n");
531		return start;
532	}
533
534	tsdev->asr = start;
535
536	/*
537	 * ADC power on, start, enable PENDET and set loop delay
538	 * ADC loop delay is set to 4.5 ms approximately
539	 * Loop delay more than this results in jitter in adc readings
540	 * Setting loop delay to 0 (continuous loop) in MAXIM stops PENDET
541	 * interrupt generation sometimes.
542	 */
543
544	if (tsdev->vendor == PMIC_VENDOR_FS) {
545		ra = 0xE0 | ADC_LOOP_DELAY0;
546		rm = 0x5;
547	} else {
548		/* NEC and MAXIm not consistent with loop delay 0 */
549		ra = 0xE0 | ADC_LOOP_DELAY1;
550		rm = 0x0;
551
552		/* configure touch screen channels */
553		err = mrstouch_ts_chan_set(tsdev->asr);
554		if (err)
555			return err;
556	}
557
558	err = intel_scu_ipc_update_register(PMIC_REG_ADCCNTL1, ra, 0xE7);
559	if (err)
560		return err;
561
562	err = intel_scu_ipc_update_register(PMIC_REG_MADCINT, rm, 0x03);
563	if (err)
564		return err;
565
566	return 0;
567}
568
569
570/* Probe function for touch screen driver */
571static int mrstouch_probe(struct platform_device *pdev)
572{
573	struct mrstouch_dev *tsdev;
574	struct input_dev *input;
575	int err;
576	int irq;
577
578	irq = platform_get_irq(pdev, 0);
579	if (irq < 0) {
580		dev_err(&pdev->dev, "no interrupt assigned\n");
581		return -EINVAL;
582	}
583
584	tsdev = devm_kzalloc(&pdev->dev, sizeof(struct mrstouch_dev),
585			     GFP_KERNEL);
586	if (!tsdev) {
587		dev_err(&pdev->dev, "unable to allocate memory\n");
588		return -ENOMEM;
589	}
590
591	input = devm_input_allocate_device(&pdev->dev);
592	if (!input) {
593		dev_err(&pdev->dev, "unable to allocate input device\n");
594		return -ENOMEM;
595	}
596
597	tsdev->dev = &pdev->dev;
598	tsdev->input = input;
599	tsdev->irq = irq;
600
601	snprintf(tsdev->phys, sizeof(tsdev->phys),
602		 "%s/input0", dev_name(tsdev->dev));
603
604	err = mrstouch_adc_init(tsdev);
605	if (err) {
606		dev_err(&pdev->dev, "ADC initialization failed\n");
607		return err;
608	}
609
610	input->name = "mrst_touchscreen";
611	input->phys = tsdev->phys;
612	input->dev.parent = tsdev->dev;
613
614	input->id.vendor = tsdev->vendor;
615	input->id.version = tsdev->rev;
616
617	input->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_ABS);
618	input->keybit[BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH);
619
620	input_set_abs_params(tsdev->input, ABS_X,
621			     MRST_X_MIN, MRST_X_MAX, MRST_X_FUZZ, 0);
622	input_set_abs_params(tsdev->input, ABS_Y,
623			     MRST_Y_MIN, MRST_Y_MAX, MRST_Y_FUZZ, 0);
624	input_set_abs_params(tsdev->input, ABS_PRESSURE,
625			     MRST_PRESSURE_MIN, MRST_PRESSURE_MAX, 0, 0);
626
627	err = devm_request_threaded_irq(&pdev->dev, tsdev->irq, NULL,
628					mrstouch_pendet_irq, IRQF_ONESHOT,
629					"mrstouch", tsdev);
630	if (err) {
631		dev_err(tsdev->dev, "unable to allocate irq\n");
632		return err;
633	}
634
635	err = input_register_device(tsdev->input);
636	if (err) {
637		dev_err(tsdev->dev, "unable to register input device\n");
638		return err;
639	}
640
641	return 0;
642}
643
644static struct platform_driver mrstouch_driver = {
645	.driver = {
646		.name	= "pmic_touch",
647	},
648	.probe		= mrstouch_probe,
649};
650module_platform_driver(mrstouch_driver);
651
652MODULE_AUTHOR("Sreedhara Murthy. D.S, sreedhara.ds@intel.com");
653MODULE_DESCRIPTION("Intel Moorestown Resistive Touch Screen Driver");
654MODULE_LICENSE("GPL");