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/drivers/ata/ata_piix.c

http://github.com/mirrors/linux
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   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3 *    ata_piix.c - Intel PATA/SATA controllers
   4 *
   5 *    Maintained by:  Tejun Heo <tj@kernel.org>
   6 *    		    Please ALWAYS copy linux-ide@vger.kernel.org
   7 *		    on emails.
   8 *
   9 *	Copyright 2003-2005 Red Hat Inc
  10 *	Copyright 2003-2005 Jeff Garzik
  11 *
  12 *	Copyright header from piix.c:
  13 *
  14 *  Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
  15 *  Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
  16 *  Copyright (C) 2003 Red Hat Inc
  17 *
  18 *  libata documentation is available via 'make {ps|pdf}docs',
  19 *  as Documentation/driver-api/libata.rst
  20 *
  21 *  Hardware documentation available at http://developer.intel.com/
  22 *
  23 * Documentation
  24 *	Publicly available from Intel web site. Errata documentation
  25 * is also publicly available. As an aide to anyone hacking on this
  26 * driver the list of errata that are relevant is below, going back to
  27 * PIIX4. Older device documentation is now a bit tricky to find.
  28 *
  29 * The chipsets all follow very much the same design. The original Triton
  30 * series chipsets do _not_ support independent device timings, but this
  31 * is fixed in Triton II. With the odd mobile exception the chips then
  32 * change little except in gaining more modes until SATA arrives. This
  33 * driver supports only the chips with independent timing (that is those
  34 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
  35 * for the early chip drivers.
  36 *
  37 * Errata of note:
  38 *
  39 * Unfixable
  40 *	PIIX4    errata #9	- Only on ultra obscure hw
  41 *	ICH3	 errata #13     - Not observed to affect real hw
  42 *				  by Intel
  43 *
  44 * Things we must deal with
  45 *	PIIX4	errata #10	- BM IDE hang with non UDMA
  46 *				  (must stop/start dma to recover)
  47 *	440MX   errata #15	- As PIIX4 errata #10
  48 *	PIIX4	errata #15	- Must not read control registers
  49 * 				  during a PIO transfer
  50 *	440MX   errata #13	- As PIIX4 errata #15
  51 *	ICH2	errata #21	- DMA mode 0 doesn't work right
  52 *	ICH0/1  errata #55	- As ICH2 errata #21
  53 *	ICH2	spec c #9	- Extra operations needed to handle
  54 *				  drive hotswap [NOT YET SUPPORTED]
  55 *	ICH2    spec c #20	- IDE PRD must not cross a 64K boundary
  56 *				  and must be dword aligned
  57 *	ICH2    spec c #24	- UDMA mode 4,5 t85/86 should be 6ns not 3.3
  58 *	ICH7	errata #16	- MWDMA1 timings are incorrect
  59 *
  60 * Should have been BIOS fixed:
  61 *	450NX:	errata #19	- DMA hangs on old 450NX
  62 *	450NX:  errata #20	- DMA hangs on old 450NX
  63 *	450NX:  errata #25	- Corruption with DMA on old 450NX
  64 *	ICH3    errata #15      - IDE deadlock under high load
  65 *				  (BIOS must set dev 31 fn 0 bit 23)
  66 *	ICH3	errata #18	- Don't use native mode
  67 */
  68
  69#include <linux/kernel.h>
  70#include <linux/module.h>
  71#include <linux/pci.h>
  72#include <linux/init.h>
  73#include <linux/blkdev.h>
  74#include <linux/delay.h>
  75#include <linux/device.h>
  76#include <linux/gfp.h>
  77#include <scsi/scsi_host.h>
  78#include <linux/libata.h>
  79#include <linux/dmi.h>
  80
  81#define DRV_NAME	"ata_piix"
  82#define DRV_VERSION	"2.13"
  83
  84enum {
  85	PIIX_IOCFG		= 0x54, /* IDE I/O configuration register */
  86	ICH5_PMR		= 0x90, /* address map register */
  87	ICH5_PCS		= 0x92,	/* port control and status */
  88	PIIX_SIDPR_BAR		= 5,
  89	PIIX_SIDPR_LEN		= 16,
  90	PIIX_SIDPR_IDX		= 0,
  91	PIIX_SIDPR_DATA		= 4,
  92
  93	PIIX_FLAG_CHECKINTR	= (1 << 28), /* make sure PCI INTx enabled */
  94	PIIX_FLAG_SIDPR		= (1 << 29), /* SATA idx/data pair regs */
  95
  96	PIIX_PATA_FLAGS		= ATA_FLAG_SLAVE_POSS,
  97	PIIX_SATA_FLAGS		= ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR,
  98
  99	PIIX_FLAG_PIO16		= (1 << 30), /*support 16bit PIO only*/
 100
 101	PIIX_80C_PRI		= (1 << 5) | (1 << 4),
 102	PIIX_80C_SEC		= (1 << 7) | (1 << 6),
 103
 104	/* constants for mapping table */
 105	P0			= 0,  /* port 0 */
 106	P1			= 1,  /* port 1 */
 107	P2			= 2,  /* port 2 */
 108	P3			= 3,  /* port 3 */
 109	IDE			= -1, /* IDE */
 110	NA			= -2, /* not available */
 111	RV			= -3, /* reserved */
 112
 113	PIIX_AHCI_DEVICE	= 6,
 114
 115	/* host->flags bits */
 116	PIIX_HOST_BROKEN_SUSPEND = (1 << 24),
 117};
 118
 119enum piix_controller_ids {
 120	/* controller IDs */
 121	piix_pata_mwdma,	/* PIIX3 MWDMA only */
 122	piix_pata_33,		/* PIIX4 at 33Mhz */
 123	ich_pata_33,		/* ICH up to UDMA 33 only */
 124	ich_pata_66,		/* ICH up to 66 Mhz */
 125	ich_pata_100,		/* ICH up to UDMA 100 */
 126	ich_pata_100_nomwdma1,	/* ICH up to UDMA 100 but with no MWDMA1*/
 127	ich5_sata,
 128	ich6_sata,
 129	ich6m_sata,
 130	ich8_sata,
 131	ich8_2port_sata,
 132	ich8m_apple_sata,	/* locks up on second port enable */
 133	tolapai_sata,
 134	piix_pata_vmw,			/* PIIX4 for VMware, spurious DMA_ERR */
 135	ich8_sata_snb,
 136	ich8_2port_sata_snb,
 137	ich8_2port_sata_byt,
 138};
 139
 140struct piix_map_db {
 141	const u32 mask;
 142	const u16 port_enable;
 143	const int map[][4];
 144};
 145
 146struct piix_host_priv {
 147	const int *map;
 148	u32 saved_iocfg;
 149	void __iomem *sidpr;
 150};
 151
 152static unsigned int in_module_init = 1;
 153
 154static const struct pci_device_id piix_pci_tbl[] = {
 155	/* Intel PIIX3 for the 430HX etc */
 156	{ 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma },
 157	/* VMware ICH4 */
 158	{ 0x8086, 0x7111, 0x15ad, 0x1976, 0, 0, piix_pata_vmw },
 159	/* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
 160	/* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
 161	{ 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
 162	/* Intel PIIX4 */
 163	{ 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
 164	/* Intel PIIX4 */
 165	{ 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
 166	/* Intel PIIX */
 167	{ 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
 168	/* Intel ICH (i810, i815, i840) UDMA 66*/
 169	{ 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
 170	/* Intel ICH0 : UDMA 33*/
 171	{ 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
 172	/* Intel ICH2M */
 173	{ 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
 174	/* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
 175	{ 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
 176	/*  Intel ICH3M */
 177	{ 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
 178	/* Intel ICH3 (E7500/1) UDMA 100 */
 179	{ 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
 180	/* Intel ICH4-L */
 181	{ 0x8086, 0x24C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
 182	/* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
 183	{ 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
 184	{ 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
 185	/* Intel ICH5 */
 186	{ 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
 187	/* C-ICH (i810E2) */
 188	{ 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
 189	/* ESB (855GME/875P + 6300ESB) UDMA 100  */
 190	{ 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
 191	/* ICH6 (and 6) (i915) UDMA 100 */
 192	{ 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
 193	/* ICH7/7-R (i945, i975) UDMA 100*/
 194	{ 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
 195	{ 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
 196	/* ICH8 Mobile PATA Controller */
 197	{ 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
 198
 199	/* SATA ports */
 200
 201	/* 82801EB (ICH5) */
 202	{ 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
 203	/* 82801EB (ICH5) */
 204	{ 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
 205	/* 6300ESB (ICH5 variant with broken PCS present bits) */
 206	{ 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
 207	/* 6300ESB pretending RAID */
 208	{ 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
 209	/* 82801FB/FW (ICH6/ICH6W) */
 210	{ 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
 211	/* 82801FR/FRW (ICH6R/ICH6RW) */
 212	{ 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
 213	/* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented).
 214	 * Attach iff the controller is in IDE mode. */
 215	{ 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID,
 216	  PCI_CLASS_STORAGE_IDE << 8, 0xffff00, ich6m_sata },
 217	/* 82801GB/GR/GH (ICH7, identical to ICH6) */
 218	{ 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
 219	/* 82801GBM/GHM (ICH7M, identical to ICH6M)  */
 220	{ 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata },
 221	/* Enterprise Southbridge 2 (631xESB/632xESB) */
 222	{ 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
 223	/* SATA Controller 1 IDE (ICH8) */
 224	{ 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
 225	/* SATA Controller 2 IDE (ICH8) */
 226	{ 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 227	/* Mobile SATA Controller IDE (ICH8M), Apple */
 228	{ 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata },
 229	{ 0x8086, 0x2828, 0x106b, 0x00a1, 0, 0, ich8m_apple_sata },
 230	{ 0x8086, 0x2828, 0x106b, 0x00a3, 0, 0, ich8m_apple_sata },
 231	/* Mobile SATA Controller IDE (ICH8M) */
 232	{ 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
 233	/* SATA Controller IDE (ICH9) */
 234	{ 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
 235	/* SATA Controller IDE (ICH9) */
 236	{ 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 237	/* SATA Controller IDE (ICH9) */
 238	{ 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 239	/* SATA Controller IDE (ICH9M) */
 240	{ 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 241	/* SATA Controller IDE (ICH9M) */
 242	{ 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 243	/* SATA Controller IDE (ICH9M) */
 244	{ 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
 245	/* SATA Controller IDE (Tolapai) */
 246	{ 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata },
 247	/* SATA Controller IDE (ICH10) */
 248	{ 0x8086, 0x3a00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
 249	/* SATA Controller IDE (ICH10) */
 250	{ 0x8086, 0x3a06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 251	/* SATA Controller IDE (ICH10) */
 252	{ 0x8086, 0x3a20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
 253	/* SATA Controller IDE (ICH10) */
 254	{ 0x8086, 0x3a26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 255	/* SATA Controller IDE (PCH) */
 256	{ 0x8086, 0x3b20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
 257	/* SATA Controller IDE (PCH) */
 258	{ 0x8086, 0x3b21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 259	/* SATA Controller IDE (PCH) */
 260	{ 0x8086, 0x3b26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 261	/* SATA Controller IDE (PCH) */
 262	{ 0x8086, 0x3b28, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
 263	/* SATA Controller IDE (PCH) */
 264	{ 0x8086, 0x3b2d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 265	/* SATA Controller IDE (PCH) */
 266	{ 0x8086, 0x3b2e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
 267	/* SATA Controller IDE (CPT) */
 268	{ 0x8086, 0x1c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
 269	/* SATA Controller IDE (CPT) */
 270	{ 0x8086, 0x1c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
 271	/* SATA Controller IDE (CPT) */
 272	{ 0x8086, 0x1c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 273	/* SATA Controller IDE (CPT) */
 274	{ 0x8086, 0x1c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 275	/* SATA Controller IDE (PBG) */
 276	{ 0x8086, 0x1d00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
 277	/* SATA Controller IDE (PBG) */
 278	{ 0x8086, 0x1d08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 279	/* SATA Controller IDE (Panther Point) */
 280	{ 0x8086, 0x1e00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
 281	/* SATA Controller IDE (Panther Point) */
 282	{ 0x8086, 0x1e01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
 283	/* SATA Controller IDE (Panther Point) */
 284	{ 0x8086, 0x1e08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 285	/* SATA Controller IDE (Panther Point) */
 286	{ 0x8086, 0x1e09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 287	/* SATA Controller IDE (Lynx Point) */
 288	{ 0x8086, 0x8c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
 289	/* SATA Controller IDE (Lynx Point) */
 290	{ 0x8086, 0x8c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
 291	/* SATA Controller IDE (Lynx Point) */
 292	{ 0x8086, 0x8c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_snb },
 293	/* SATA Controller IDE (Lynx Point) */
 294	{ 0x8086, 0x8c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 295	/* SATA Controller IDE (Lynx Point-LP) */
 296	{ 0x8086, 0x9c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
 297	/* SATA Controller IDE (Lynx Point-LP) */
 298	{ 0x8086, 0x9c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
 299	/* SATA Controller IDE (Lynx Point-LP) */
 300	{ 0x8086, 0x9c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 301	/* SATA Controller IDE (Lynx Point-LP) */
 302	{ 0x8086, 0x9c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 303	/* SATA Controller IDE (DH89xxCC) */
 304	{ 0x8086, 0x2326, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 305	/* SATA Controller IDE (Avoton) */
 306	{ 0x8086, 0x1f20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
 307	/* SATA Controller IDE (Avoton) */
 308	{ 0x8086, 0x1f21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
 309	/* SATA Controller IDE (Avoton) */
 310	{ 0x8086, 0x1f30, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 311	/* SATA Controller IDE (Avoton) */
 312	{ 0x8086, 0x1f31, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 313	/* SATA Controller IDE (Wellsburg) */
 314	{ 0x8086, 0x8d00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
 315	/* SATA Controller IDE (Wellsburg) */
 316	{ 0x8086, 0x8d08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_snb },
 317	/* SATA Controller IDE (Wellsburg) */
 318	{ 0x8086, 0x8d60, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
 319	/* SATA Controller IDE (Wellsburg) */
 320	{ 0x8086, 0x8d68, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 321	/* SATA Controller IDE (BayTrail) */
 322	{ 0x8086, 0x0F20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_byt },
 323	{ 0x8086, 0x0F21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_byt },
 324	/* SATA Controller IDE (Coleto Creek) */
 325	{ 0x8086, 0x23a6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 326	/* SATA Controller IDE (9 Series) */
 327	{ 0x8086, 0x8c88, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_snb },
 328	/* SATA Controller IDE (9 Series) */
 329	{ 0x8086, 0x8c89, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_snb },
 330	/* SATA Controller IDE (9 Series) */
 331	{ 0x8086, 0x8c80, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
 332	/* SATA Controller IDE (9 Series) */
 333	{ 0x8086, 0x8c81, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
 334
 335	{ }	/* terminate list */
 336};
 337
 338static const struct piix_map_db ich5_map_db = {
 339	.mask = 0x7,
 340	.port_enable = 0x3,
 341	.map = {
 342		/* PM   PS   SM   SS       MAP  */
 343		{  P0,  NA,  P1,  NA }, /* 000b */
 344		{  P1,  NA,  P0,  NA }, /* 001b */
 345		{  RV,  RV,  RV,  RV },
 346		{  RV,  RV,  RV,  RV },
 347		{  P0,  P1, IDE, IDE }, /* 100b */
 348		{  P1,  P0, IDE, IDE }, /* 101b */
 349		{ IDE, IDE,  P0,  P1 }, /* 110b */
 350		{ IDE, IDE,  P1,  P0 }, /* 111b */
 351	},
 352};
 353
 354static const struct piix_map_db ich6_map_db = {
 355	.mask = 0x3,
 356	.port_enable = 0xf,
 357	.map = {
 358		/* PM   PS   SM   SS       MAP */
 359		{  P0,  P2,  P1,  P3 }, /* 00b */
 360		{ IDE, IDE,  P1,  P3 }, /* 01b */
 361		{  P0,  P2, IDE, IDE }, /* 10b */
 362		{  RV,  RV,  RV,  RV },
 363	},
 364};
 365
 366static const struct piix_map_db ich6m_map_db = {
 367	.mask = 0x3,
 368	.port_enable = 0x5,
 369
 370	/* Map 01b isn't specified in the doc but some notebooks use
 371	 * it anyway.  MAP 01b have been spotted on both ICH6M and
 372	 * ICH7M.
 373	 */
 374	.map = {
 375		/* PM   PS   SM   SS       MAP */
 376		{  P0,  P2,  NA,  NA }, /* 00b */
 377		{ IDE, IDE,  P1,  P3 }, /* 01b */
 378		{  P0,  P2, IDE, IDE }, /* 10b */
 379		{  RV,  RV,  RV,  RV },
 380	},
 381};
 382
 383static const struct piix_map_db ich8_map_db = {
 384	.mask = 0x3,
 385	.port_enable = 0xf,
 386	.map = {
 387		/* PM   PS   SM   SS       MAP */
 388		{  P0,  P2,  P1,  P3 }, /* 00b (hardwired when in AHCI) */
 389		{  RV,  RV,  RV,  RV },
 390		{  P0,  P2, IDE, IDE }, /* 10b (IDE mode) */
 391		{  RV,  RV,  RV,  RV },
 392	},
 393};
 394
 395static const struct piix_map_db ich8_2port_map_db = {
 396	.mask = 0x3,
 397	.port_enable = 0x3,
 398	.map = {
 399		/* PM   PS   SM   SS       MAP */
 400		{  P0,  NA,  P1,  NA }, /* 00b */
 401		{  RV,  RV,  RV,  RV }, /* 01b */
 402		{  RV,  RV,  RV,  RV }, /* 10b */
 403		{  RV,  RV,  RV,  RV },
 404	},
 405};
 406
 407static const struct piix_map_db ich8m_apple_map_db = {
 408	.mask = 0x3,
 409	.port_enable = 0x1,
 410	.map = {
 411		/* PM   PS   SM   SS       MAP */
 412		{  P0,  NA,  NA,  NA }, /* 00b */
 413		{  RV,  RV,  RV,  RV },
 414		{  P0,  P2, IDE, IDE }, /* 10b */
 415		{  RV,  RV,  RV,  RV },
 416	},
 417};
 418
 419static const struct piix_map_db tolapai_map_db = {
 420	.mask = 0x3,
 421	.port_enable = 0x3,
 422	.map = {
 423		/* PM   PS   SM   SS       MAP */
 424		{  P0,  NA,  P1,  NA }, /* 00b */
 425		{  RV,  RV,  RV,  RV }, /* 01b */
 426		{  RV,  RV,  RV,  RV }, /* 10b */
 427		{  RV,  RV,  RV,  RV },
 428	},
 429};
 430
 431static const struct piix_map_db *piix_map_db_table[] = {
 432	[ich5_sata]		= &ich5_map_db,
 433	[ich6_sata]		= &ich6_map_db,
 434	[ich6m_sata]		= &ich6m_map_db,
 435	[ich8_sata]		= &ich8_map_db,
 436	[ich8_2port_sata]	= &ich8_2port_map_db,
 437	[ich8m_apple_sata]	= &ich8m_apple_map_db,
 438	[tolapai_sata]		= &tolapai_map_db,
 439	[ich8_sata_snb]		= &ich8_map_db,
 440	[ich8_2port_sata_snb]	= &ich8_2port_map_db,
 441	[ich8_2port_sata_byt]	= &ich8_2port_map_db,
 442};
 443
 444static const struct pci_bits piix_enable_bits[] = {
 445	{ 0x41U, 1U, 0x80UL, 0x80UL },	/* port 0 */
 446	{ 0x43U, 1U, 0x80UL, 0x80UL },	/* port 1 */
 447};
 448
 449MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
 450MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
 451MODULE_LICENSE("GPL");
 452MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
 453MODULE_VERSION(DRV_VERSION);
 454
 455struct ich_laptop {
 456	u16 device;
 457	u16 subvendor;
 458	u16 subdevice;
 459};
 460
 461/*
 462 *	List of laptops that use short cables rather than 80 wire
 463 */
 464
 465static const struct ich_laptop ich_laptop[] = {
 466	/* devid, subvendor, subdev */
 467	{ 0x27DF, 0x0005, 0x0280 },	/* ICH7 on Acer 5602WLMi */
 468	{ 0x27DF, 0x1025, 0x0102 },	/* ICH7 on Acer 5602aWLMi */
 469	{ 0x27DF, 0x1025, 0x0110 },	/* ICH7 on Acer 3682WLMi */
 470	{ 0x27DF, 0x1028, 0x02b0 },	/* ICH7 on unknown Dell */
 471	{ 0x27DF, 0x1043, 0x1267 },	/* ICH7 on Asus W5F */
 472	{ 0x27DF, 0x103C, 0x30A1 },	/* ICH7 on HP Compaq nc2400 */
 473	{ 0x27DF, 0x103C, 0x361a },	/* ICH7 on unknown HP  */
 474	{ 0x27DF, 0x1071, 0xD221 },	/* ICH7 on Hercules EC-900 */
 475	{ 0x27DF, 0x152D, 0x0778 },	/* ICH7 on unknown Intel */
 476	{ 0x24CA, 0x1025, 0x0061 },	/* ICH4 on ACER Aspire 2023WLMi */
 477	{ 0x24CA, 0x1025, 0x003d },	/* ICH4 on ACER TM290 */
 478	{ 0x24CA, 0x10CF, 0x11AB },	/* ICH4M on Fujitsu-Siemens Lifebook S6120 */
 479	{ 0x266F, 0x1025, 0x0066 },	/* ICH6 on ACER Aspire 1694WLMi */
 480	{ 0x2653, 0x1043, 0x82D8 },	/* ICH6M on Asus Eee 701 */
 481	{ 0x27df, 0x104d, 0x900e },	/* ICH7 on Sony TZ-90 */
 482	/* end marker */
 483	{ 0, }
 484};
 485
 486static int piix_port_start(struct ata_port *ap)
 487{
 488	if (!(ap->flags & PIIX_FLAG_PIO16))
 489		ap->pflags |= ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE;
 490
 491	return ata_bmdma_port_start(ap);
 492}
 493
 494/**
 495 *	ich_pata_cable_detect - Probe host controller cable detect info
 496 *	@ap: Port for which cable detect info is desired
 497 *
 498 *	Read 80c cable indicator from ATA PCI device's PCI config
 499 *	register.  This register is normally set by firmware (BIOS).
 500 *
 501 *	LOCKING:
 502 *	None (inherited from caller).
 503 */
 504
 505static int ich_pata_cable_detect(struct ata_port *ap)
 506{
 507	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 508	struct piix_host_priv *hpriv = ap->host->private_data;
 509	const struct ich_laptop *lap = &ich_laptop[0];
 510	u8 mask;
 511
 512	/* Check for specials */
 513	while (lap->device) {
 514		if (lap->device == pdev->device &&
 515		    lap->subvendor == pdev->subsystem_vendor &&
 516		    lap->subdevice == pdev->subsystem_device)
 517			return ATA_CBL_PATA40_SHORT;
 518
 519		lap++;
 520	}
 521
 522	/* check BIOS cable detect results */
 523	mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
 524	if ((hpriv->saved_iocfg & mask) == 0)
 525		return ATA_CBL_PATA40;
 526	return ATA_CBL_PATA80;
 527}
 528
 529/**
 530 *	piix_pata_prereset - prereset for PATA host controller
 531 *	@link: Target link
 532 *	@deadline: deadline jiffies for the operation
 533 *
 534 *	LOCKING:
 535 *	None (inherited from caller).
 536 */
 537static int piix_pata_prereset(struct ata_link *link, unsigned long deadline)
 538{
 539	struct ata_port *ap = link->ap;
 540	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 541
 542	if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
 543		return -ENOENT;
 544	return ata_sff_prereset(link, deadline);
 545}
 546
 547static DEFINE_SPINLOCK(piix_lock);
 548
 549static void piix_set_timings(struct ata_port *ap, struct ata_device *adev,
 550			     u8 pio)
 551{
 552	struct pci_dev *dev	= to_pci_dev(ap->host->dev);
 553	unsigned long flags;
 554	unsigned int is_slave	= (adev->devno != 0);
 555	unsigned int master_port= ap->port_no ? 0x42 : 0x40;
 556	unsigned int slave_port	= 0x44;
 557	u16 master_data;
 558	u8 slave_data;
 559	u8 udma_enable;
 560	int control = 0;
 561
 562	/*
 563	 *	See Intel Document 298600-004 for the timing programing rules
 564	 *	for ICH controllers.
 565	 */
 566
 567	static const	 /* ISP  RTC */
 568	u8 timings[][2]	= { { 0, 0 },
 569			    { 0, 0 },
 570			    { 1, 0 },
 571			    { 2, 1 },
 572			    { 2, 3 }, };
 573
 574	if (pio >= 2)
 575		control |= 1;	/* TIME1 enable */
 576	if (ata_pio_need_iordy(adev))
 577		control |= 2;	/* IE enable */
 578	/* Intel specifies that the PPE functionality is for disk only */
 579	if (adev->class == ATA_DEV_ATA)
 580		control |= 4;	/* PPE enable */
 581	/*
 582	 * If the drive MWDMA is faster than it can do PIO then
 583	 * we must force PIO into PIO0
 584	 */
 585	if (adev->pio_mode < XFER_PIO_0 + pio)
 586		/* Enable DMA timing only */
 587		control |= 8;	/* PIO cycles in PIO0 */
 588
 589	spin_lock_irqsave(&piix_lock, flags);
 590
 591	/* PIO configuration clears DTE unconditionally.  It will be
 592	 * programmed in set_dmamode which is guaranteed to be called
 593	 * after set_piomode if any DMA mode is available.
 594	 */
 595	pci_read_config_word(dev, master_port, &master_data);
 596	if (is_slave) {
 597		/* clear TIME1|IE1|PPE1|DTE1 */
 598		master_data &= 0xff0f;
 599		/* enable PPE1, IE1 and TIME1 as needed */
 600		master_data |= (control << 4);
 601		pci_read_config_byte(dev, slave_port, &slave_data);
 602		slave_data &= (ap->port_no ? 0x0f : 0xf0);
 603		/* Load the timing nibble for this slave */
 604		slave_data |= ((timings[pio][0] << 2) | timings[pio][1])
 605						<< (ap->port_no ? 4 : 0);
 606	} else {
 607		/* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
 608		master_data &= 0xccf0;
 609		/* Enable PPE, IE and TIME as appropriate */
 610		master_data |= control;
 611		/* load ISP and RCT */
 612		master_data |=
 613			(timings[pio][0] << 12) |
 614			(timings[pio][1] << 8);
 615	}
 616
 617	/* Enable SITRE (separate slave timing register) */
 618	master_data |= 0x4000;
 619	pci_write_config_word(dev, master_port, master_data);
 620	if (is_slave)
 621		pci_write_config_byte(dev, slave_port, slave_data);
 622
 623	/* Ensure the UDMA bit is off - it will be turned back on if
 624	   UDMA is selected */
 625
 626	if (ap->udma_mask) {
 627		pci_read_config_byte(dev, 0x48, &udma_enable);
 628		udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
 629		pci_write_config_byte(dev, 0x48, udma_enable);
 630	}
 631
 632	spin_unlock_irqrestore(&piix_lock, flags);
 633}
 634
 635/**
 636 *	piix_set_piomode - Initialize host controller PATA PIO timings
 637 *	@ap: Port whose timings we are configuring
 638 *	@adev: Drive in question
 639 *
 640 *	Set PIO mode for device, in host controller PCI config space.
 641 *
 642 *	LOCKING:
 643 *	None (inherited from caller).
 644 */
 645
 646static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev)
 647{
 648	piix_set_timings(ap, adev, adev->pio_mode - XFER_PIO_0);
 649}
 650
 651/**
 652 *	do_pata_set_dmamode - Initialize host controller PATA PIO timings
 653 *	@ap: Port whose timings we are configuring
 654 *	@adev: Drive in question
 655 *	@isich: set if the chip is an ICH device
 656 *
 657 *	Set UDMA mode for device, in host controller PCI config space.
 658 *
 659 *	LOCKING:
 660 *	None (inherited from caller).
 661 */
 662
 663static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich)
 664{
 665	struct pci_dev *dev	= to_pci_dev(ap->host->dev);
 666	unsigned long flags;
 667	u8 speed		= adev->dma_mode;
 668	int devid		= adev->devno + 2 * ap->port_no;
 669	u8 udma_enable		= 0;
 670
 671	if (speed >= XFER_UDMA_0) {
 672		unsigned int udma = speed - XFER_UDMA_0;
 673		u16 udma_timing;
 674		u16 ideconf;
 675		int u_clock, u_speed;
 676
 677		spin_lock_irqsave(&piix_lock, flags);
 678
 679		pci_read_config_byte(dev, 0x48, &udma_enable);
 680
 681		/*
 682		 * UDMA is handled by a combination of clock switching and
 683		 * selection of dividers
 684		 *
 685		 * Handy rule: Odd modes are UDMATIMx 01, even are 02
 686		 *	       except UDMA0 which is 00
 687		 */
 688		u_speed = min(2 - (udma & 1), udma);
 689		if (udma == 5)
 690			u_clock = 0x1000;	/* 100Mhz */
 691		else if (udma > 2)
 692			u_clock = 1;		/* 66Mhz */
 693		else
 694			u_clock = 0;		/* 33Mhz */
 695
 696		udma_enable |= (1 << devid);
 697
 698		/* Load the CT/RP selection */
 699		pci_read_config_word(dev, 0x4A, &udma_timing);
 700		udma_timing &= ~(3 << (4 * devid));
 701		udma_timing |= u_speed << (4 * devid);
 702		pci_write_config_word(dev, 0x4A, udma_timing);
 703
 704		if (isich) {
 705			/* Select a 33/66/100Mhz clock */
 706			pci_read_config_word(dev, 0x54, &ideconf);
 707			ideconf &= ~(0x1001 << devid);
 708			ideconf |= u_clock << devid;
 709			/* For ICH or later we should set bit 10 for better
 710			   performance (WR_PingPong_En) */
 711			pci_write_config_word(dev, 0x54, ideconf);
 712		}
 713
 714		pci_write_config_byte(dev, 0x48, udma_enable);
 715
 716		spin_unlock_irqrestore(&piix_lock, flags);
 717	} else {
 718		/* MWDMA is driven by the PIO timings. */
 719		unsigned int mwdma = speed - XFER_MW_DMA_0;
 720		const unsigned int needed_pio[3] = {
 721			XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
 722		};
 723		int pio = needed_pio[mwdma] - XFER_PIO_0;
 724
 725		/* XFER_PIO_0 is never used currently */
 726		piix_set_timings(ap, adev, pio);
 727	}
 728}
 729
 730/**
 731 *	piix_set_dmamode - Initialize host controller PATA DMA timings
 732 *	@ap: Port whose timings we are configuring
 733 *	@adev: um
 734 *
 735 *	Set MW/UDMA mode for device, in host controller PCI config space.
 736 *
 737 *	LOCKING:
 738 *	None (inherited from caller).
 739 */
 740
 741static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev)
 742{
 743	do_pata_set_dmamode(ap, adev, 0);
 744}
 745
 746/**
 747 *	ich_set_dmamode - Initialize host controller PATA DMA timings
 748 *	@ap: Port whose timings we are configuring
 749 *	@adev: um
 750 *
 751 *	Set MW/UDMA mode for device, in host controller PCI config space.
 752 *
 753 *	LOCKING:
 754 *	None (inherited from caller).
 755 */
 756
 757static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev)
 758{
 759	do_pata_set_dmamode(ap, adev, 1);
 760}
 761
 762/*
 763 * Serial ATA Index/Data Pair Superset Registers access
 764 *
 765 * Beginning from ICH8, there's a sane way to access SCRs using index
 766 * and data register pair located at BAR5 which means that we have
 767 * separate SCRs for master and slave.  This is handled using libata
 768 * slave_link facility.
 769 */
 770static const int piix_sidx_map[] = {
 771	[SCR_STATUS]	= 0,
 772	[SCR_ERROR]	= 2,
 773	[SCR_CONTROL]	= 1,
 774};
 775
 776static void piix_sidpr_sel(struct ata_link *link, unsigned int reg)
 777{
 778	struct ata_port *ap = link->ap;
 779	struct piix_host_priv *hpriv = ap->host->private_data;
 780
 781	iowrite32(((ap->port_no * 2 + link->pmp) << 8) | piix_sidx_map[reg],
 782		  hpriv->sidpr + PIIX_SIDPR_IDX);
 783}
 784
 785static int piix_sidpr_scr_read(struct ata_link *link,
 786			       unsigned int reg, u32 *val)
 787{
 788	struct piix_host_priv *hpriv = link->ap->host->private_data;
 789
 790	if (reg >= ARRAY_SIZE(piix_sidx_map))
 791		return -EINVAL;
 792
 793	piix_sidpr_sel(link, reg);
 794	*val = ioread32(hpriv->sidpr + PIIX_SIDPR_DATA);
 795	return 0;
 796}
 797
 798static int piix_sidpr_scr_write(struct ata_link *link,
 799				unsigned int reg, u32 val)
 800{
 801	struct piix_host_priv *hpriv = link->ap->host->private_data;
 802
 803	if (reg >= ARRAY_SIZE(piix_sidx_map))
 804		return -EINVAL;
 805
 806	piix_sidpr_sel(link, reg);
 807	iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA);
 808	return 0;
 809}
 810
 811static int piix_sidpr_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
 812			      unsigned hints)
 813{
 814	return sata_link_scr_lpm(link, policy, false);
 815}
 816
 817static bool piix_irq_check(struct ata_port *ap)
 818{
 819	if (unlikely(!ap->ioaddr.bmdma_addr))
 820		return false;
 821
 822	return ap->ops->bmdma_status(ap) & ATA_DMA_INTR;
 823}
 824
 825#ifdef CONFIG_PM_SLEEP
 826static int piix_broken_suspend(void)
 827{
 828	static const struct dmi_system_id sysids[] = {
 829		{
 830			.ident = "TECRA M3",
 831			.matches = {
 832				DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 833				DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"),
 834			},
 835		},
 836		{
 837			.ident = "TECRA M3",
 838			.matches = {
 839				DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 840				DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"),
 841			},
 842		},
 843		{
 844			.ident = "TECRA M3",
 845			.matches = {
 846				DMI_MATCH(DMI_OEM_STRING, "Tecra M3,"),
 847			},
 848		},
 849		{
 850			.ident = "TECRA M4",
 851			.matches = {
 852				DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 853				DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M4"),
 854			},
 855		},
 856		{
 857			.ident = "TECRA M4",
 858			.matches = {
 859				DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 860				DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M4"),
 861			},
 862		},
 863		{
 864			.ident = "TECRA M5",
 865			.matches = {
 866				DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 867				DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"),
 868			},
 869		},
 870		{
 871			.ident = "TECRA M6",
 872			.matches = {
 873				DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 874				DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M6"),
 875			},
 876		},
 877		{
 878			.ident = "TECRA M7",
 879			.matches = {
 880				DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 881				DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"),
 882			},
 883		},
 884		{
 885			.ident = "TECRA A8",
 886			.matches = {
 887				DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 888				DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"),
 889			},
 890		},
 891		{
 892			.ident = "Satellite R20",
 893			.matches = {
 894				DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 895				DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R20"),
 896			},
 897		},
 898		{
 899			.ident = "Satellite R25",
 900			.matches = {
 901				DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 902				DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"),
 903			},
 904		},
 905		{
 906			.ident = "Satellite U200",
 907			.matches = {
 908				DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 909				DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"),
 910			},
 911		},
 912		{
 913			.ident = "Satellite U200",
 914			.matches = {
 915				DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 916				DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"),
 917			},
 918		},
 919		{
 920			.ident = "Satellite Pro U200",
 921			.matches = {
 922				DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 923				DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"),
 924			},
 925		},
 926		{
 927			.ident = "Satellite U205",
 928			.matches = {
 929				DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 930				DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"),
 931			},
 932		},
 933		{
 934			.ident = "SATELLITE U205",
 935			.matches = {
 936				DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 937				DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"),
 938			},
 939		},
 940		{
 941			.ident = "Satellite Pro A120",
 942			.matches = {
 943				DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 944				DMI_MATCH(DMI_PRODUCT_NAME, "Satellite Pro A120"),
 945			},
 946		},
 947		{
 948			.ident = "Portege M500",
 949			.matches = {
 950				DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 951				DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"),
 952			},
 953		},
 954		{
 955			.ident = "VGN-BX297XP",
 956			.matches = {
 957				DMI_MATCH(DMI_SYS_VENDOR, "Sony Corporation"),
 958				DMI_MATCH(DMI_PRODUCT_NAME, "VGN-BX297XP"),
 959			},
 960		},
 961
 962		{ }	/* terminate list */
 963	};
 964
 965	if (dmi_check_system(sysids))
 966		return 1;
 967
 968	/* TECRA M4 sometimes forgets its identify and reports bogus
 969	 * DMI information.  As the bogus information is a bit
 970	 * generic, match as many entries as possible.  This manual
 971	 * matching is necessary because dmi_system_id.matches is
 972	 * limited to four entries.
 973	 */
 974	if (dmi_match(DMI_SYS_VENDOR, "TOSHIBA") &&
 975	    dmi_match(DMI_PRODUCT_NAME, "000000") &&
 976	    dmi_match(DMI_PRODUCT_VERSION, "000000") &&
 977	    dmi_match(DMI_PRODUCT_SERIAL, "000000") &&
 978	    dmi_match(DMI_BOARD_VENDOR, "TOSHIBA") &&
 979	    dmi_match(DMI_BOARD_NAME, "Portable PC") &&
 980	    dmi_match(DMI_BOARD_VERSION, "Version A0"))
 981		return 1;
 982
 983	return 0;
 984}
 985
 986static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
 987{
 988	struct ata_host *host = pci_get_drvdata(pdev);
 989	unsigned long flags;
 990	int rc = 0;
 991
 992	rc = ata_host_suspend(host, mesg);
 993	if (rc)
 994		return rc;
 995
 996	/* Some braindamaged ACPI suspend implementations expect the
 997	 * controller to be awake on entry; otherwise, it burns cpu
 998	 * cycles and power trying to do something to the sleeping
 999	 * beauty.
1000	 */
1001	if (piix_broken_suspend() && (mesg.event & PM_EVENT_SLEEP)) {
1002		pci_save_state(pdev);
1003
1004		/* mark its power state as "unknown", since we don't
1005		 * know if e.g. the BIOS will change its device state
1006		 * when we suspend.
1007		 */
1008		if (pdev->current_state == PCI_D0)
1009			pdev->current_state = PCI_UNKNOWN;
1010
1011		/* tell resume that it's waking up from broken suspend */
1012		spin_lock_irqsave(&host->lock, flags);
1013		host->flags |= PIIX_HOST_BROKEN_SUSPEND;
1014		spin_unlock_irqrestore(&host->lock, flags);
1015	} else
1016		ata_pci_device_do_suspend(pdev, mesg);
1017
1018	return 0;
1019}
1020
1021static int piix_pci_device_resume(struct pci_dev *pdev)
1022{
1023	struct ata_host *host = pci_get_drvdata(pdev);
1024	unsigned long flags;
1025	int rc;
1026
1027	if (host->flags & PIIX_HOST_BROKEN_SUSPEND) {
1028		spin_lock_irqsave(&host->lock, flags);
1029		host->flags &= ~PIIX_HOST_BROKEN_SUSPEND;
1030		spin_unlock_irqrestore(&host->lock, flags);
1031
1032		pci_set_power_state(pdev, PCI_D0);
1033		pci_restore_state(pdev);
1034
1035		/* PCI device wasn't disabled during suspend.  Use
1036		 * pci_reenable_device() to avoid affecting the enable
1037		 * count.
1038		 */
1039		rc = pci_reenable_device(pdev);
1040		if (rc)
1041			dev_err(&pdev->dev,
1042				"failed to enable device after resume (%d)\n",
1043				rc);
1044	} else
1045		rc = ata_pci_device_do_resume(pdev);
1046
1047	if (rc == 0)
1048		ata_host_resume(host);
1049
1050	return rc;
1051}
1052#endif
1053
1054static u8 piix_vmw_bmdma_status(struct ata_port *ap)
1055{
1056	return ata_bmdma_status(ap) & ~ATA_DMA_ERR;
1057}
1058
1059static struct scsi_host_template piix_sht = {
1060	ATA_BMDMA_SHT(DRV_NAME),
1061};
1062
1063static struct ata_port_operations piix_sata_ops = {
1064	.inherits		= &ata_bmdma32_port_ops,
1065	.sff_irq_check		= piix_irq_check,
1066	.port_start		= piix_port_start,
1067};
1068
1069static struct ata_port_operations piix_pata_ops = {
1070	.inherits		= &piix_sata_ops,
1071	.cable_detect		= ata_cable_40wire,
1072	.set_piomode		= piix_set_piomode,
1073	.set_dmamode		= piix_set_dmamode,
1074	.prereset		= piix_pata_prereset,
1075};
1076
1077static struct ata_port_operations piix_vmw_ops = {
1078	.inherits		= &piix_pata_ops,
1079	.bmdma_status		= piix_vmw_bmdma_status,
1080};
1081
1082static struct ata_port_operations ich_pata_ops = {
1083	.inherits		= &piix_pata_ops,
1084	.cable_detect		= ich_pata_cable_detect,
1085	.set_dmamode		= ich_set_dmamode,
1086};
1087
1088static struct device_attribute *piix_sidpr_shost_attrs[] = {
1089	&dev_attr_link_power_management_policy,
1090	NULL
1091};
1092
1093static struct scsi_host_template piix_sidpr_sht = {
1094	ATA_BMDMA_SHT(DRV_NAME),
1095	.shost_attrs		= piix_sidpr_shost_attrs,
1096};
1097
1098static struct ata_port_operations piix_sidpr_sata_ops = {
1099	.inherits		= &piix_sata_ops,
1100	.hardreset		= sata_std_hardreset,
1101	.scr_read		= piix_sidpr_scr_read,
1102	.scr_write		= piix_sidpr_scr_write,
1103	.set_lpm		= piix_sidpr_set_lpm,
1104};
1105
1106static struct ata_port_info piix_port_info[] = {
1107	[piix_pata_mwdma] =	/* PIIX3 MWDMA only */
1108	{
1109		.flags		= PIIX_PATA_FLAGS,
1110		.pio_mask	= ATA_PIO4,
1111		.mwdma_mask	= ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
1112		.port_ops	= &piix_pata_ops,
1113	},
1114
1115	[piix_pata_33] =	/* PIIX4 at 33MHz */
1116	{
1117		.flags		= PIIX_PATA_FLAGS,
1118		.pio_mask	= ATA_PIO4,
1119		.mwdma_mask	= ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
1120		.udma_mask	= ATA_UDMA2,
1121		.port_ops	= &piix_pata_ops,
1122	},
1123
1124	[ich_pata_33] =		/* ICH0 - ICH at 33Mhz*/
1125	{
1126		.flags		= PIIX_PATA_FLAGS,
1127		.pio_mask	= ATA_PIO4,
1128		.mwdma_mask	= ATA_MWDMA12_ONLY, /* Check: maybe MWDMA0 is ok  */
1129		.udma_mask	= ATA_UDMA2,
1130		.port_ops	= &ich_pata_ops,
1131	},
1132
1133	[ich_pata_66] =		/* ICH controllers up to 66MHz */
1134	{
1135		.flags		= PIIX_PATA_FLAGS,
1136		.pio_mask	= ATA_PIO4,
1137		.mwdma_mask	= ATA_MWDMA12_ONLY, /* MWDMA0 is broken on chip */
1138		.udma_mask	= ATA_UDMA4,
1139		.port_ops	= &ich_pata_ops,
1140	},
1141
1142	[ich_pata_100] =
1143	{
1144		.flags		= PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
1145		.pio_mask	= ATA_PIO4,
1146		.mwdma_mask	= ATA_MWDMA12_ONLY,
1147		.udma_mask	= ATA_UDMA5,
1148		.port_ops	= &ich_pata_ops,
1149	},
1150
1151	[ich_pata_100_nomwdma1] =
1152	{
1153		.flags		= PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
1154		.pio_mask	= ATA_PIO4,
1155		.mwdma_mask	= ATA_MWDMA2_ONLY,
1156		.udma_mask	= ATA_UDMA5,
1157		.port_ops	= &ich_pata_ops,
1158	},
1159
1160	[ich5_sata] =
1161	{
1162		.flags		= PIIX_SATA_FLAGS,
1163		.pio_mask	= ATA_PIO4,
1164		.mwdma_mask	= ATA_MWDMA2,
1165		.udma_mask	= ATA_UDMA6,
1166		.port_ops	= &piix_sata_ops,
1167	},
1168
1169	[ich6_sata] =
1170	{
1171		.flags		= PIIX_SATA_FLAGS,
1172		.pio_mask	= ATA_PIO4,
1173		.mwdma_mask	= ATA_MWDMA2,
1174		.udma_mask	= ATA_UDMA6,
1175		.port_ops	= &piix_sata_ops,
1176	},
1177
1178	[ich6m_sata] =
1179	{
1180		.flags		= PIIX_SATA_FLAGS,
1181		.pio_mask	= ATA_PIO4,
1182		.mwdma_mask	= ATA_MWDMA2,
1183		.udma_mask	= ATA_UDMA6,
1184		.port_ops	= &piix_sata_ops,
1185	},
1186
1187	[ich8_sata] =
1188	{
1189		.flags		= PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
1190		.pio_mask	= ATA_PIO4,
1191		.mwdma_mask	= ATA_MWDMA2,
1192		.udma_mask	= ATA_UDMA6,
1193		.port_ops	= &piix_sata_ops,
1194	},
1195
1196	[ich8_2port_sata] =
1197	{
1198		.flags		= PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
1199		.pio_mask	= ATA_PIO4,
1200		.mwdma_mask	= ATA_MWDMA2,
1201		.udma_mask	= ATA_UDMA6,
1202		.port_ops	= &piix_sata_ops,
1203	},
1204
1205	[tolapai_sata] =
1206	{
1207		.flags		= PIIX_SATA_FLAGS,
1208		.pio_mask	= ATA_PIO4,
1209		.mwdma_mask	= ATA_MWDMA2,
1210		.udma_mask	= ATA_UDMA6,
1211		.port_ops	= &piix_sata_ops,
1212	},
1213
1214	[ich8m_apple_sata] =
1215	{
1216		.flags		= PIIX_SATA_FLAGS,
1217		.pio_mask	= ATA_PIO4,
1218		.mwdma_mask	= ATA_MWDMA2,
1219		.udma_mask	= ATA_UDMA6,
1220		.port_ops	= &piix_sata_ops,
1221	},
1222
1223	[piix_pata_vmw] =
1224	{
1225		.flags		= PIIX_PATA_FLAGS,
1226		.pio_mask	= ATA_PIO4,
1227		.mwdma_mask	= ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
1228		.udma_mask	= ATA_UDMA2,
1229		.port_ops	= &piix_vmw_ops,
1230	},
1231
1232	/*
1233	 * some Sandybridge chipsets have broken 32 mode up to now,
1234	 * see https://bugzilla.kernel.org/show_bug.cgi?id=40592
1235	 */
1236	[ich8_sata_snb] =
1237	{
1238		.flags		= PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR | PIIX_FLAG_PIO16,
1239		.pio_mask	= ATA_PIO4,
1240		.mwdma_mask	= ATA_MWDMA2,
1241		.udma_mask	= ATA_UDMA6,
1242		.port_ops	= &piix_sata_ops,
1243	},
1244
1245	[ich8_2port_sata_snb] =
1246	{
1247		.flags		= PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR
1248					| PIIX_FLAG_PIO16,
1249		.pio_mask	= ATA_PIO4,
1250		.mwdma_mask	= ATA_MWDMA2,
1251		.udma_mask	= ATA_UDMA6,
1252		.port_ops	= &piix_sata_ops,
1253	},
1254
1255	[ich8_2port_sata_byt] =
1256	{
1257		.flags          = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR | PIIX_FLAG_PIO16,
1258		.pio_mask       = ATA_PIO4,
1259		.mwdma_mask     = ATA_MWDMA2,
1260		.udma_mask      = ATA_UDMA6,
1261		.port_ops       = &piix_sata_ops,
1262	},
1263
1264};
1265
1266#define AHCI_PCI_BAR 5
1267#define AHCI_GLOBAL_CTL 0x04
1268#define AHCI_ENABLE (1 << 31)
1269static int piix_disable_ahci(struct pci_dev *pdev)
1270{
1271	void __iomem *mmio;
1272	u32 tmp;
1273	int rc = 0;
1274
1275	/* BUG: pci_enable_device has not yet been called.  This
1276	 * works because this device is usually set up by BIOS.
1277	 */
1278
1279	if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
1280	    !pci_resource_len(pdev, AHCI_PCI_BAR))
1281		return 0;
1282
1283	mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
1284	if (!mmio)
1285		return -ENOMEM;
1286
1287	tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1288	if (tmp & AHCI_ENABLE) {
1289		tmp &= ~AHCI_ENABLE;
1290		iowrite32(tmp, mmio + AHCI_GLOBAL_CTL);
1291
1292		tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1293		if (tmp & AHCI_ENABLE)
1294			rc = -EIO;
1295	}
1296
1297	pci_iounmap(pdev, mmio);
1298	return rc;
1299}
1300
1301/**
1302 *	piix_check_450nx_errata	-	Check for problem 450NX setup
1303 *	@ata_dev: the PCI device to check
1304 *
1305 *	Check for the present of 450NX errata #19 and errata #25. If
1306 *	they are found return an error code so we can turn off DMA
1307 */
1308
1309static int piix_check_450nx_errata(struct pci_dev *ata_dev)
1310{
1311	struct pci_dev *pdev = NULL;
1312	u16 cfg;
1313	int no_piix_dma = 0;
1314
1315	while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) {
1316		/* Look for 450NX PXB. Check for problem configurations
1317		   A PCI quirk checks bit 6 already */
1318		pci_read_config_word(pdev, 0x41, &cfg);
1319		/* Only on the original revision: IDE DMA can hang */
1320		if (pdev->revision == 0x00)
1321			no_piix_dma = 1;
1322		/* On all revisions below 5 PXB bus lock must be disabled for IDE */
1323		else if (cfg & (1<<14) && pdev->revision < 5)
1324			no_piix_dma = 2;
1325	}
1326	if (no_piix_dma)
1327		dev_warn(&ata_dev->dev,
1328			 "450NX errata present, disabling IDE DMA%s\n",
1329			 no_piix_dma == 2 ? " - a BIOS update may resolve this"
1330			 : "");
1331
1332	return no_piix_dma;
1333}
1334
1335static void piix_init_pcs(struct ata_host *host,
1336			  const struct piix_map_db *map_db)
1337{
1338	struct pci_dev *pdev = to_pci_dev(host->dev);
1339	u16 pcs, new_pcs;
1340
1341	pci_read_config_word(pdev, ICH5_PCS, &pcs);
1342
1343	new_pcs = pcs | map_db->port_enable;
1344
1345	if (new_pcs != pcs) {
1346		DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
1347		pci_write_config_word(pdev, ICH5_PCS, new_pcs);
1348		msleep(150);
1349	}
1350}
1351
1352static const int *piix_init_sata_map(struct pci_dev *pdev,
1353				     struct ata_port_info *pinfo,
1354				     const struct piix_map_db *map_db)
1355{
1356	const int *map;
1357	int i, invalid_map = 0;
1358	u8 map_value;
1359	char buf[32];
1360	char *p = buf, *end = buf + sizeof(buf);
1361
1362	pci_read_config_byte(pdev, ICH5_PMR, &map_value);
1363
1364	map = map_db->map[map_value & map_db->mask];
1365
1366	for (i = 0; i < 4; i++) {
1367		switch (map[i]) {
1368		case RV:
1369			invalid_map = 1;
1370			p += scnprintf(p, end - p, " XX");
1371			break;
1372
1373		case NA:
1374			p += scnprintf(p, end - p, " --");
1375			break;
1376
1377		case IDE:
1378			WARN_ON((i & 1) || map[i + 1] != IDE);
1379			pinfo[i / 2] = piix_port_info[ich_pata_100];
1380			i++;
1381			p += scnprintf(p, end - p, " IDE IDE");
1382			break;
1383
1384		default:
1385			p += scnprintf(p, end - p, " P%d", map[i]);
1386			if (i & 1)
1387				pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
1388			break;
1389		}
1390	}
1391	dev_info(&pdev->dev, "MAP [%s ]\n", buf);
1392
1393	if (invalid_map)
1394		dev_err(&pdev->dev, "invalid MAP value %u\n", map_value);
1395
1396	return map;
1397}
1398
1399static bool piix_no_sidpr(struct ata_host *host)
1400{
1401	struct pci_dev *pdev = to_pci_dev(host->dev);
1402
1403	/*
1404	 * Samsung DB-P70 only has three ATA ports exposed and
1405	 * curiously the unconnected first port reports link online
1406	 * while not responding to SRST protocol causing excessive
1407	 * detection delay.
1408	 *
1409	 * Unfortunately, the system doesn't carry enough DMI
1410	 * information to identify the machine but does have subsystem
1411	 * vendor and device set.  As it's unclear whether the
1412	 * subsystem vendor/device is used only for this specific
1413	 * board, the port can't be disabled solely with the
1414	 * information; however, turning off SIDPR access works around
1415	 * the problem.  Turn it off.
1416	 *
1417	 * This problem is reported in bnc#441240.
1418	 *
1419	 * https://bugzilla.novell.com/show_bug.cgi?id=441420
1420	 */
1421	if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2920 &&
1422	    pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG &&
1423	    pdev->subsystem_device == 0xb049) {
1424		dev_warn(host->dev,
1425			 "Samsung DB-P70 detected, disabling SIDPR\n");
1426		return true;
1427	}
1428
1429	return false;
1430}
1431
1432static int piix_init_sidpr(struct ata_host *host)
1433{
1434	struct pci_dev *pdev = to_pci_dev(host->dev);
1435	struct piix_host_priv *hpriv = host->private_data;
1436	struct ata_link *link0 = &host->ports[0]->link;
1437	u32 scontrol;
1438	int i, rc;
1439
1440	/* check for availability */
1441	for (i = 0; i < 4; i++)
1442		if (hpriv->map[i] == IDE)
1443			return 0;
1444
1445	/* is it blacklisted? */
1446	if (piix_no_sidpr(host))
1447		return 0;
1448
1449	if (!(host->ports[0]->flags & PIIX_FLAG_SIDPR))
1450		return 0;
1451
1452	if (pci_resource_start(pdev, PIIX_SIDPR_BAR) == 0 ||
1453	    pci_resource_len(pdev, PIIX_SIDPR_BAR) != PIIX_SIDPR_LEN)
1454		return 0;
1455
1456	if (pcim_iomap_regions(pdev, 1 << PIIX_SIDPR_BAR, DRV_NAME))
1457		return 0;
1458
1459	hpriv->sidpr = pcim_iomap_table(pdev)[PIIX_SIDPR_BAR];
1460
1461	/* SCR access via SIDPR doesn't work on some configurations.
1462	 * Give it a test drive by inhibiting power save modes which
1463	 * we'll do anyway.
1464	 */
1465	piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
1466
1467	/* if IPM is already 3, SCR access is probably working.  Don't
1468	 * un-inhibit power save modes as BIOS might have inhibited
1469	 * them for a reason.
1470	 */
1471	if ((scontrol & 0xf00) != 0x300) {
1472		scontrol |= 0x300;
1473		piix_sidpr_scr_write(link0, SCR_CONTROL, scontrol);
1474		piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
1475
1476		if ((scontrol & 0xf00) != 0x300) {
1477			dev_info(host->dev,
1478				 "SCR access via SIDPR is available but doesn't work\n");
1479			return 0;
1480		}
1481	}
1482
1483	/* okay, SCRs available, set ops and ask libata for slave_link */
1484	for (i = 0; i < 2; i++) {
1485		struct ata_port *ap = host->ports[i];
1486
1487		ap->ops = &piix_sidpr_sata_ops;
1488
1489		if (ap->flags & ATA_FLAG_SLAVE_POSS) {
1490			rc = ata_slave_link_init(ap);
1491			if (rc)
1492				return rc;
1493		}
1494	}
1495
1496	return 0;
1497}
1498
1499static void piix_iocfg_bit18_quirk(struct ata_host *host)
1500{
1501	static const struct dmi_system_id sysids[] = {
1502		{
1503			/* Clevo M570U sets IOCFG bit 18 if the cdrom
1504			 * isn't used to boot the system which
1505			 * disables the channel.
1506			 */
1507			.ident = "M570U",
1508			.matches = {
1509				DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."),
1510				DMI_MATCH(DMI_PRODUCT_NAME, "M570U"),
1511			},
1512		},
1513
1514		{ }	/* terminate list */
1515	};
1516	struct pci_dev *pdev = to_pci_dev(host->dev);
1517	struct piix_host_priv *hpriv = host->private_data;
1518
1519	if (!dmi_check_system(sysids))
1520		return;
1521
1522	/* The datasheet says that bit 18 is NOOP but certain systems
1523	 * seem to use it to disable a channel.  Clear the bit on the
1524	 * affected systems.
1525	 */
1526	if (hpriv->saved_iocfg & (1 << 18)) {
1527		dev_info(&pdev->dev, "applying IOCFG bit18 quirk\n");
1528		pci_write_config_dword(pdev, PIIX_IOCFG,
1529				       hpriv->saved_iocfg & ~(1 << 18));
1530	}
1531}
1532
1533static bool piix_broken_system_poweroff(struct pci_dev *pdev)
1534{
1535	static const struct dmi_system_id broken_systems[] = {
1536		{
1537			.ident = "HP Compaq 2510p",
1538			.matches = {
1539				DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1540				DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 2510p"),
1541			},
1542			/* PCI slot number of the controller */
1543			.driver_data = (void *)0x1FUL,
1544		},
1545		{
1546			.ident = "HP Compaq nc6000",
1547			.matches = {
1548				DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1549				DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nc6000"),
1550			},
1551			/* PCI slot number of the controller */
1552			.driver_data = (void *)0x1FUL,
1553		},
1554
1555		{ }	/* terminate list */
1556	};
1557	const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1558
1559	if (dmi) {
1560		unsigned long slot = (unsigned long)dmi->driver_data;
1561		/* apply the quirk only to on-board controllers */
1562		return slot == PCI_SLOT(pdev->devfn);
1563	}
1564
1565	return false;
1566}
1567
1568static int prefer_ms_hyperv = 1;
1569module_param(prefer_ms_hyperv, int, 0);
1570MODULE_PARM_DESC(prefer_ms_hyperv,
1571	"Prefer Hyper-V paravirtualization drivers instead of ATA, "
1572	"0 - Use ATA drivers, "
1573	"1 (Default) - Use the paravirtualization drivers.");
1574
1575static void piix_ignore_devices_quirk(struct ata_host *host)
1576{
1577#if IS_ENABLED(CONFIG_HYPERV_STORAGE)
1578	static const struct dmi_system_id ignore_hyperv[] = {
1579		{
1580			/* On Hyper-V hypervisors the disks are exposed on
1581			 * both the emulated SATA controller and on the
1582			 * paravirtualised drivers.  The CD/DVD devices
1583			 * are only exposed on the emulated controller.
1584			 * Request we ignore ATA devices on this host.
1585			 */
1586			.ident = "Hyper-V Virtual Machine",
1587			.matches = {
1588				DMI_MATCH(DMI_SYS_VENDOR,
1589						"Microsoft Corporation"),
1590				DMI_MATCH(DMI_PRODUCT_NAME, "Virtual Machine"),
1591			},
1592		},
1593		{ }	/* terminate list */
1594	};
1595	static const struct dmi_system_id allow_virtual_pc[] = {
1596		{
1597			/* In MS Virtual PC guests the DMI ident is nearly
1598			 * identical to a Hyper-V guest. One difference is the
1599			 * product version which is used here to identify
1600			 * a Virtual PC guest. This entry allows ata_piix to
1601			 * drive the emulated hardware.
1602			 */
1603			.ident = "MS Virtual PC 2007",
1604			.matches = {
1605				DMI_MATCH(DMI_SYS_VENDOR,
1606						"Microsoft Corporation"),
1607				DMI_MATCH(DMI_PRODUCT_NAME, "Virtual Machine"),
1608				DMI_MATCH(DMI_PRODUCT_VERSION, "VS2005R2"),
1609			},
1610		},
1611		{ }	/* terminate list */
1612	};
1613	const struct dmi_system_id *ignore = dmi_first_match(ignore_hyperv);
1614	const struct dmi_system_id *allow = dmi_first_match(allow_virtual_pc);
1615
1616	if (ignore && !allow && prefer_ms_hyperv) {
1617		host->flags |= ATA_HOST_IGNORE_ATA;
1618		dev_info(host->dev, "%s detected, ATA device ignore set\n",
1619			ignore->ident);
1620	}
1621#endif
1622}
1623
1624/**
1625 *	piix_init_one - Register PIIX ATA PCI device with kernel services
1626 *	@pdev: PCI device to register
1627 *	@ent: Entry in piix_pci_tbl matching with @pdev
1628 *
1629 *	Called from kernel PCI layer.  We probe for combined mode (sigh),
1630 *	and then hand over control to libata, for it to do the rest.
1631 *
1632 *	LOCKING:
1633 *	Inherited from PCI layer (may sleep).
1634 *
1635 *	RETURNS:
1636 *	Zero on success, or -ERRNO value.
1637 */
1638
1639static int piix_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1640{
1641	struct device *dev = &pdev->dev;
1642	struct ata_port_info port_info[2];
1643	const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] };
1644	struct scsi_host_template *sht = &piix_sht;
1645	unsigned long port_flags;
1646	struct ata_host *host;
1647	struct piix_host_priv *hpriv;
1648	int rc;
1649
1650	ata_print_version_once(&pdev->dev, DRV_VERSION);
1651
1652	/* no hotplugging support for later devices (FIXME) */
1653	if (!in_module_init && ent->driver_data >= ich5_sata)
1654		return -ENODEV;
1655
1656	if (piix_broken_system_poweroff(pdev)) {
1657		piix_port_info[ent->driver_data].flags |=
1658				ATA_FLAG_NO_POWEROFF_SPINDOWN |
1659					ATA_FLAG_NO_HIBERNATE_SPINDOWN;
1660		dev_info(&pdev->dev, "quirky BIOS, skipping spindown "
1661				"on poweroff and hibernation\n");
1662	}
1663
1664	port_info[0] = piix_port_info[ent->driver_data];
1665	port_info[1] = piix_port_info[ent->driver_data];
1666
1667	port_flags = port_info[0].flags;
1668
1669	/* enable device and prepare host */
1670	rc = pcim_enable_device(pdev);
1671	if (rc)
1672		return rc;
1673
1674	hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1675	if (!hpriv)
1676		return -ENOMEM;
1677
1678	/* Save IOCFG, this will be used for cable detection, quirk
1679	 * detection and restoration on detach.  This is necessary
1680	 * because some ACPI implementations mess up cable related
1681	 * bits on _STM.  Reported on kernel bz#11879.
1682	 */
1683	pci_read_config_dword(pdev, PIIX_IOCFG, &hpriv->saved_iocfg);
1684
1685	/* ICH6R may be driven by either ata_piix or ahci driver
1686	 * regardless of BIOS configuration.  Make sure AHCI mode is
1687	 * off.
1688	 */
1689	if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2652) {
1690		rc = piix_disable_ahci(pdev);
1691		if (rc)
1692			return rc;
1693	}
1694
1695	/* SATA map init can change port_info, do it before prepping host */
1696	if (port_flags & ATA_FLAG_SATA)
1697		hpriv->map = piix_init_sata_map(pdev, port_info,
1698					piix_map_db_table[ent->driver_data]);
1699
1700	rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
1701	if (rc)
1702		return rc;
1703	host->private_data = hpriv;
1704
1705	/* initialize controller */
1706	if (port_flags & ATA_FLAG_SATA) {
1707		piix_init_pcs(host, piix_map_db_table[ent->driver_data]);
1708		rc = piix_init_sidpr(host);
1709		if (rc)
1710			return rc;
1711		if (host->ports[0]->ops == &piix_sidpr_sata_ops)
1712			sht = &piix_sidpr_sht;
1713	}
1714
1715	/* apply IOCFG bit18 quirk */
1716	piix_iocfg_bit18_quirk(host);
1717
1718	/* On ICH5, some BIOSen disable the interrupt using the
1719	 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
1720	 * On ICH6, this bit has the same effect, but only when
1721	 * MSI is disabled (and it is disabled, as we don't use
1722	 * message-signalled interrupts currently).
1723	 */
1724	if (port_flags & PIIX_FLAG_CHECKINTR)
1725		pci_intx(pdev, 1);
1726
1727	if (piix_check_450nx_errata(pdev)) {
1728		/* This writes into the master table but it does not
1729		   really matter for this errata as we will apply it to
1730		   all the PIIX devices on the board */
1731		host->ports[0]->mwdma_mask = 0;
1732		host->ports[0]->udma_mask = 0;
1733		host->ports[1]->mwdma_mask = 0;
1734		host->ports[1]->udma_mask = 0;
1735	}

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