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/drivers/ata/sata_qstor.c

http://github.com/mirrors/linux
C | 608 lines | 452 code | 107 blank | 49 comment | 37 complexity | 9401c055d447e892546462c6d2d1dd01 MD5 | raw file
  1// SPDX-License-Identifier: GPL-2.0-or-later
  2/*
  3 *  sata_qstor.c - Pacific Digital Corporation QStor SATA
  4 *
  5 *  Maintained by:  Mark Lord <mlord@pobox.com>
  6 *
  7 *  Copyright 2005 Pacific Digital Corporation.
  8 *  (OSL/GPL code release authorized by Jalil Fadavi).
  9 *
 10 *  libata documentation is available via 'make {ps|pdf}docs',
 11 *  as Documentation/driver-api/libata.rst
 12 */
 13
 14#include <linux/kernel.h>
 15#include <linux/module.h>
 16#include <linux/gfp.h>
 17#include <linux/pci.h>
 18#include <linux/blkdev.h>
 19#include <linux/delay.h>
 20#include <linux/interrupt.h>
 21#include <linux/device.h>
 22#include <scsi/scsi_host.h>
 23#include <linux/libata.h>
 24
 25#define DRV_NAME	"sata_qstor"
 26#define DRV_VERSION	"0.09"
 27
 28enum {
 29	QS_MMIO_BAR		= 4,
 30
 31	QS_PORTS		= 4,
 32	QS_MAX_PRD		= LIBATA_MAX_PRD,
 33	QS_CPB_ORDER		= 6,
 34	QS_CPB_BYTES		= (1 << QS_CPB_ORDER),
 35	QS_PRD_BYTES		= QS_MAX_PRD * 16,
 36	QS_PKT_BYTES		= QS_CPB_BYTES + QS_PRD_BYTES,
 37
 38	/* global register offsets */
 39	QS_HCF_CNFG3		= 0x0003, /* host configuration offset */
 40	QS_HID_HPHY		= 0x0004, /* host physical interface info */
 41	QS_HCT_CTRL		= 0x00e4, /* global interrupt mask offset */
 42	QS_HST_SFF		= 0x0100, /* host status fifo offset */
 43	QS_HVS_SERD3		= 0x0393, /* PHY enable offset */
 44
 45	/* global control bits */
 46	QS_HPHY_64BIT		= (1 << 1), /* 64-bit bus detected */
 47	QS_CNFG3_GSRST		= 0x01,     /* global chip reset */
 48	QS_SERD3_PHY_ENA	= 0xf0,     /* PHY detection ENAble*/
 49
 50	/* per-channel register offsets */
 51	QS_CCF_CPBA		= 0x0710, /* chan CPB base address */
 52	QS_CCF_CSEP		= 0x0718, /* chan CPB separation factor */
 53	QS_CFC_HUFT		= 0x0800, /* host upstream fifo threshold */
 54	QS_CFC_HDFT		= 0x0804, /* host downstream fifo threshold */
 55	QS_CFC_DUFT		= 0x0808, /* dev upstream fifo threshold */
 56	QS_CFC_DDFT		= 0x080c, /* dev downstream fifo threshold */
 57	QS_CCT_CTR0		= 0x0900, /* chan control-0 offset */
 58	QS_CCT_CTR1		= 0x0901, /* chan control-1 offset */
 59	QS_CCT_CFF		= 0x0a00, /* chan command fifo offset */
 60
 61	/* channel control bits */
 62	QS_CTR0_REG		= (1 << 1),   /* register mode (vs. pkt mode) */
 63	QS_CTR0_CLER		= (1 << 2),   /* clear channel errors */
 64	QS_CTR1_RDEV		= (1 << 1),   /* sata phy/comms reset */
 65	QS_CTR1_RCHN		= (1 << 4),   /* reset channel logic */
 66	QS_CCF_RUN_PKT		= 0x107,      /* RUN a new dma PKT */
 67
 68	/* pkt sub-field headers */
 69	QS_HCB_HDR		= 0x01,   /* Host Control Block header */
 70	QS_DCB_HDR		= 0x02,   /* Device Control Block header */
 71
 72	/* pkt HCB flag bits */
 73	QS_HF_DIRO		= (1 << 0),   /* data DIRection Out */
 74	QS_HF_DAT		= (1 << 3),   /* DATa pkt */
 75	QS_HF_IEN		= (1 << 4),   /* Interrupt ENable */
 76	QS_HF_VLD		= (1 << 5),   /* VaLiD pkt */
 77
 78	/* pkt DCB flag bits */
 79	QS_DF_PORD		= (1 << 2),   /* Pio OR Dma */
 80	QS_DF_ELBA		= (1 << 3),   /* Extended LBA (lba48) */
 81
 82	/* PCI device IDs */
 83	board_2068_idx		= 0,	/* QStor 4-port SATA/RAID */
 84};
 85
 86enum {
 87	QS_DMA_BOUNDARY		= ~0UL
 88};
 89
 90typedef enum { qs_state_mmio, qs_state_pkt } qs_state_t;
 91
 92struct qs_port_priv {
 93	u8			*pkt;
 94	dma_addr_t		pkt_dma;
 95	qs_state_t		state;
 96};
 97
 98static int qs_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
 99static int qs_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
100static int qs_ata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
101static int qs_port_start(struct ata_port *ap);
102static void qs_host_stop(struct ata_host *host);
103static enum ata_completion_errors qs_qc_prep(struct ata_queued_cmd *qc);
104static unsigned int qs_qc_issue(struct ata_queued_cmd *qc);
105static int qs_check_atapi_dma(struct ata_queued_cmd *qc);
106static void qs_freeze(struct ata_port *ap);
107static void qs_thaw(struct ata_port *ap);
108static int qs_prereset(struct ata_link *link, unsigned long deadline);
109static void qs_error_handler(struct ata_port *ap);
110
111static struct scsi_host_template qs_ata_sht = {
112	ATA_BASE_SHT(DRV_NAME),
113	.sg_tablesize		= QS_MAX_PRD,
114	.dma_boundary		= QS_DMA_BOUNDARY,
115};
116
117static struct ata_port_operations qs_ata_ops = {
118	.inherits		= &ata_sff_port_ops,
119
120	.check_atapi_dma	= qs_check_atapi_dma,
121	.qc_prep		= qs_qc_prep,
122	.qc_issue		= qs_qc_issue,
123
124	.freeze			= qs_freeze,
125	.thaw			= qs_thaw,
126	.prereset		= qs_prereset,
127	.softreset		= ATA_OP_NULL,
128	.error_handler		= qs_error_handler,
129	.lost_interrupt		= ATA_OP_NULL,
130
131	.scr_read		= qs_scr_read,
132	.scr_write		= qs_scr_write,
133
134	.port_start		= qs_port_start,
135	.host_stop		= qs_host_stop,
136};
137
138static const struct ata_port_info qs_port_info[] = {
139	/* board_2068_idx */
140	{
141		.flags		= ATA_FLAG_SATA | ATA_FLAG_PIO_POLLING,
142		.pio_mask	= ATA_PIO4_ONLY,
143		.udma_mask	= ATA_UDMA6,
144		.port_ops	= &qs_ata_ops,
145	},
146};
147
148static const struct pci_device_id qs_ata_pci_tbl[] = {
149	{ PCI_VDEVICE(PDC, 0x2068), board_2068_idx },
150
151	{ }	/* terminate list */
152};
153
154static struct pci_driver qs_ata_pci_driver = {
155	.name			= DRV_NAME,
156	.id_table		= qs_ata_pci_tbl,
157	.probe			= qs_ata_init_one,
158	.remove			= ata_pci_remove_one,
159};
160
161static void __iomem *qs_mmio_base(struct ata_host *host)
162{
163	return host->iomap[QS_MMIO_BAR];
164}
165
166static int qs_check_atapi_dma(struct ata_queued_cmd *qc)
167{
168	return 1;	/* ATAPI DMA not supported */
169}
170
171static inline void qs_enter_reg_mode(struct ata_port *ap)
172{
173	u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000);
174	struct qs_port_priv *pp = ap->private_data;
175
176	pp->state = qs_state_mmio;
177	writeb(QS_CTR0_REG, chan + QS_CCT_CTR0);
178	readb(chan + QS_CCT_CTR0);        /* flush */
179}
180
181static inline void qs_reset_channel_logic(struct ata_port *ap)
182{
183	u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000);
184
185	writeb(QS_CTR1_RCHN, chan + QS_CCT_CTR1);
186	readb(chan + QS_CCT_CTR0);        /* flush */
187	qs_enter_reg_mode(ap);
188}
189
190static void qs_freeze(struct ata_port *ap)
191{
192	u8 __iomem *mmio_base = qs_mmio_base(ap->host);
193
194	writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
195	qs_enter_reg_mode(ap);
196}
197
198static void qs_thaw(struct ata_port *ap)
199{
200	u8 __iomem *mmio_base = qs_mmio_base(ap->host);
201
202	qs_enter_reg_mode(ap);
203	writeb(1, mmio_base + QS_HCT_CTRL); /* enable host interrupts */
204}
205
206static int qs_prereset(struct ata_link *link, unsigned long deadline)
207{
208	struct ata_port *ap = link->ap;
209
210	qs_reset_channel_logic(ap);
211	return ata_sff_prereset(link, deadline);
212}
213
214static int qs_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
215{
216	if (sc_reg > SCR_CONTROL)
217		return -EINVAL;
218	*val = readl(link->ap->ioaddr.scr_addr + (sc_reg * 8));
219	return 0;
220}
221
222static void qs_error_handler(struct ata_port *ap)
223{
224	qs_enter_reg_mode(ap);
225	ata_sff_error_handler(ap);
226}
227
228static int qs_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
229{
230	if (sc_reg > SCR_CONTROL)
231		return -EINVAL;
232	writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 8));
233	return 0;
234}
235
236static unsigned int qs_fill_sg(struct ata_queued_cmd *qc)
237{
238	struct scatterlist *sg;
239	struct ata_port *ap = qc->ap;
240	struct qs_port_priv *pp = ap->private_data;
241	u8 *prd = pp->pkt + QS_CPB_BYTES;
242	unsigned int si;
243
244	for_each_sg(qc->sg, sg, qc->n_elem, si) {
245		u64 addr;
246		u32 len;
247
248		addr = sg_dma_address(sg);
249		*(__le64 *)prd = cpu_to_le64(addr);
250		prd += sizeof(u64);
251
252		len = sg_dma_len(sg);
253		*(__le32 *)prd = cpu_to_le32(len);
254		prd += sizeof(u64);
255
256		VPRINTK("PRD[%u] = (0x%llX, 0x%X)\n", si,
257					(unsigned long long)addr, len);
258	}
259
260	return si;
261}
262
263static enum ata_completion_errors qs_qc_prep(struct ata_queued_cmd *qc)
264{
265	struct qs_port_priv *pp = qc->ap->private_data;
266	u8 dflags = QS_DF_PORD, *buf = pp->pkt;
267	u8 hflags = QS_HF_DAT | QS_HF_IEN | QS_HF_VLD;
268	u64 addr;
269	unsigned int nelem;
270
271	VPRINTK("ENTER\n");
272
273	qs_enter_reg_mode(qc->ap);
274	if (qc->tf.protocol != ATA_PROT_DMA)
275		return AC_ERR_OK;
276
277	nelem = qs_fill_sg(qc);
278
279	if ((qc->tf.flags & ATA_TFLAG_WRITE))
280		hflags |= QS_HF_DIRO;
281	if ((qc->tf.flags & ATA_TFLAG_LBA48))
282		dflags |= QS_DF_ELBA;
283
284	/* host control block (HCB) */
285	buf[ 0] = QS_HCB_HDR;
286	buf[ 1] = hflags;
287	*(__le32 *)(&buf[ 4]) = cpu_to_le32(qc->nbytes);
288	*(__le32 *)(&buf[ 8]) = cpu_to_le32(nelem);
289	addr = ((u64)pp->pkt_dma) + QS_CPB_BYTES;
290	*(__le64 *)(&buf[16]) = cpu_to_le64(addr);
291
292	/* device control block (DCB) */
293	buf[24] = QS_DCB_HDR;
294	buf[28] = dflags;
295
296	/* frame information structure (FIS) */
297	ata_tf_to_fis(&qc->tf, 0, 1, &buf[32]);
298
299	return AC_ERR_OK;
300}
301
302static inline void qs_packet_start(struct ata_queued_cmd *qc)
303{
304	struct ata_port *ap = qc->ap;
305	u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000);
306
307	VPRINTK("ENTER, ap %p\n", ap);
308
309	writeb(QS_CTR0_CLER, chan + QS_CCT_CTR0);
310	wmb();                             /* flush PRDs and pkt to memory */
311	writel(QS_CCF_RUN_PKT, chan + QS_CCT_CFF);
312	readl(chan + QS_CCT_CFF);          /* flush */
313}
314
315static unsigned int qs_qc_issue(struct ata_queued_cmd *qc)
316{
317	struct qs_port_priv *pp = qc->ap->private_data;
318
319	switch (qc->tf.protocol) {
320	case ATA_PROT_DMA:
321		pp->state = qs_state_pkt;
322		qs_packet_start(qc);
323		return 0;
324
325	case ATAPI_PROT_DMA:
326		BUG();
327		break;
328
329	default:
330		break;
331	}
332
333	pp->state = qs_state_mmio;
334	return ata_sff_qc_issue(qc);
335}
336
337static void qs_do_or_die(struct ata_queued_cmd *qc, u8 status)
338{
339	qc->err_mask |= ac_err_mask(status);
340
341	if (!qc->err_mask) {
342		ata_qc_complete(qc);
343	} else {
344		struct ata_port    *ap  = qc->ap;
345		struct ata_eh_info *ehi = &ap->link.eh_info;
346
347		ata_ehi_clear_desc(ehi);
348		ata_ehi_push_desc(ehi, "status 0x%02X", status);
349
350		if (qc->err_mask == AC_ERR_DEV)
351			ata_port_abort(ap);
352		else
353			ata_port_freeze(ap);
354	}
355}
356
357static inline unsigned int qs_intr_pkt(struct ata_host *host)
358{
359	unsigned int handled = 0;
360	u8 sFFE;
361	u8 __iomem *mmio_base = qs_mmio_base(host);
362
363	do {
364		u32 sff0 = readl(mmio_base + QS_HST_SFF);
365		u32 sff1 = readl(mmio_base + QS_HST_SFF + 4);
366		u8 sEVLD = (sff1 >> 30) & 0x01;	/* valid flag */
367		sFFE  = sff1 >> 31;		/* empty flag */
368
369		if (sEVLD) {
370			u8 sDST = sff0 >> 16;	/* dev status */
371			u8 sHST = sff1 & 0x3f;	/* host status */
372			unsigned int port_no = (sff1 >> 8) & 0x03;
373			struct ata_port *ap = host->ports[port_no];
374			struct qs_port_priv *pp = ap->private_data;
375			struct ata_queued_cmd *qc;
376
377			DPRINTK("SFF=%08x%08x: sCHAN=%u sHST=%d sDST=%02x\n",
378					sff1, sff0, port_no, sHST, sDST);
379			handled = 1;
380			if (!pp || pp->state != qs_state_pkt)
381				continue;
382			qc = ata_qc_from_tag(ap, ap->link.active_tag);
383			if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
384				switch (sHST) {
385				case 0: /* successful CPB */
386				case 3: /* device error */
387					qs_enter_reg_mode(qc->ap);
388					qs_do_or_die(qc, sDST);
389					break;
390				default:
391					break;
392				}
393			}
394		}
395	} while (!sFFE);
396	return handled;
397}
398
399static inline unsigned int qs_intr_mmio(struct ata_host *host)
400{
401	unsigned int handled = 0, port_no;
402
403	for (port_no = 0; port_no < host->n_ports; ++port_no) {
404		struct ata_port *ap = host->ports[port_no];
405		struct qs_port_priv *pp = ap->private_data;
406		struct ata_queued_cmd *qc;
407
408		qc = ata_qc_from_tag(ap, ap->link.active_tag);
409		if (!qc) {
410			/*
411			 * The qstor hardware generates spurious
412			 * interrupts from time to time when switching
413			 * in and out of packet mode.  There's no
414			 * obvious way to know if we're here now due
415			 * to that, so just ack the irq and pretend we
416			 * knew it was ours.. (ugh).  This does not
417			 * affect packet mode.
418			 */
419			ata_sff_check_status(ap);
420			handled = 1;
421			continue;
422		}
423
424		if (!pp || pp->state != qs_state_mmio)
425			continue;
426		if (!(qc->tf.flags & ATA_TFLAG_POLLING))
427			handled |= ata_sff_port_intr(ap, qc);
428	}
429	return handled;
430}
431
432static irqreturn_t qs_intr(int irq, void *dev_instance)
433{
434	struct ata_host *host = dev_instance;
435	unsigned int handled = 0;
436	unsigned long flags;
437
438	VPRINTK("ENTER\n");
439
440	spin_lock_irqsave(&host->lock, flags);
441	handled  = qs_intr_pkt(host) | qs_intr_mmio(host);
442	spin_unlock_irqrestore(&host->lock, flags);
443
444	VPRINTK("EXIT\n");
445
446	return IRQ_RETVAL(handled);
447}
448
449static void qs_ata_setup_port(struct ata_ioports *port, void __iomem *base)
450{
451	port->cmd_addr		=
452	port->data_addr		= base + 0x400;
453	port->error_addr	=
454	port->feature_addr	= base + 0x408; /* hob_feature = 0x409 */
455	port->nsect_addr	= base + 0x410; /* hob_nsect   = 0x411 */
456	port->lbal_addr		= base + 0x418; /* hob_lbal    = 0x419 */
457	port->lbam_addr		= base + 0x420; /* hob_lbam    = 0x421 */
458	port->lbah_addr		= base + 0x428; /* hob_lbah    = 0x429 */
459	port->device_addr	= base + 0x430;
460	port->status_addr	=
461	port->command_addr	= base + 0x438;
462	port->altstatus_addr	=
463	port->ctl_addr		= base + 0x440;
464	port->scr_addr		= base + 0xc00;
465}
466
467static int qs_port_start(struct ata_port *ap)
468{
469	struct device *dev = ap->host->dev;
470	struct qs_port_priv *pp;
471	void __iomem *mmio_base = qs_mmio_base(ap->host);
472	void __iomem *chan = mmio_base + (ap->port_no * 0x4000);
473	u64 addr;
474
475	pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
476	if (!pp)
477		return -ENOMEM;
478	pp->pkt = dmam_alloc_coherent(dev, QS_PKT_BYTES, &pp->pkt_dma,
479				      GFP_KERNEL);
480	if (!pp->pkt)
481		return -ENOMEM;
482	ap->private_data = pp;
483
484	qs_enter_reg_mode(ap);
485	addr = (u64)pp->pkt_dma;
486	writel((u32) addr,        chan + QS_CCF_CPBA);
487	writel((u32)(addr >> 32), chan + QS_CCF_CPBA + 4);
488	return 0;
489}
490
491static void qs_host_stop(struct ata_host *host)
492{
493	void __iomem *mmio_base = qs_mmio_base(host);
494
495	writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
496	writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */
497}
498
499static void qs_host_init(struct ata_host *host, unsigned int chip_id)
500{
501	void __iomem *mmio_base = host->iomap[QS_MMIO_BAR];
502	unsigned int port_no;
503
504	writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
505	writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */
506
507	/* reset each channel in turn */
508	for (port_no = 0; port_no < host->n_ports; ++port_no) {
509		u8 __iomem *chan = mmio_base + (port_no * 0x4000);
510		writeb(QS_CTR1_RDEV|QS_CTR1_RCHN, chan + QS_CCT_CTR1);
511		writeb(QS_CTR0_REG, chan + QS_CCT_CTR0);
512		readb(chan + QS_CCT_CTR0);        /* flush */
513	}
514	writeb(QS_SERD3_PHY_ENA, mmio_base + QS_HVS_SERD3); /* enable phy */
515
516	for (port_no = 0; port_no < host->n_ports; ++port_no) {
517		u8 __iomem *chan = mmio_base + (port_no * 0x4000);
518		/* set FIFO depths to same settings as Windows driver */
519		writew(32, chan + QS_CFC_HUFT);
520		writew(32, chan + QS_CFC_HDFT);
521		writew(10, chan + QS_CFC_DUFT);
522		writew( 8, chan + QS_CFC_DDFT);
523		/* set CPB size in bytes, as a power of two */
524		writeb(QS_CPB_ORDER,    chan + QS_CCF_CSEP);
525	}
526	writeb(1, mmio_base + QS_HCT_CTRL); /* enable host interrupts */
527}
528
529/*
530 * The QStor understands 64-bit buses, and uses 64-bit fields
531 * for DMA pointers regardless of bus width.  We just have to
532 * make sure our DMA masks are set appropriately for whatever
533 * bridge lies between us and the QStor, and then the DMA mapping
534 * code will ensure we only ever "see" appropriate buffer addresses.
535 * If we're 32-bit limited somewhere, then our 64-bit fields will
536 * just end up with zeros in the upper 32-bits, without any special
537 * logic required outside of this routine (below).
538 */
539static int qs_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base)
540{
541	u32 bus_info = readl(mmio_base + QS_HID_HPHY);
542	int dma_bits = (bus_info & QS_HPHY_64BIT) ? 64 : 32;
543	int rc;
544
545	rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits));
546	if (rc)
547		dev_err(&pdev->dev, "%d-bit DMA enable failed\n", dma_bits);
548	return rc;
549}
550
551static int qs_ata_init_one(struct pci_dev *pdev,
552				const struct pci_device_id *ent)
553{
554	unsigned int board_idx = (unsigned int) ent->driver_data;
555	const struct ata_port_info *ppi[] = { &qs_port_info[board_idx], NULL };
556	struct ata_host *host;
557	int rc, port_no;
558
559	ata_print_version_once(&pdev->dev, DRV_VERSION);
560
561	/* alloc host */
562	host = ata_host_alloc_pinfo(&pdev->dev, ppi, QS_PORTS);
563	if (!host)
564		return -ENOMEM;
565
566	/* acquire resources and fill host */
567	rc = pcim_enable_device(pdev);
568	if (rc)
569		return rc;
570
571	if ((pci_resource_flags(pdev, QS_MMIO_BAR) & IORESOURCE_MEM) == 0)
572		return -ENODEV;
573
574	rc = pcim_iomap_regions(pdev, 1 << QS_MMIO_BAR, DRV_NAME);
575	if (rc)
576		return rc;
577	host->iomap = pcim_iomap_table(pdev);
578
579	rc = qs_set_dma_masks(pdev, host->iomap[QS_MMIO_BAR]);
580	if (rc)
581		return rc;
582
583	for (port_no = 0; port_no < host->n_ports; ++port_no) {
584		struct ata_port *ap = host->ports[port_no];
585		unsigned int offset = port_no * 0x4000;
586		void __iomem *chan = host->iomap[QS_MMIO_BAR] + offset;
587
588		qs_ata_setup_port(&ap->ioaddr, chan);
589
590		ata_port_pbar_desc(ap, QS_MMIO_BAR, -1, "mmio");
591		ata_port_pbar_desc(ap, QS_MMIO_BAR, offset, "port");
592	}
593
594	/* initialize adapter */
595	qs_host_init(host, board_idx);
596
597	pci_set_master(pdev);
598	return ata_host_activate(host, pdev->irq, qs_intr, IRQF_SHARED,
599				 &qs_ata_sht);
600}
601
602module_pci_driver(qs_ata_pci_driver);
603
604MODULE_AUTHOR("Mark Lord");
605MODULE_DESCRIPTION("Pacific Digital Corporation QStor SATA low-level driver");
606MODULE_LICENSE("GPL");
607MODULE_DEVICE_TABLE(pci, qs_ata_pci_tbl);
608MODULE_VERSION(DRV_VERSION);