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/drivers/ata/ata_generic.c

http://github.com/mirrors/linux
C | 258 lines | 155 code | 31 blank | 72 comment | 31 complexity | 068ed006b956a080e3d8fa2efd52b711 MD5 | raw file
  1/*
  2 *  ata_generic.c - Generic PATA/SATA controller driver.
  3 *  Copyright 2005 Red Hat Inc, all rights reserved.
  4 *
  5 *  Elements from ide/pci/generic.c
  6 *	    Copyright (C) 2001-2002	Andre Hedrick <andre@linux-ide.org>
  7 *	    Portions (C) Copyright 2002  Red Hat Inc <alan@redhat.com>
  8 *
  9 *  May be copied or modified under the terms of the GNU General Public License
 10 *
 11 *  Driver for PCI IDE interfaces implementing the standard bus mastering
 12 *  interface functionality. This assumes the BIOS did the drive set up and
 13 *  tuning for us. By default we do not grab all IDE class devices as they
 14 *  may have other drivers or need fixups to avoid problems. Instead we keep
 15 *  a default list of stuff without documentation/driver that appears to
 16 *  work.
 17 */
 18
 19#include <linux/kernel.h>
 20#include <linux/module.h>
 21#include <linux/pci.h>
 22#include <linux/blkdev.h>
 23#include <linux/delay.h>
 24#include <scsi/scsi_host.h>
 25#include <linux/libata.h>
 26
 27#define DRV_NAME "ata_generic"
 28#define DRV_VERSION "0.2.15"
 29
 30/*
 31 *	A generic parallel ATA driver using libata
 32 */
 33
 34enum {
 35	ATA_GEN_CLASS_MATCH		= (1 << 0),
 36	ATA_GEN_FORCE_DMA		= (1 << 1),
 37	ATA_GEN_INTEL_IDER		= (1 << 2),
 38};
 39
 40/**
 41 *	generic_set_mode	-	mode setting
 42 *	@link: link to set up
 43 *	@unused: returned device on error
 44 *
 45 *	Use a non standard set_mode function. We don't want to be tuned.
 46 *	The BIOS configured everything. Our job is not to fiddle. We
 47 *	read the dma enabled bits from the PCI configuration of the device
 48 *	and respect them.
 49 */
 50
 51static int generic_set_mode(struct ata_link *link, struct ata_device **unused)
 52{
 53	struct ata_port *ap = link->ap;
 54	const struct pci_device_id *id = ap->host->private_data;
 55	int dma_enabled = 0;
 56	struct ata_device *dev;
 57
 58	if (id->driver_data & ATA_GEN_FORCE_DMA) {
 59		dma_enabled = 0xff;
 60	} else if (ap->ioaddr.bmdma_addr) {
 61		/* Bits 5 and 6 indicate if DMA is active on master/slave */
 62		dma_enabled = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
 63	}
 64
 65	ata_for_each_dev(dev, link, ENABLED) {
 66		/* We don't really care */
 67		dev->pio_mode = XFER_PIO_0;
 68		dev->dma_mode = XFER_MW_DMA_0;
 69		/* We do need the right mode information for DMA or PIO
 70		   and this comes from the current configuration flags */
 71		if (dma_enabled & (1 << (5 + dev->devno))) {
 72			unsigned int xfer_mask = ata_id_xfermask(dev->id);
 73			const char *name;
 74
 75			if (xfer_mask & (ATA_MASK_MWDMA | ATA_MASK_UDMA))
 76				name = ata_mode_string(xfer_mask);
 77			else {
 78				/* SWDMA perhaps? */
 79				name = "DMA";
 80				xfer_mask |= ata_xfer_mode2mask(XFER_MW_DMA_0);
 81			}
 82
 83			ata_dev_info(dev, "configured for %s\n", name);
 84
 85			dev->xfer_mode = ata_xfer_mask2mode(xfer_mask);
 86			dev->xfer_shift = ata_xfer_mode2shift(dev->xfer_mode);
 87			dev->flags &= ~ATA_DFLAG_PIO;
 88		} else {
 89			ata_dev_info(dev, "configured for PIO\n");
 90			dev->xfer_mode = XFER_PIO_0;
 91			dev->xfer_shift = ATA_SHIFT_PIO;
 92			dev->flags |= ATA_DFLAG_PIO;
 93		}
 94	}
 95	return 0;
 96}
 97
 98static struct scsi_host_template generic_sht = {
 99	ATA_BMDMA_SHT(DRV_NAME),
100};
101
102static struct ata_port_operations generic_port_ops = {
103	.inherits	= &ata_bmdma_port_ops,
104	.cable_detect	= ata_cable_unknown,
105	.set_mode	= generic_set_mode,
106};
107
108static int all_generic_ide;		/* Set to claim all devices */
109
110/**
111 *	is_intel_ider		-	identify intel IDE-R devices
112 *	@dev: PCI device
113 *
114 *	Distinguish Intel IDE-R controller devices from other Intel IDE
115 *	devices. IDE-R devices have no timing registers and are in
116 *	most respects virtual. They should be driven by the ata_generic
117 *	driver.
118 *
119 *	IDE-R devices have PCI offset 0xF8.L as zero, later Intel ATA has
120 *	it non zero. All Intel ATA has 0x40 writable (timing), but it is
121 *	not writable on IDE-R devices (this is guaranteed).
122 */
123
124static int is_intel_ider(struct pci_dev *dev)
125{
126	/* For Intel IDE the value at 0xF8 is only zero on IDE-R
127	   interfaces */
128	u32 r;
129	u16 t;
130
131	/* Check the manufacturing ID, it will be zero for IDE-R */
132	pci_read_config_dword(dev, 0xF8, &r);
133	/* Not IDE-R: punt so that ata_(old)piix gets it */
134	if (r != 0)
135		return 0;
136	/* 0xF8 will also be zero on some early Intel IDE devices
137	   but they will have a sane timing register */
138	pci_read_config_word(dev, 0x40, &t);
139	if (t != 0)
140		return 0;
141	/* Finally check if the timing register is writable so that
142	   we eliminate any early devices hot-docked in a docking
143	   station */
144	pci_write_config_word(dev, 0x40, 1);
145	pci_read_config_word(dev, 0x40, &t);
146	if (t) {
147		pci_write_config_word(dev, 0x40, 0);
148		return 0;
149	}
150	return 1;
151}
152
153/**
154 *	ata_generic_init		-	attach generic IDE
155 *	@dev: PCI device found
156 *	@id: match entry
157 *
158 *	Called each time a matching IDE interface is found. We check if the
159 *	interface is one we wish to claim and if so we perform any chip
160 *	specific hacks then let the ATA layer do the heavy lifting.
161 */
162
163static int ata_generic_init_one(struct pci_dev *dev, const struct pci_device_id *id)
164{
165	u16 command;
166	static const struct ata_port_info info = {
167		.flags = ATA_FLAG_SLAVE_POSS,
168		.pio_mask = ATA_PIO4,
169		.mwdma_mask = ATA_MWDMA2,
170		.udma_mask = ATA_UDMA5,
171		.port_ops = &generic_port_ops
172	};
173	const struct ata_port_info *ppi[] = { &info, NULL };
174
175	/* Don't use the generic entry unless instructed to do so */
176	if ((id->driver_data & ATA_GEN_CLASS_MATCH) && all_generic_ide == 0)
177		return -ENODEV;
178
179	if ((id->driver_data & ATA_GEN_INTEL_IDER) && !all_generic_ide)
180		if (!is_intel_ider(dev))
181			return -ENODEV;
182
183	/* Devices that need care */
184	if (dev->vendor == PCI_VENDOR_ID_UMC &&
185	    dev->device == PCI_DEVICE_ID_UMC_UM8886A &&
186	    (!(PCI_FUNC(dev->devfn) & 1)))
187		return -ENODEV;
188
189	if (dev->vendor == PCI_VENDOR_ID_OPTI &&
190	    dev->device == PCI_DEVICE_ID_OPTI_82C558 &&
191	    (!(PCI_FUNC(dev->devfn) & 1)))
192		return -ENODEV;
193
194	/* Don't re-enable devices in generic mode or we will break some
195	   motherboards with disabled and unused IDE controllers */
196	pci_read_config_word(dev, PCI_COMMAND, &command);
197	if (!(command & PCI_COMMAND_IO))
198		return -ENODEV;
199
200	if (dev->vendor == PCI_VENDOR_ID_AL)
201		ata_pci_bmdma_clear_simplex(dev);
202
203	if (dev->vendor == PCI_VENDOR_ID_ATI) {
204		int rc = pcim_enable_device(dev);
205		if (rc < 0)
206			return rc;
207		pcim_pin_device(dev);
208	}
209	return ata_pci_bmdma_init_one(dev, ppi, &generic_sht, (void *)id, 0);
210}
211
212static struct pci_device_id ata_generic[] = {
213	{ PCI_DEVICE(PCI_VENDOR_ID_PCTECH, PCI_DEVICE_ID_PCTECH_SAMURAI_IDE), },
214	{ PCI_DEVICE(PCI_VENDOR_ID_HOLTEK, PCI_DEVICE_ID_HOLTEK_6565), },
215	{ PCI_DEVICE(PCI_VENDOR_ID_UMC,    PCI_DEVICE_ID_UMC_UM8673F), },
216	{ PCI_DEVICE(PCI_VENDOR_ID_UMC,    PCI_DEVICE_ID_UMC_UM8886A), },
217	{ PCI_DEVICE(PCI_VENDOR_ID_UMC,    PCI_DEVICE_ID_UMC_UM8886BF), },
218	{ PCI_DEVICE(PCI_VENDOR_ID_HINT,   PCI_DEVICE_ID_HINT_VXPROII_IDE), },
219	{ PCI_DEVICE(PCI_VENDOR_ID_VIA,    PCI_DEVICE_ID_VIA_82C561), },
220	{ PCI_DEVICE(PCI_VENDOR_ID_OPTI,   PCI_DEVICE_ID_OPTI_82C558), },
221	{ PCI_DEVICE(PCI_VENDOR_ID_CENATEK,PCI_DEVICE_ID_CENATEK_IDE),
222	  .driver_data = ATA_GEN_FORCE_DMA },
223#if !defined(CONFIG_PATA_TOSHIBA) && !defined(CONFIG_PATA_TOSHIBA_MODULE)
224	{ PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA,PCI_DEVICE_ID_TOSHIBA_PICCOLO_1), },
225	{ PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA,PCI_DEVICE_ID_TOSHIBA_PICCOLO_2),  },
226	{ PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA,PCI_DEVICE_ID_TOSHIBA_PICCOLO_3),  },
227	{ PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA,PCI_DEVICE_ID_TOSHIBA_PICCOLO_5),  },
228#endif
229	/* Intel, IDE class device */
230	{ PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
231	  PCI_CLASS_STORAGE_IDE << 8, 0xFFFFFF00UL,
232	  .driver_data = ATA_GEN_INTEL_IDER },
233	/* Must come last. If you add entries adjust this table appropriately */
234	{ PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_IDE << 8, 0xFFFFFF00UL),
235	  .driver_data = ATA_GEN_CLASS_MATCH },
236	{ 0, },
237};
238
239static struct pci_driver ata_generic_pci_driver = {
240	.name 		= DRV_NAME,
241	.id_table	= ata_generic,
242	.probe 		= ata_generic_init_one,
243	.remove		= ata_pci_remove_one,
244#ifdef CONFIG_PM_SLEEP
245	.suspend	= ata_pci_device_suspend,
246	.resume		= ata_pci_device_resume,
247#endif
248};
249
250module_pci_driver(ata_generic_pci_driver);
251
252MODULE_AUTHOR("Alan Cox");
253MODULE_DESCRIPTION("low-level driver for generic ATA");
254MODULE_LICENSE("GPL");
255MODULE_DEVICE_TABLE(pci, ata_generic);
256MODULE_VERSION(DRV_VERSION);
257
258module_param(all_generic_ide, int, 0);