/drivers/tty/serial/mfd.c
C | 1507 lines | 1106 code | 251 blank | 150 comment | 143 complexity | e7378440a340c71fb694fe4a6860004d MD5 | raw file
1/* 2 * mfd.c: driver for High Speed UART device of Intel Medfield platform 3 * 4 * Refer pxa.c, 8250.c and some other drivers in drivers/serial/ 5 * 6 * (C) Copyright 2010 Intel Corporation 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * as published by the Free Software Foundation; version 2 11 * of the License. 12 */ 13 14/* Notes: 15 * 1. DMA channel allocation: 0/1 channel are assigned to port 0, 16 * 2/3 chan to port 1, 4/5 chan to port 3. Even number chans 17 * are used for RX, odd chans for TX 18 * 19 * 2. The RI/DSR/DCD/DTR are not pinned out, DCD & DSR are always 20 * asserted, only when the HW is reset the DDCD and DDSR will 21 * be triggered 22 */ 23 24#if defined(CONFIG_SERIAL_MFD_HSU_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 25#define SUPPORT_SYSRQ 26#endif 27 28#include <linux/module.h> 29#include <linux/init.h> 30#include <linux/console.h> 31#include <linux/sysrq.h> 32#include <linux/slab.h> 33#include <linux/serial_reg.h> 34#include <linux/circ_buf.h> 35#include <linux/delay.h> 36#include <linux/interrupt.h> 37#include <linux/tty.h> 38#include <linux/tty_flip.h> 39#include <linux/serial_core.h> 40#include <linux/serial_mfd.h> 41#include <linux/dma-mapping.h> 42#include <linux/pci.h> 43#include <linux/nmi.h> 44#include <linux/io.h> 45#include <linux/debugfs.h> 46#include <linux/pm_runtime.h> 47 48#define HSU_DMA_BUF_SIZE 2048 49 50#define chan_readl(chan, offset) readl(chan->reg + offset) 51#define chan_writel(chan, offset, val) writel(val, chan->reg + offset) 52 53#define mfd_readl(obj, offset) readl(obj->reg + offset) 54#define mfd_writel(obj, offset, val) writel(val, obj->reg + offset) 55 56static int hsu_dma_enable; 57module_param(hsu_dma_enable, int, 0); 58MODULE_PARM_DESC(hsu_dma_enable, 59 "It is a bitmap to set working mode, if bit[x] is 1, then port[x] will work in DMA mode, otherwise in PIO mode."); 60 61struct hsu_dma_buffer { 62 u8 *buf; 63 dma_addr_t dma_addr; 64 u32 dma_size; 65 u32 ofs; 66}; 67 68struct hsu_dma_chan { 69 u32 id; 70 enum dma_data_direction dirt; 71 struct uart_hsu_port *uport; 72 void __iomem *reg; 73}; 74 75struct uart_hsu_port { 76 struct uart_port port; 77 unsigned char ier; 78 unsigned char lcr; 79 unsigned char mcr; 80 unsigned int lsr_break_flag; 81 char name[12]; 82 int index; 83 struct device *dev; 84 85 struct hsu_dma_chan *txc; 86 struct hsu_dma_chan *rxc; 87 struct hsu_dma_buffer txbuf; 88 struct hsu_dma_buffer rxbuf; 89 int use_dma; /* flag for DMA/PIO */ 90 int running; 91 int dma_tx_on; 92}; 93 94/* Top level data structure of HSU */ 95struct hsu_port { 96 void __iomem *reg; 97 unsigned long paddr; 98 unsigned long iolen; 99 u32 irq; 100 101 struct uart_hsu_port port[3]; 102 struct hsu_dma_chan chans[10]; 103 104 struct dentry *debugfs; 105}; 106 107static inline unsigned int serial_in(struct uart_hsu_port *up, int offset) 108{ 109 unsigned int val; 110 111 if (offset > UART_MSR) { 112 offset <<= 2; 113 val = readl(up->port.membase + offset); 114 } else 115 val = (unsigned int)readb(up->port.membase + offset); 116 117 return val; 118} 119 120static inline void serial_out(struct uart_hsu_port *up, int offset, int value) 121{ 122 if (offset > UART_MSR) { 123 offset <<= 2; 124 writel(value, up->port.membase + offset); 125 } else { 126 unsigned char val = value & 0xff; 127 writeb(val, up->port.membase + offset); 128 } 129} 130 131#ifdef CONFIG_DEBUG_FS 132 133#define HSU_REGS_BUFSIZE 1024 134 135 136static ssize_t port_show_regs(struct file *file, char __user *user_buf, 137 size_t count, loff_t *ppos) 138{ 139 struct uart_hsu_port *up = file->private_data; 140 char *buf; 141 u32 len = 0; 142 ssize_t ret; 143 144 buf = kzalloc(HSU_REGS_BUFSIZE, GFP_KERNEL); 145 if (!buf) 146 return 0; 147 148 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, 149 "MFD HSU port[%d] regs:\n", up->index); 150 151 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, 152 "=================================\n"); 153 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, 154 "IER: \t\t0x%08x\n", serial_in(up, UART_IER)); 155 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, 156 "IIR: \t\t0x%08x\n", serial_in(up, UART_IIR)); 157 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, 158 "LCR: \t\t0x%08x\n", serial_in(up, UART_LCR)); 159 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, 160 "MCR: \t\t0x%08x\n", serial_in(up, UART_MCR)); 161 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, 162 "LSR: \t\t0x%08x\n", serial_in(up, UART_LSR)); 163 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, 164 "MSR: \t\t0x%08x\n", serial_in(up, UART_MSR)); 165 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, 166 "FOR: \t\t0x%08x\n", serial_in(up, UART_FOR)); 167 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, 168 "PS: \t\t0x%08x\n", serial_in(up, UART_PS)); 169 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, 170 "MUL: \t\t0x%08x\n", serial_in(up, UART_MUL)); 171 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, 172 "DIV: \t\t0x%08x\n", serial_in(up, UART_DIV)); 173 174 if (len > HSU_REGS_BUFSIZE) 175 len = HSU_REGS_BUFSIZE; 176 177 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len); 178 kfree(buf); 179 return ret; 180} 181 182static ssize_t dma_show_regs(struct file *file, char __user *user_buf, 183 size_t count, loff_t *ppos) 184{ 185 struct hsu_dma_chan *chan = file->private_data; 186 char *buf; 187 u32 len = 0; 188 ssize_t ret; 189 190 buf = kzalloc(HSU_REGS_BUFSIZE, GFP_KERNEL); 191 if (!buf) 192 return 0; 193 194 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, 195 "MFD HSU DMA channel [%d] regs:\n", chan->id); 196 197 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, 198 "=================================\n"); 199 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, 200 "CR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_CR)); 201 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, 202 "DCR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_DCR)); 203 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, 204 "BSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_BSR)); 205 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, 206 "MOTSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_MOTSR)); 207 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, 208 "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D0SAR)); 209 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, 210 "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D0TSR)); 211 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, 212 "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D1SAR)); 213 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, 214 "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D1TSR)); 215 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, 216 "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D2SAR)); 217 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, 218 "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D2TSR)); 219 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, 220 "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D3SAR)); 221 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, 222 "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D3TSR)); 223 224 if (len > HSU_REGS_BUFSIZE) 225 len = HSU_REGS_BUFSIZE; 226 227 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len); 228 kfree(buf); 229 return ret; 230} 231 232static const struct file_operations port_regs_ops = { 233 .owner = THIS_MODULE, 234 .open = simple_open, 235 .read = port_show_regs, 236 .llseek = default_llseek, 237}; 238 239static const struct file_operations dma_regs_ops = { 240 .owner = THIS_MODULE, 241 .open = simple_open, 242 .read = dma_show_regs, 243 .llseek = default_llseek, 244}; 245 246static int hsu_debugfs_init(struct hsu_port *hsu) 247{ 248 int i; 249 char name[32]; 250 251 hsu->debugfs = debugfs_create_dir("hsu", NULL); 252 if (!hsu->debugfs) 253 return -ENOMEM; 254 255 for (i = 0; i < 3; i++) { 256 snprintf(name, sizeof(name), "port_%d_regs", i); 257 debugfs_create_file(name, S_IFREG | S_IRUGO, 258 hsu->debugfs, (void *)(&hsu->port[i]), &port_regs_ops); 259 } 260 261 for (i = 0; i < 6; i++) { 262 snprintf(name, sizeof(name), "dma_chan_%d_regs", i); 263 debugfs_create_file(name, S_IFREG | S_IRUGO, 264 hsu->debugfs, (void *)&hsu->chans[i], &dma_regs_ops); 265 } 266 267 return 0; 268} 269 270static void hsu_debugfs_remove(struct hsu_port *hsu) 271{ 272 if (hsu->debugfs) 273 debugfs_remove_recursive(hsu->debugfs); 274} 275 276#else 277static inline int hsu_debugfs_init(struct hsu_port *hsu) 278{ 279 return 0; 280} 281 282static inline void hsu_debugfs_remove(struct hsu_port *hsu) 283{ 284} 285#endif /* CONFIG_DEBUG_FS */ 286 287static void serial_hsu_enable_ms(struct uart_port *port) 288{ 289 struct uart_hsu_port *up = 290 container_of(port, struct uart_hsu_port, port); 291 292 up->ier |= UART_IER_MSI; 293 serial_out(up, UART_IER, up->ier); 294} 295 296void hsu_dma_tx(struct uart_hsu_port *up) 297{ 298 struct circ_buf *xmit = &up->port.state->xmit; 299 struct hsu_dma_buffer *dbuf = &up->txbuf; 300 int count; 301 302 /* test_and_set_bit may be better, but anyway it's in lock protected mode */ 303 if (up->dma_tx_on) 304 return; 305 306 /* Update the circ buf info */ 307 xmit->tail += dbuf->ofs; 308 xmit->tail &= UART_XMIT_SIZE - 1; 309 310 up->port.icount.tx += dbuf->ofs; 311 dbuf->ofs = 0; 312 313 /* Disable the channel */ 314 chan_writel(up->txc, HSU_CH_CR, 0x0); 315 316 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&up->port)) { 317 dma_sync_single_for_device(up->port.dev, 318 dbuf->dma_addr, 319 dbuf->dma_size, 320 DMA_TO_DEVICE); 321 322 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 323 dbuf->ofs = count; 324 325 /* Reprogram the channel */ 326 chan_writel(up->txc, HSU_CH_D0SAR, dbuf->dma_addr + xmit->tail); 327 chan_writel(up->txc, HSU_CH_D0TSR, count); 328 329 /* Reenable the channel */ 330 chan_writel(up->txc, HSU_CH_DCR, 0x1 331 | (0x1 << 8) 332 | (0x1 << 16) 333 | (0x1 << 24)); 334 up->dma_tx_on = 1; 335 chan_writel(up->txc, HSU_CH_CR, 0x1); 336 } 337 338 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 339 uart_write_wakeup(&up->port); 340} 341 342/* The buffer is already cache coherent */ 343void hsu_dma_start_rx_chan(struct hsu_dma_chan *rxc, struct hsu_dma_buffer *dbuf) 344{ 345 dbuf->ofs = 0; 346 347 chan_writel(rxc, HSU_CH_BSR, 32); 348 chan_writel(rxc, HSU_CH_MOTSR, 4); 349 350 chan_writel(rxc, HSU_CH_D0SAR, dbuf->dma_addr); 351 chan_writel(rxc, HSU_CH_D0TSR, dbuf->dma_size); 352 chan_writel(rxc, HSU_CH_DCR, 0x1 | (0x1 << 8) 353 | (0x1 << 16) 354 | (0x1 << 24) /* timeout bit, see HSU Errata 1 */ 355 ); 356 chan_writel(rxc, HSU_CH_CR, 0x3); 357} 358 359/* Protected by spin_lock_irqsave(port->lock) */ 360static void serial_hsu_start_tx(struct uart_port *port) 361{ 362 struct uart_hsu_port *up = 363 container_of(port, struct uart_hsu_port, port); 364 365 if (up->use_dma) { 366 hsu_dma_tx(up); 367 } else if (!(up->ier & UART_IER_THRI)) { 368 up->ier |= UART_IER_THRI; 369 serial_out(up, UART_IER, up->ier); 370 } 371} 372 373static void serial_hsu_stop_tx(struct uart_port *port) 374{ 375 struct uart_hsu_port *up = 376 container_of(port, struct uart_hsu_port, port); 377 struct hsu_dma_chan *txc = up->txc; 378 379 if (up->use_dma) 380 chan_writel(txc, HSU_CH_CR, 0x0); 381 else if (up->ier & UART_IER_THRI) { 382 up->ier &= ~UART_IER_THRI; 383 serial_out(up, UART_IER, up->ier); 384 } 385} 386 387/* This is always called in spinlock protected mode, so 388 * modify timeout timer is safe here */ 389void hsu_dma_rx(struct uart_hsu_port *up, u32 int_sts, unsigned long *flags) 390{ 391 struct hsu_dma_buffer *dbuf = &up->rxbuf; 392 struct hsu_dma_chan *chan = up->rxc; 393 struct uart_port *port = &up->port; 394 struct tty_port *tport = &port->state->port; 395 int count; 396 397 /* 398 * First need to know how many is already transferred, 399 * then check if its a timeout DMA irq, and return 400 * the trail bytes out, push them up and reenable the 401 * channel 402 */ 403 404 /* Timeout IRQ, need wait some time, see Errata 2 */ 405 if (int_sts & 0xf00) 406 udelay(2); 407 408 /* Stop the channel */ 409 chan_writel(chan, HSU_CH_CR, 0x0); 410 411 count = chan_readl(chan, HSU_CH_D0SAR) - dbuf->dma_addr; 412 if (!count) { 413 /* Restart the channel before we leave */ 414 chan_writel(chan, HSU_CH_CR, 0x3); 415 return; 416 } 417 418 dma_sync_single_for_cpu(port->dev, dbuf->dma_addr, 419 dbuf->dma_size, DMA_FROM_DEVICE); 420 421 /* 422 * Head will only wrap around when we recycle 423 * the DMA buffer, and when that happens, we 424 * explicitly set tail to 0. So head will 425 * always be greater than tail. 426 */ 427 tty_insert_flip_string(tport, dbuf->buf, count); 428 port->icount.rx += count; 429 430 dma_sync_single_for_device(up->port.dev, dbuf->dma_addr, 431 dbuf->dma_size, DMA_FROM_DEVICE); 432 433 /* Reprogram the channel */ 434 chan_writel(chan, HSU_CH_D0SAR, dbuf->dma_addr); 435 chan_writel(chan, HSU_CH_D0TSR, dbuf->dma_size); 436 chan_writel(chan, HSU_CH_DCR, 0x1 437 | (0x1 << 8) 438 | (0x1 << 16) 439 | (0x1 << 24) /* timeout bit, see HSU Errata 1 */ 440 ); 441 spin_unlock_irqrestore(&up->port.lock, *flags); 442 tty_flip_buffer_push(tport); 443 spin_lock_irqsave(&up->port.lock, *flags); 444 445 chan_writel(chan, HSU_CH_CR, 0x3); 446 447} 448 449static void serial_hsu_stop_rx(struct uart_port *port) 450{ 451 struct uart_hsu_port *up = 452 container_of(port, struct uart_hsu_port, port); 453 struct hsu_dma_chan *chan = up->rxc; 454 455 if (up->use_dma) 456 chan_writel(chan, HSU_CH_CR, 0x2); 457 else { 458 up->ier &= ~UART_IER_RLSI; 459 up->port.read_status_mask &= ~UART_LSR_DR; 460 serial_out(up, UART_IER, up->ier); 461 } 462} 463 464static inline void receive_chars(struct uart_hsu_port *up, int *status, 465 unsigned long *flags) 466{ 467 unsigned int ch, flag; 468 unsigned int max_count = 256; 469 470 do { 471 ch = serial_in(up, UART_RX); 472 flag = TTY_NORMAL; 473 up->port.icount.rx++; 474 475 if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE | 476 UART_LSR_FE | UART_LSR_OE))) { 477 478 dev_warn(up->dev, "We really rush into ERR/BI case" 479 "status = 0x%02x", *status); 480 /* For statistics only */ 481 if (*status & UART_LSR_BI) { 482 *status &= ~(UART_LSR_FE | UART_LSR_PE); 483 up->port.icount.brk++; 484 /* 485 * We do the SysRQ and SAK checking 486 * here because otherwise the break 487 * may get masked by ignore_status_mask 488 * or read_status_mask. 489 */ 490 if (uart_handle_break(&up->port)) 491 goto ignore_char; 492 } else if (*status & UART_LSR_PE) 493 up->port.icount.parity++; 494 else if (*status & UART_LSR_FE) 495 up->port.icount.frame++; 496 if (*status & UART_LSR_OE) 497 up->port.icount.overrun++; 498 499 /* Mask off conditions which should be ignored. */ 500 *status &= up->port.read_status_mask; 501 502#ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE 503 if (up->port.cons && 504 up->port.cons->index == up->port.line) { 505 /* Recover the break flag from console xmit */ 506 *status |= up->lsr_break_flag; 507 up->lsr_break_flag = 0; 508 } 509#endif 510 if (*status & UART_LSR_BI) { 511 flag = TTY_BREAK; 512 } else if (*status & UART_LSR_PE) 513 flag = TTY_PARITY; 514 else if (*status & UART_LSR_FE) 515 flag = TTY_FRAME; 516 } 517 518 if (uart_handle_sysrq_char(&up->port, ch)) 519 goto ignore_char; 520 521 uart_insert_char(&up->port, *status, UART_LSR_OE, ch, flag); 522 ignore_char: 523 *status = serial_in(up, UART_LSR); 524 } while ((*status & UART_LSR_DR) && max_count--); 525 526 spin_unlock_irqrestore(&up->port.lock, *flags); 527 tty_flip_buffer_push(&up->port.state->port); 528 spin_lock_irqsave(&up->port.lock, *flags); 529} 530 531static void transmit_chars(struct uart_hsu_port *up) 532{ 533 struct circ_buf *xmit = &up->port.state->xmit; 534 int count; 535 536 if (up->port.x_char) { 537 serial_out(up, UART_TX, up->port.x_char); 538 up->port.icount.tx++; 539 up->port.x_char = 0; 540 return; 541 } 542 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) { 543 serial_hsu_stop_tx(&up->port); 544 return; 545 } 546 547 /* The IRQ is for TX FIFO half-empty */ 548 count = up->port.fifosize / 2; 549 550 do { 551 serial_out(up, UART_TX, xmit->buf[xmit->tail]); 552 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 553 554 up->port.icount.tx++; 555 if (uart_circ_empty(xmit)) 556 break; 557 } while (--count > 0); 558 559 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 560 uart_write_wakeup(&up->port); 561 562 if (uart_circ_empty(xmit)) 563 serial_hsu_stop_tx(&up->port); 564} 565 566static inline void check_modem_status(struct uart_hsu_port *up) 567{ 568 int status; 569 570 status = serial_in(up, UART_MSR); 571 572 if ((status & UART_MSR_ANY_DELTA) == 0) 573 return; 574 575 if (status & UART_MSR_TERI) 576 up->port.icount.rng++; 577 if (status & UART_MSR_DDSR) 578 up->port.icount.dsr++; 579 /* We may only get DDCD when HW init and reset */ 580 if (status & UART_MSR_DDCD) 581 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD); 582 /* Will start/stop_tx accordingly */ 583 if (status & UART_MSR_DCTS) 584 uart_handle_cts_change(&up->port, status & UART_MSR_CTS); 585 586 wake_up_interruptible(&up->port.state->port.delta_msr_wait); 587} 588 589/* 590 * This handles the interrupt from one port. 591 */ 592static irqreturn_t port_irq(int irq, void *dev_id) 593{ 594 struct uart_hsu_port *up = dev_id; 595 unsigned int iir, lsr; 596 unsigned long flags; 597 598 if (unlikely(!up->running)) 599 return IRQ_NONE; 600 601 spin_lock_irqsave(&up->port.lock, flags); 602 if (up->use_dma) { 603 lsr = serial_in(up, UART_LSR); 604 if (unlikely(lsr & (UART_LSR_BI | UART_LSR_PE | 605 UART_LSR_FE | UART_LSR_OE))) 606 dev_warn(up->dev, 607 "Got lsr irq while using DMA, lsr = 0x%2x\n", 608 lsr); 609 check_modem_status(up); 610 spin_unlock_irqrestore(&up->port.lock, flags); 611 return IRQ_HANDLED; 612 } 613 614 iir = serial_in(up, UART_IIR); 615 if (iir & UART_IIR_NO_INT) { 616 spin_unlock_irqrestore(&up->port.lock, flags); 617 return IRQ_NONE; 618 } 619 620 lsr = serial_in(up, UART_LSR); 621 if (lsr & UART_LSR_DR) 622 receive_chars(up, &lsr, &flags); 623 check_modem_status(up); 624 625 /* lsr will be renewed during the receive_chars */ 626 if (lsr & UART_LSR_THRE) 627 transmit_chars(up); 628 629 spin_unlock_irqrestore(&up->port.lock, flags); 630 return IRQ_HANDLED; 631} 632 633static inline void dma_chan_irq(struct hsu_dma_chan *chan) 634{ 635 struct uart_hsu_port *up = chan->uport; 636 unsigned long flags; 637 u32 int_sts; 638 639 spin_lock_irqsave(&up->port.lock, flags); 640 641 if (!up->use_dma || !up->running) 642 goto exit; 643 644 /* 645 * No matter what situation, need read clear the IRQ status 646 * There is a bug, see Errata 5, HSD 2900918 647 */ 648 int_sts = chan_readl(chan, HSU_CH_SR); 649 650 /* Rx channel */ 651 if (chan->dirt == DMA_FROM_DEVICE) 652 hsu_dma_rx(up, int_sts, &flags); 653 654 /* Tx channel */ 655 if (chan->dirt == DMA_TO_DEVICE) { 656 chan_writel(chan, HSU_CH_CR, 0x0); 657 up->dma_tx_on = 0; 658 hsu_dma_tx(up); 659 } 660 661exit: 662 spin_unlock_irqrestore(&up->port.lock, flags); 663 return; 664} 665 666static irqreturn_t dma_irq(int irq, void *dev_id) 667{ 668 struct hsu_port *hsu = dev_id; 669 u32 int_sts, i; 670 671 int_sts = mfd_readl(hsu, HSU_GBL_DMAISR); 672 673 /* Currently we only have 6 channels may be used */ 674 for (i = 0; i < 6; i++) { 675 if (int_sts & 0x1) 676 dma_chan_irq(&hsu->chans[i]); 677 int_sts >>= 1; 678 } 679 680 return IRQ_HANDLED; 681} 682 683static unsigned int serial_hsu_tx_empty(struct uart_port *port) 684{ 685 struct uart_hsu_port *up = 686 container_of(port, struct uart_hsu_port, port); 687 unsigned long flags; 688 unsigned int ret; 689 690 spin_lock_irqsave(&up->port.lock, flags); 691 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0; 692 spin_unlock_irqrestore(&up->port.lock, flags); 693 694 return ret; 695} 696 697static unsigned int serial_hsu_get_mctrl(struct uart_port *port) 698{ 699 struct uart_hsu_port *up = 700 container_of(port, struct uart_hsu_port, port); 701 unsigned char status; 702 unsigned int ret; 703 704 status = serial_in(up, UART_MSR); 705 706 ret = 0; 707 if (status & UART_MSR_DCD) 708 ret |= TIOCM_CAR; 709 if (status & UART_MSR_RI) 710 ret |= TIOCM_RNG; 711 if (status & UART_MSR_DSR) 712 ret |= TIOCM_DSR; 713 if (status & UART_MSR_CTS) 714 ret |= TIOCM_CTS; 715 return ret; 716} 717 718static void serial_hsu_set_mctrl(struct uart_port *port, unsigned int mctrl) 719{ 720 struct uart_hsu_port *up = 721 container_of(port, struct uart_hsu_port, port); 722 unsigned char mcr = 0; 723 724 if (mctrl & TIOCM_RTS) 725 mcr |= UART_MCR_RTS; 726 if (mctrl & TIOCM_DTR) 727 mcr |= UART_MCR_DTR; 728 if (mctrl & TIOCM_OUT1) 729 mcr |= UART_MCR_OUT1; 730 if (mctrl & TIOCM_OUT2) 731 mcr |= UART_MCR_OUT2; 732 if (mctrl & TIOCM_LOOP) 733 mcr |= UART_MCR_LOOP; 734 735 mcr |= up->mcr; 736 737 serial_out(up, UART_MCR, mcr); 738} 739 740static void serial_hsu_break_ctl(struct uart_port *port, int break_state) 741{ 742 struct uart_hsu_port *up = 743 container_of(port, struct uart_hsu_port, port); 744 unsigned long flags; 745 746 spin_lock_irqsave(&up->port.lock, flags); 747 if (break_state == -1) 748 up->lcr |= UART_LCR_SBC; 749 else 750 up->lcr &= ~UART_LCR_SBC; 751 serial_out(up, UART_LCR, up->lcr); 752 spin_unlock_irqrestore(&up->port.lock, flags); 753} 754 755/* 756 * What special to do: 757 * 1. chose the 64B fifo mode 758 * 2. start dma or pio depends on configuration 759 * 3. we only allocate dma memory when needed 760 */ 761static int serial_hsu_startup(struct uart_port *port) 762{ 763 struct uart_hsu_port *up = 764 container_of(port, struct uart_hsu_port, port); 765 unsigned long flags; 766 767 pm_runtime_get_sync(up->dev); 768 769 /* 770 * Clear the FIFO buffers and disable them. 771 * (they will be reenabled in set_termios()) 772 */ 773 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); 774 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | 775 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 776 serial_out(up, UART_FCR, 0); 777 778 /* Clear the interrupt registers. */ 779 (void) serial_in(up, UART_LSR); 780 (void) serial_in(up, UART_RX); 781 (void) serial_in(up, UART_IIR); 782 (void) serial_in(up, UART_MSR); 783 784 /* Now, initialize the UART, default is 8n1 */ 785 serial_out(up, UART_LCR, UART_LCR_WLEN8); 786 787 spin_lock_irqsave(&up->port.lock, flags); 788 789 up->port.mctrl |= TIOCM_OUT2; 790 serial_hsu_set_mctrl(&up->port, up->port.mctrl); 791 792 /* 793 * Finally, enable interrupts. Note: Modem status interrupts 794 * are set via set_termios(), which will be occurring imminently 795 * anyway, so we don't enable them here. 796 */ 797 if (!up->use_dma) 798 up->ier = UART_IER_RLSI | UART_IER_RDI | UART_IER_RTOIE; 799 else 800 up->ier = 0; 801 serial_out(up, UART_IER, up->ier); 802 803 spin_unlock_irqrestore(&up->port.lock, flags); 804 805 /* DMA init */ 806 if (up->use_dma) { 807 struct hsu_dma_buffer *dbuf; 808 struct circ_buf *xmit = &port->state->xmit; 809 810 up->dma_tx_on = 0; 811 812 /* First allocate the RX buffer */ 813 dbuf = &up->rxbuf; 814 dbuf->buf = kzalloc(HSU_DMA_BUF_SIZE, GFP_KERNEL); 815 if (!dbuf->buf) { 816 up->use_dma = 0; 817 goto exit; 818 } 819 dbuf->dma_addr = dma_map_single(port->dev, 820 dbuf->buf, 821 HSU_DMA_BUF_SIZE, 822 DMA_FROM_DEVICE); 823 dbuf->dma_size = HSU_DMA_BUF_SIZE; 824 825 /* Start the RX channel right now */ 826 hsu_dma_start_rx_chan(up->rxc, dbuf); 827 828 /* Next init the TX DMA */ 829 dbuf = &up->txbuf; 830 dbuf->buf = xmit->buf; 831 dbuf->dma_addr = dma_map_single(port->dev, 832 dbuf->buf, 833 UART_XMIT_SIZE, 834 DMA_TO_DEVICE); 835 dbuf->dma_size = UART_XMIT_SIZE; 836 837 /* This should not be changed all around */ 838 chan_writel(up->txc, HSU_CH_BSR, 32); 839 chan_writel(up->txc, HSU_CH_MOTSR, 4); 840 dbuf->ofs = 0; 841 } 842 843exit: 844 /* And clear the interrupt registers again for luck. */ 845 (void) serial_in(up, UART_LSR); 846 (void) serial_in(up, UART_RX); 847 (void) serial_in(up, UART_IIR); 848 (void) serial_in(up, UART_MSR); 849 850 up->running = 1; 851 return 0; 852} 853 854static void serial_hsu_shutdown(struct uart_port *port) 855{ 856 struct uart_hsu_port *up = 857 container_of(port, struct uart_hsu_port, port); 858 unsigned long flags; 859 860 /* Disable interrupts from this port */ 861 up->ier = 0; 862 serial_out(up, UART_IER, 0); 863 up->running = 0; 864 865 spin_lock_irqsave(&up->port.lock, flags); 866 up->port.mctrl &= ~TIOCM_OUT2; 867 serial_hsu_set_mctrl(&up->port, up->port.mctrl); 868 spin_unlock_irqrestore(&up->port.lock, flags); 869 870 /* Disable break condition and FIFOs */ 871 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC); 872 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | 873 UART_FCR_CLEAR_RCVR | 874 UART_FCR_CLEAR_XMIT); 875 serial_out(up, UART_FCR, 0); 876 877 pm_runtime_put(up->dev); 878} 879 880static void 881serial_hsu_set_termios(struct uart_port *port, struct ktermios *termios, 882 struct ktermios *old) 883{ 884 struct uart_hsu_port *up = 885 container_of(port, struct uart_hsu_port, port); 886 unsigned char cval, fcr = 0; 887 unsigned long flags; 888 unsigned int baud, quot; 889 u32 ps, mul; 890 891 switch (termios->c_cflag & CSIZE) { 892 case CS5: 893 cval = UART_LCR_WLEN5; 894 break; 895 case CS6: 896 cval = UART_LCR_WLEN6; 897 break; 898 case CS7: 899 cval = UART_LCR_WLEN7; 900 break; 901 default: 902 case CS8: 903 cval = UART_LCR_WLEN8; 904 break; 905 } 906 907 /* CMSPAR isn't supported by this driver */ 908 termios->c_cflag &= ~CMSPAR; 909 910 if (termios->c_cflag & CSTOPB) 911 cval |= UART_LCR_STOP; 912 if (termios->c_cflag & PARENB) 913 cval |= UART_LCR_PARITY; 914 if (!(termios->c_cflag & PARODD)) 915 cval |= UART_LCR_EPAR; 916 917 /* 918 * The base clk is 50Mhz, and the baud rate come from: 919 * baud = 50M * MUL / (DIV * PS * DLAB) 920 * 921 * For those basic low baud rate we can get the direct 922 * scalar from 2746800, like 115200 = 2746800/24. For those 923 * higher baud rate, we handle them case by case, mainly by 924 * adjusting the MUL/PS registers, and DIV register is kept 925 * as default value 0x3d09 to make things simple 926 */ 927 baud = uart_get_baud_rate(port, termios, old, 0, 4000000); 928 929 quot = 1; 930 ps = 0x10; 931 mul = 0x3600; 932 switch (baud) { 933 case 3500000: 934 mul = 0x3345; 935 ps = 0xC; 936 break; 937 case 1843200: 938 mul = 0x2400; 939 break; 940 case 3000000: 941 case 2500000: 942 case 2000000: 943 case 1500000: 944 case 1000000: 945 case 500000: 946 /* mul/ps/quot = 0x9C4/0x10/0x1 will make a 500000 bps */ 947 mul = baud / 500000 * 0x9C4; 948 break; 949 default: 950 /* Use uart_get_divisor to get quot for other baud rates */ 951 quot = 0; 952 } 953 954 if (!quot) 955 quot = uart_get_divisor(port, baud); 956 957 if ((up->port.uartclk / quot) < (2400 * 16)) 958 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_1B; 959 else if ((up->port.uartclk / quot) < (230400 * 16)) 960 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_16B; 961 else 962 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_32B; 963 964 fcr |= UART_FCR_HSU_64B_FIFO; 965 966 /* 967 * Ok, we're now changing the port state. Do it with 968 * interrupts disabled. 969 */ 970 spin_lock_irqsave(&up->port.lock, flags); 971 972 /* Update the per-port timeout */ 973 uart_update_timeout(port, termios->c_cflag, baud); 974 975 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; 976 if (termios->c_iflag & INPCK) 977 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; 978 if (termios->c_iflag & (BRKINT | PARMRK)) 979 up->port.read_status_mask |= UART_LSR_BI; 980 981 /* Characters to ignore */ 982 up->port.ignore_status_mask = 0; 983 if (termios->c_iflag & IGNPAR) 984 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; 985 if (termios->c_iflag & IGNBRK) { 986 up->port.ignore_status_mask |= UART_LSR_BI; 987 /* 988 * If we're ignoring parity and break indicators, 989 * ignore overruns too (for real raw support). 990 */ 991 if (termios->c_iflag & IGNPAR) 992 up->port.ignore_status_mask |= UART_LSR_OE; 993 } 994 995 /* Ignore all characters if CREAD is not set */ 996 if ((termios->c_cflag & CREAD) == 0) 997 up->port.ignore_status_mask |= UART_LSR_DR; 998 999 /* 1000 * CTS flow control flag and modem status interrupts, disable 1001 * MSI by default 1002 */ 1003 up->ier &= ~UART_IER_MSI; 1004 if (UART_ENABLE_MS(&up->port, termios->c_cflag)) 1005 up->ier |= UART_IER_MSI; 1006 1007 serial_out(up, UART_IER, up->ier); 1008 1009 if (termios->c_cflag & CRTSCTS) 1010 up->mcr |= UART_MCR_AFE | UART_MCR_RTS; 1011 else 1012 up->mcr &= ~UART_MCR_AFE; 1013 1014 serial_out(up, UART_LCR, cval | UART_LCR_DLAB); /* set DLAB */ 1015 serial_out(up, UART_DLL, quot & 0xff); /* LS of divisor */ 1016 serial_out(up, UART_DLM, quot >> 8); /* MS of divisor */ 1017 serial_out(up, UART_LCR, cval); /* reset DLAB */ 1018 serial_out(up, UART_MUL, mul); /* set MUL */ 1019 serial_out(up, UART_PS, ps); /* set PS */ 1020 up->lcr = cval; /* Save LCR */ 1021 serial_hsu_set_mctrl(&up->port, up->port.mctrl); 1022 serial_out(up, UART_FCR, fcr); 1023 spin_unlock_irqrestore(&up->port.lock, flags); 1024} 1025 1026static void 1027serial_hsu_pm(struct uart_port *port, unsigned int state, 1028 unsigned int oldstate) 1029{ 1030} 1031 1032static void serial_hsu_release_port(struct uart_port *port) 1033{ 1034} 1035 1036static int serial_hsu_request_port(struct uart_port *port) 1037{ 1038 return 0; 1039} 1040 1041static void serial_hsu_config_port(struct uart_port *port, int flags) 1042{ 1043 struct uart_hsu_port *up = 1044 container_of(port, struct uart_hsu_port, port); 1045 up->port.type = PORT_MFD; 1046} 1047 1048static int 1049serial_hsu_verify_port(struct uart_port *port, struct serial_struct *ser) 1050{ 1051 /* We don't want the core code to modify any port params */ 1052 return -EINVAL; 1053} 1054 1055static const char * 1056serial_hsu_type(struct uart_port *port) 1057{ 1058 struct uart_hsu_port *up = 1059 container_of(port, struct uart_hsu_port, port); 1060 return up->name; 1061} 1062 1063/* Mainly for uart console use */ 1064static struct uart_hsu_port *serial_hsu_ports[3]; 1065static struct uart_driver serial_hsu_reg; 1066 1067#ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE 1068 1069#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) 1070 1071/* Wait for transmitter & holding register to empty */ 1072static inline void wait_for_xmitr(struct uart_hsu_port *up) 1073{ 1074 unsigned int status, tmout = 1000; 1075 1076 /* Wait up to 1ms for the character to be sent. */ 1077 do { 1078 status = serial_in(up, UART_LSR); 1079 1080 if (status & UART_LSR_BI) 1081 up->lsr_break_flag = UART_LSR_BI; 1082 1083 if (--tmout == 0) 1084 break; 1085 udelay(1); 1086 } while (!(status & BOTH_EMPTY)); 1087 1088 /* Wait up to 1s for flow control if necessary */ 1089 if (up->port.flags & UPF_CONS_FLOW) { 1090 tmout = 1000000; 1091 while (--tmout && 1092 ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0)) 1093 udelay(1); 1094 } 1095} 1096 1097static void serial_hsu_console_putchar(struct uart_port *port, int ch) 1098{ 1099 struct uart_hsu_port *up = 1100 container_of(port, struct uart_hsu_port, port); 1101 1102 wait_for_xmitr(up); 1103 serial_out(up, UART_TX, ch); 1104} 1105 1106/* 1107 * Print a string to the serial port trying not to disturb 1108 * any possible real use of the port... 1109 * 1110 * The console_lock must be held when we get here. 1111 */ 1112static void 1113serial_hsu_console_write(struct console *co, const char *s, unsigned int count) 1114{ 1115 struct uart_hsu_port *up = serial_hsu_ports[co->index]; 1116 unsigned long flags; 1117 unsigned int ier; 1118 int locked = 1; 1119 1120 touch_nmi_watchdog(); 1121 1122 local_irq_save(flags); 1123 if (up->port.sysrq) 1124 locked = 0; 1125 else if (oops_in_progress) { 1126 locked = spin_trylock(&up->port.lock); 1127 } else 1128 spin_lock(&up->port.lock); 1129 1130 /* First save the IER then disable the interrupts */ 1131 ier = serial_in(up, UART_IER); 1132 serial_out(up, UART_IER, 0); 1133 1134 uart_console_write(&up->port, s, count, serial_hsu_console_putchar); 1135 1136 /* 1137 * Finally, wait for transmitter to become empty 1138 * and restore the IER 1139 */ 1140 wait_for_xmitr(up); 1141 serial_out(up, UART_IER, ier); 1142 1143 if (locked) 1144 spin_unlock(&up->port.lock); 1145 local_irq_restore(flags); 1146} 1147 1148static struct console serial_hsu_console; 1149 1150static int __init 1151serial_hsu_console_setup(struct console *co, char *options) 1152{ 1153 struct uart_hsu_port *up; 1154 int baud = 115200; 1155 int bits = 8; 1156 int parity = 'n'; 1157 int flow = 'n'; 1158 1159 if (co->index == -1 || co->index >= serial_hsu_reg.nr) 1160 co->index = 0; 1161 up = serial_hsu_ports[co->index]; 1162 if (!up) 1163 return -ENODEV; 1164 1165 if (options) 1166 uart_parse_options(options, &baud, &parity, &bits, &flow); 1167 1168 return uart_set_options(&up->port, co, baud, parity, bits, flow); 1169} 1170 1171static struct console serial_hsu_console = { 1172 .name = "ttyMFD", 1173 .write = serial_hsu_console_write, 1174 .device = uart_console_device, 1175 .setup = serial_hsu_console_setup, 1176 .flags = CON_PRINTBUFFER, 1177 .index = -1, 1178 .data = &serial_hsu_reg, 1179}; 1180 1181#define SERIAL_HSU_CONSOLE (&serial_hsu_console) 1182#else 1183#define SERIAL_HSU_CONSOLE NULL 1184#endif 1185 1186struct uart_ops serial_hsu_pops = { 1187 .tx_empty = serial_hsu_tx_empty, 1188 .set_mctrl = serial_hsu_set_mctrl, 1189 .get_mctrl = serial_hsu_get_mctrl, 1190 .stop_tx = serial_hsu_stop_tx, 1191 .start_tx = serial_hsu_start_tx, 1192 .stop_rx = serial_hsu_stop_rx, 1193 .enable_ms = serial_hsu_enable_ms, 1194 .break_ctl = serial_hsu_break_ctl, 1195 .startup = serial_hsu_startup, 1196 .shutdown = serial_hsu_shutdown, 1197 .set_termios = serial_hsu_set_termios, 1198 .pm = serial_hsu_pm, 1199 .type = serial_hsu_type, 1200 .release_port = serial_hsu_release_port, 1201 .request_port = serial_hsu_request_port, 1202 .config_port = serial_hsu_config_port, 1203 .verify_port = serial_hsu_verify_port, 1204}; 1205 1206static struct uart_driver serial_hsu_reg = { 1207 .owner = THIS_MODULE, 1208 .driver_name = "MFD serial", 1209 .dev_name = "ttyMFD", 1210 .major = TTY_MAJOR, 1211 .minor = 128, 1212 .nr = 3, 1213 .cons = SERIAL_HSU_CONSOLE, 1214}; 1215 1216#ifdef CONFIG_PM 1217static int serial_hsu_suspend(struct pci_dev *pdev, pm_message_t state) 1218{ 1219 void *priv = pci_get_drvdata(pdev); 1220 struct uart_hsu_port *up; 1221 1222 /* Make sure this is not the internal dma controller */ 1223 if (priv && (pdev->device != 0x081E)) { 1224 up = priv; 1225 uart_suspend_port(&serial_hsu_reg, &up->port); 1226 } 1227 1228 pci_save_state(pdev); 1229 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 1230 return 0; 1231} 1232 1233static int serial_hsu_resume(struct pci_dev *pdev) 1234{ 1235 void *priv = pci_get_drvdata(pdev); 1236 struct uart_hsu_port *up; 1237 int ret; 1238 1239 pci_set_power_state(pdev, PCI_D0); 1240 pci_restore_state(pdev); 1241 1242 ret = pci_enable_device(pdev); 1243 if (ret) 1244 dev_warn(&pdev->dev, 1245 "HSU: can't re-enable device, try to continue\n"); 1246 1247 if (priv && (pdev->device != 0x081E)) { 1248 up = priv; 1249 uart_resume_port(&serial_hsu_reg, &up->port); 1250 } 1251 return 0; 1252} 1253#else 1254#define serial_hsu_suspend NULL 1255#define serial_hsu_resume NULL 1256#endif 1257 1258#ifdef CONFIG_PM_RUNTIME 1259static int serial_hsu_runtime_idle(struct device *dev) 1260{ 1261 pm_schedule_suspend(dev, 500); 1262 return -EBUSY; 1263} 1264 1265static int serial_hsu_runtime_suspend(struct device *dev) 1266{ 1267 return 0; 1268} 1269 1270static int serial_hsu_runtime_resume(struct device *dev) 1271{ 1272 return 0; 1273} 1274#else 1275#define serial_hsu_runtime_idle NULL 1276#define serial_hsu_runtime_suspend NULL 1277#define serial_hsu_runtime_resume NULL 1278#endif 1279 1280static const struct dev_pm_ops serial_hsu_pm_ops = { 1281 .runtime_suspend = serial_hsu_runtime_suspend, 1282 .runtime_resume = serial_hsu_runtime_resume, 1283 .runtime_idle = serial_hsu_runtime_idle, 1284}; 1285 1286/* temp global pointer before we settle down on using one or four PCI dev */ 1287static struct hsu_port *phsu; 1288 1289static int serial_hsu_probe(struct pci_dev *pdev, 1290 const struct pci_device_id *ent) 1291{ 1292 struct uart_hsu_port *uport; 1293 int index, ret; 1294 1295 printk(KERN_INFO "HSU: found PCI Serial controller(ID: %04x:%04x)\n", 1296 pdev->vendor, pdev->device); 1297 1298 switch (pdev->device) { 1299 case 0x081B: 1300 index = 0; 1301 break; 1302 case 0x081C: 1303 index = 1; 1304 break; 1305 case 0x081D: 1306 index = 2; 1307 break; 1308 case 0x081E: 1309 /* internal DMA controller */ 1310 index = 3; 1311 break; 1312 default: 1313 dev_err(&pdev->dev, "HSU: out of index!"); 1314 return -ENODEV; 1315 } 1316 1317 ret = pci_enable_device(pdev); 1318 if (ret) 1319 return ret; 1320 1321 if (index == 3) { 1322 /* DMA controller */ 1323 ret = request_irq(pdev->irq, dma_irq, 0, "hsu_dma", phsu); 1324 if (ret) { 1325 dev_err(&pdev->dev, "can not get IRQ\n"); 1326 goto err_disable; 1327 } 1328 pci_set_drvdata(pdev, phsu); 1329 } else { 1330 /* UART port 0~2 */ 1331 uport = &phsu->port[index]; 1332 uport->port.irq = pdev->irq; 1333 uport->port.dev = &pdev->dev; 1334 uport->dev = &pdev->dev; 1335 1336 ret = request_irq(pdev->irq, port_irq, 0, uport->name, uport); 1337 if (ret) { 1338 dev_err(&pdev->dev, "can not get IRQ\n"); 1339 goto err_disable; 1340 } 1341 uart_add_one_port(&serial_hsu_reg, &uport->port); 1342 1343 pci_set_drvdata(pdev, uport); 1344 } 1345 1346 pm_runtime_put_noidle(&pdev->dev); 1347 pm_runtime_allow(&pdev->dev); 1348 1349 return 0; 1350 1351err_disable: 1352 pci_disable_device(pdev); 1353 return ret; 1354} 1355 1356static void hsu_global_init(void) 1357{ 1358 struct hsu_port *hsu; 1359 struct uart_hsu_port *uport; 1360 struct hsu_dma_chan *dchan; 1361 int i, ret; 1362 1363 hsu = kzalloc(sizeof(struct hsu_port), GFP_KERNEL); 1364 if (!hsu) 1365 return; 1366 1367 /* Get basic io resource and map it */ 1368 hsu->paddr = 0xffa28000; 1369 hsu->iolen = 0x1000; 1370 1371 if (!(request_mem_region(hsu->paddr, hsu->iolen, "HSU global"))) 1372 pr_warning("HSU: error in request mem region\n"); 1373 1374 hsu->reg = ioremap_nocache((unsigned long)hsu->paddr, hsu->iolen); 1375 if (!hsu->reg) { 1376 pr_err("HSU: error in ioremap\n"); 1377 ret = -ENOMEM; 1378 goto err_free_region; 1379 } 1380 1381 /* Initialise the 3 UART ports */ 1382 uport = hsu->port; 1383 for (i = 0; i < 3; i++) { 1384 uport->port.type = PORT_MFD; 1385 uport->port.iotype = UPIO_MEM; 1386 uport->port.mapbase = (resource_size_t)hsu->paddr 1387 + HSU_PORT_REG_OFFSET 1388 + i * HSU_PORT_REG_LENGTH; 1389 uport->port.membase = hsu->reg + HSU_PORT_REG_OFFSET 1390 + i * HSU_PORT_REG_LENGTH; 1391 1392 sprintf(uport->name, "hsu_port%d", i); 1393 uport->port.fifosize = 64; 1394 uport->port.ops = &serial_hsu_pops; 1395 uport->port.line = i; 1396 uport->port.flags = UPF_IOREMAP; 1397 /* set the scalable maxim support rate to 2746800 bps */ 1398 uport->port.uartclk = 115200 * 24 * 16; 1399 1400 uport->running = 0; 1401 uport->txc = &hsu->chans[i * 2]; 1402 uport->rxc = &hsu->chans[i * 2 + 1]; 1403 1404 serial_hsu_ports[i] = uport; 1405 uport->index = i; 1406 1407 if (hsu_dma_enable & (1<<i)) 1408 uport->use_dma = 1; 1409 else 1410 uport->use_dma = 0; 1411 1412 uport++; 1413 } 1414 1415 /* Initialise 6 dma channels */ 1416 dchan = hsu->chans; 1417 for (i = 0; i < 6; i++) { 1418 dchan->id = i; 1419 dchan->dirt = (i & 0x1) ? DMA_FROM_DEVICE : DMA_TO_DEVICE; 1420 dchan->uport = &hsu->port[i/2]; 1421 dchan->reg = hsu->reg + HSU_DMA_CHANS_REG_OFFSET + 1422 i * HSU_DMA_CHANS_REG_LENGTH; 1423 1424 dchan++; 1425 } 1426 1427 phsu = hsu; 1428 hsu_debugfs_init(hsu); 1429 return; 1430 1431err_free_region: 1432 release_mem_region(hsu->paddr, hsu->iolen); 1433 kfree(hsu); 1434 return; 1435} 1436 1437static void serial_hsu_remove(struct pci_dev *pdev) 1438{ 1439 void *priv = pci_get_drvdata(pdev); 1440 struct uart_hsu_port *up; 1441 1442 if (!priv) 1443 return; 1444 1445 pm_runtime_forbid(&pdev->dev); 1446 pm_runtime_get_noresume(&pdev->dev); 1447 1448 /* For port 0/1/2, priv is the address of uart_hsu_port */ 1449 if (pdev->device != 0x081E) { 1450 up = priv; 1451 uart_remove_one_port(&serial_hsu_reg, &up->port); 1452 } 1453 1454 pci_set_drvdata(pdev, NULL); 1455 free_irq(pdev->irq, priv); 1456 pci_disable_device(pdev); 1457} 1458 1459/* First 3 are UART ports, and the 4th is the DMA */ 1460static const struct pci_device_id pci_ids[] = { 1461 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081B) }, 1462 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081C) }, 1463 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081D) }, 1464 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081E) }, 1465 {}, 1466}; 1467 1468static struct pci_driver hsu_pci_driver = { 1469 .name = "HSU serial", 1470 .id_table = pci_ids, 1471 .probe = serial_hsu_probe, 1472 .remove = serial_hsu_remove, 1473 .suspend = serial_hsu_suspend, 1474 .resume = serial_hsu_resume, 1475 .driver = { 1476 .pm = &serial_hsu_pm_ops, 1477 }, 1478}; 1479 1480static int __init hsu_pci_init(void) 1481{ 1482 int ret; 1483 1484 hsu_global_init(); 1485 1486 ret = uart_register_driver(&serial_hsu_reg); 1487 if (ret) 1488 return ret; 1489 1490 return pci_register_driver(&hsu_pci_driver); 1491} 1492 1493static void __exit hsu_pci_exit(void) 1494{ 1495 pci_unregister_driver(&hsu_pci_driver); 1496 uart_unregister_driver(&serial_hsu_reg); 1497 1498 hsu_debugfs_remove(phsu); 1499 1500 kfree(phsu); 1501} 1502 1503module_init(hsu_pci_init); 1504module_exit(hsu_pci_exit); 1505 1506MODULE_LICENSE("GPL v2"); 1507MODULE_ALIAS("platform:medfield-hsu");