/drivers/tty/serial/mfd.c

http://github.com/mirrors/linux · C · 1507 lines · 1106 code · 251 blank · 150 comment · 143 complexity · e7378440a340c71fb694fe4a6860004d MD5 · raw file

  1. /*
  2. * mfd.c: driver for High Speed UART device of Intel Medfield platform
  3. *
  4. * Refer pxa.c, 8250.c and some other drivers in drivers/serial/
  5. *
  6. * (C) Copyright 2010 Intel Corporation
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License
  10. * as published by the Free Software Foundation; version 2
  11. * of the License.
  12. */
  13. /* Notes:
  14. * 1. DMA channel allocation: 0/1 channel are assigned to port 0,
  15. * 2/3 chan to port 1, 4/5 chan to port 3. Even number chans
  16. * are used for RX, odd chans for TX
  17. *
  18. * 2. The RI/DSR/DCD/DTR are not pinned out, DCD & DSR are always
  19. * asserted, only when the HW is reset the DDCD and DDSR will
  20. * be triggered
  21. */
  22. #if defined(CONFIG_SERIAL_MFD_HSU_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  23. #define SUPPORT_SYSRQ
  24. #endif
  25. #include <linux/module.h>
  26. #include <linux/init.h>
  27. #include <linux/console.h>
  28. #include <linux/sysrq.h>
  29. #include <linux/slab.h>
  30. #include <linux/serial_reg.h>
  31. #include <linux/circ_buf.h>
  32. #include <linux/delay.h>
  33. #include <linux/interrupt.h>
  34. #include <linux/tty.h>
  35. #include <linux/tty_flip.h>
  36. #include <linux/serial_core.h>
  37. #include <linux/serial_mfd.h>
  38. #include <linux/dma-mapping.h>
  39. #include <linux/pci.h>
  40. #include <linux/nmi.h>
  41. #include <linux/io.h>
  42. #include <linux/debugfs.h>
  43. #include <linux/pm_runtime.h>
  44. #define HSU_DMA_BUF_SIZE 2048
  45. #define chan_readl(chan, offset) readl(chan->reg + offset)
  46. #define chan_writel(chan, offset, val) writel(val, chan->reg + offset)
  47. #define mfd_readl(obj, offset) readl(obj->reg + offset)
  48. #define mfd_writel(obj, offset, val) writel(val, obj->reg + offset)
  49. static int hsu_dma_enable;
  50. module_param(hsu_dma_enable, int, 0);
  51. MODULE_PARM_DESC(hsu_dma_enable,
  52. "It is a bitmap to set working mode, if bit[x] is 1, then port[x] will work in DMA mode, otherwise in PIO mode.");
  53. struct hsu_dma_buffer {
  54. u8 *buf;
  55. dma_addr_t dma_addr;
  56. u32 dma_size;
  57. u32 ofs;
  58. };
  59. struct hsu_dma_chan {
  60. u32 id;
  61. enum dma_data_direction dirt;
  62. struct uart_hsu_port *uport;
  63. void __iomem *reg;
  64. };
  65. struct uart_hsu_port {
  66. struct uart_port port;
  67. unsigned char ier;
  68. unsigned char lcr;
  69. unsigned char mcr;
  70. unsigned int lsr_break_flag;
  71. char name[12];
  72. int index;
  73. struct device *dev;
  74. struct hsu_dma_chan *txc;
  75. struct hsu_dma_chan *rxc;
  76. struct hsu_dma_buffer txbuf;
  77. struct hsu_dma_buffer rxbuf;
  78. int use_dma; /* flag for DMA/PIO */
  79. int running;
  80. int dma_tx_on;
  81. };
  82. /* Top level data structure of HSU */
  83. struct hsu_port {
  84. void __iomem *reg;
  85. unsigned long paddr;
  86. unsigned long iolen;
  87. u32 irq;
  88. struct uart_hsu_port port[3];
  89. struct hsu_dma_chan chans[10];
  90. struct dentry *debugfs;
  91. };
  92. static inline unsigned int serial_in(struct uart_hsu_port *up, int offset)
  93. {
  94. unsigned int val;
  95. if (offset > UART_MSR) {
  96. offset <<= 2;
  97. val = readl(up->port.membase + offset);
  98. } else
  99. val = (unsigned int)readb(up->port.membase + offset);
  100. return val;
  101. }
  102. static inline void serial_out(struct uart_hsu_port *up, int offset, int value)
  103. {
  104. if (offset > UART_MSR) {
  105. offset <<= 2;
  106. writel(value, up->port.membase + offset);
  107. } else {
  108. unsigned char val = value & 0xff;
  109. writeb(val, up->port.membase + offset);
  110. }
  111. }
  112. #ifdef CONFIG_DEBUG_FS
  113. #define HSU_REGS_BUFSIZE 1024
  114. static ssize_t port_show_regs(struct file *file, char __user *user_buf,
  115. size_t count, loff_t *ppos)
  116. {
  117. struct uart_hsu_port *up = file->private_data;
  118. char *buf;
  119. u32 len = 0;
  120. ssize_t ret;
  121. buf = kzalloc(HSU_REGS_BUFSIZE, GFP_KERNEL);
  122. if (!buf)
  123. return 0;
  124. len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
  125. "MFD HSU port[%d] regs:\n", up->index);
  126. len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
  127. "=================================\n");
  128. len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
  129. "IER: \t\t0x%08x\n", serial_in(up, UART_IER));
  130. len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
  131. "IIR: \t\t0x%08x\n", serial_in(up, UART_IIR));
  132. len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
  133. "LCR: \t\t0x%08x\n", serial_in(up, UART_LCR));
  134. len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
  135. "MCR: \t\t0x%08x\n", serial_in(up, UART_MCR));
  136. len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
  137. "LSR: \t\t0x%08x\n", serial_in(up, UART_LSR));
  138. len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
  139. "MSR: \t\t0x%08x\n", serial_in(up, UART_MSR));
  140. len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
  141. "FOR: \t\t0x%08x\n", serial_in(up, UART_FOR));
  142. len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
  143. "PS: \t\t0x%08x\n", serial_in(up, UART_PS));
  144. len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
  145. "MUL: \t\t0x%08x\n", serial_in(up, UART_MUL));
  146. len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
  147. "DIV: \t\t0x%08x\n", serial_in(up, UART_DIV));
  148. if (len > HSU_REGS_BUFSIZE)
  149. len = HSU_REGS_BUFSIZE;
  150. ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
  151. kfree(buf);
  152. return ret;
  153. }
  154. static ssize_t dma_show_regs(struct file *file, char __user *user_buf,
  155. size_t count, loff_t *ppos)
  156. {
  157. struct hsu_dma_chan *chan = file->private_data;
  158. char *buf;
  159. u32 len = 0;
  160. ssize_t ret;
  161. buf = kzalloc(HSU_REGS_BUFSIZE, GFP_KERNEL);
  162. if (!buf)
  163. return 0;
  164. len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
  165. "MFD HSU DMA channel [%d] regs:\n", chan->id);
  166. len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
  167. "=================================\n");
  168. len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
  169. "CR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_CR));
  170. len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
  171. "DCR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_DCR));
  172. len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
  173. "BSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_BSR));
  174. len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
  175. "MOTSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_MOTSR));
  176. len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
  177. "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D0SAR));
  178. len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
  179. "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D0TSR));
  180. len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
  181. "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D1SAR));
  182. len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
  183. "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D1TSR));
  184. len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
  185. "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D2SAR));
  186. len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
  187. "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D2TSR));
  188. len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
  189. "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D3SAR));
  190. len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
  191. "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D3TSR));
  192. if (len > HSU_REGS_BUFSIZE)
  193. len = HSU_REGS_BUFSIZE;
  194. ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
  195. kfree(buf);
  196. return ret;
  197. }
  198. static const struct file_operations port_regs_ops = {
  199. .owner = THIS_MODULE,
  200. .open = simple_open,
  201. .read = port_show_regs,
  202. .llseek = default_llseek,
  203. };
  204. static const struct file_operations dma_regs_ops = {
  205. .owner = THIS_MODULE,
  206. .open = simple_open,
  207. .read = dma_show_regs,
  208. .llseek = default_llseek,
  209. };
  210. static int hsu_debugfs_init(struct hsu_port *hsu)
  211. {
  212. int i;
  213. char name[32];
  214. hsu->debugfs = debugfs_create_dir("hsu", NULL);
  215. if (!hsu->debugfs)
  216. return -ENOMEM;
  217. for (i = 0; i < 3; i++) {
  218. snprintf(name, sizeof(name), "port_%d_regs", i);
  219. debugfs_create_file(name, S_IFREG | S_IRUGO,
  220. hsu->debugfs, (void *)(&hsu->port[i]), &port_regs_ops);
  221. }
  222. for (i = 0; i < 6; i++) {
  223. snprintf(name, sizeof(name), "dma_chan_%d_regs", i);
  224. debugfs_create_file(name, S_IFREG | S_IRUGO,
  225. hsu->debugfs, (void *)&hsu->chans[i], &dma_regs_ops);
  226. }
  227. return 0;
  228. }
  229. static void hsu_debugfs_remove(struct hsu_port *hsu)
  230. {
  231. if (hsu->debugfs)
  232. debugfs_remove_recursive(hsu->debugfs);
  233. }
  234. #else
  235. static inline int hsu_debugfs_init(struct hsu_port *hsu)
  236. {
  237. return 0;
  238. }
  239. static inline void hsu_debugfs_remove(struct hsu_port *hsu)
  240. {
  241. }
  242. #endif /* CONFIG_DEBUG_FS */
  243. static void serial_hsu_enable_ms(struct uart_port *port)
  244. {
  245. struct uart_hsu_port *up =
  246. container_of(port, struct uart_hsu_port, port);
  247. up->ier |= UART_IER_MSI;
  248. serial_out(up, UART_IER, up->ier);
  249. }
  250. void hsu_dma_tx(struct uart_hsu_port *up)
  251. {
  252. struct circ_buf *xmit = &up->port.state->xmit;
  253. struct hsu_dma_buffer *dbuf = &up->txbuf;
  254. int count;
  255. /* test_and_set_bit may be better, but anyway it's in lock protected mode */
  256. if (up->dma_tx_on)
  257. return;
  258. /* Update the circ buf info */
  259. xmit->tail += dbuf->ofs;
  260. xmit->tail &= UART_XMIT_SIZE - 1;
  261. up->port.icount.tx += dbuf->ofs;
  262. dbuf->ofs = 0;
  263. /* Disable the channel */
  264. chan_writel(up->txc, HSU_CH_CR, 0x0);
  265. if (!uart_circ_empty(xmit) && !uart_tx_stopped(&up->port)) {
  266. dma_sync_single_for_device(up->port.dev,
  267. dbuf->dma_addr,
  268. dbuf->dma_size,
  269. DMA_TO_DEVICE);
  270. count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
  271. dbuf->ofs = count;
  272. /* Reprogram the channel */
  273. chan_writel(up->txc, HSU_CH_D0SAR, dbuf->dma_addr + xmit->tail);
  274. chan_writel(up->txc, HSU_CH_D0TSR, count);
  275. /* Reenable the channel */
  276. chan_writel(up->txc, HSU_CH_DCR, 0x1
  277. | (0x1 << 8)
  278. | (0x1 << 16)
  279. | (0x1 << 24));
  280. up->dma_tx_on = 1;
  281. chan_writel(up->txc, HSU_CH_CR, 0x1);
  282. }
  283. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  284. uart_write_wakeup(&up->port);
  285. }
  286. /* The buffer is already cache coherent */
  287. void hsu_dma_start_rx_chan(struct hsu_dma_chan *rxc, struct hsu_dma_buffer *dbuf)
  288. {
  289. dbuf->ofs = 0;
  290. chan_writel(rxc, HSU_CH_BSR, 32);
  291. chan_writel(rxc, HSU_CH_MOTSR, 4);
  292. chan_writel(rxc, HSU_CH_D0SAR, dbuf->dma_addr);
  293. chan_writel(rxc, HSU_CH_D0TSR, dbuf->dma_size);
  294. chan_writel(rxc, HSU_CH_DCR, 0x1 | (0x1 << 8)
  295. | (0x1 << 16)
  296. | (0x1 << 24) /* timeout bit, see HSU Errata 1 */
  297. );
  298. chan_writel(rxc, HSU_CH_CR, 0x3);
  299. }
  300. /* Protected by spin_lock_irqsave(port->lock) */
  301. static void serial_hsu_start_tx(struct uart_port *port)
  302. {
  303. struct uart_hsu_port *up =
  304. container_of(port, struct uart_hsu_port, port);
  305. if (up->use_dma) {
  306. hsu_dma_tx(up);
  307. } else if (!(up->ier & UART_IER_THRI)) {
  308. up->ier |= UART_IER_THRI;
  309. serial_out(up, UART_IER, up->ier);
  310. }
  311. }
  312. static void serial_hsu_stop_tx(struct uart_port *port)
  313. {
  314. struct uart_hsu_port *up =
  315. container_of(port, struct uart_hsu_port, port);
  316. struct hsu_dma_chan *txc = up->txc;
  317. if (up->use_dma)
  318. chan_writel(txc, HSU_CH_CR, 0x0);
  319. else if (up->ier & UART_IER_THRI) {
  320. up->ier &= ~UART_IER_THRI;
  321. serial_out(up, UART_IER, up->ier);
  322. }
  323. }
  324. /* This is always called in spinlock protected mode, so
  325. * modify timeout timer is safe here */
  326. void hsu_dma_rx(struct uart_hsu_port *up, u32 int_sts, unsigned long *flags)
  327. {
  328. struct hsu_dma_buffer *dbuf = &up->rxbuf;
  329. struct hsu_dma_chan *chan = up->rxc;
  330. struct uart_port *port = &up->port;
  331. struct tty_port *tport = &port->state->port;
  332. int count;
  333. /*
  334. * First need to know how many is already transferred,
  335. * then check if its a timeout DMA irq, and return
  336. * the trail bytes out, push them up and reenable the
  337. * channel
  338. */
  339. /* Timeout IRQ, need wait some time, see Errata 2 */
  340. if (int_sts & 0xf00)
  341. udelay(2);
  342. /* Stop the channel */
  343. chan_writel(chan, HSU_CH_CR, 0x0);
  344. count = chan_readl(chan, HSU_CH_D0SAR) - dbuf->dma_addr;
  345. if (!count) {
  346. /* Restart the channel before we leave */
  347. chan_writel(chan, HSU_CH_CR, 0x3);
  348. return;
  349. }
  350. dma_sync_single_for_cpu(port->dev, dbuf->dma_addr,
  351. dbuf->dma_size, DMA_FROM_DEVICE);
  352. /*
  353. * Head will only wrap around when we recycle
  354. * the DMA buffer, and when that happens, we
  355. * explicitly set tail to 0. So head will
  356. * always be greater than tail.
  357. */
  358. tty_insert_flip_string(tport, dbuf->buf, count);
  359. port->icount.rx += count;
  360. dma_sync_single_for_device(up->port.dev, dbuf->dma_addr,
  361. dbuf->dma_size, DMA_FROM_DEVICE);
  362. /* Reprogram the channel */
  363. chan_writel(chan, HSU_CH_D0SAR, dbuf->dma_addr);
  364. chan_writel(chan, HSU_CH_D0TSR, dbuf->dma_size);
  365. chan_writel(chan, HSU_CH_DCR, 0x1
  366. | (0x1 << 8)
  367. | (0x1 << 16)
  368. | (0x1 << 24) /* timeout bit, see HSU Errata 1 */
  369. );
  370. spin_unlock_irqrestore(&up->port.lock, *flags);
  371. tty_flip_buffer_push(tport);
  372. spin_lock_irqsave(&up->port.lock, *flags);
  373. chan_writel(chan, HSU_CH_CR, 0x3);
  374. }
  375. static void serial_hsu_stop_rx(struct uart_port *port)
  376. {
  377. struct uart_hsu_port *up =
  378. container_of(port, struct uart_hsu_port, port);
  379. struct hsu_dma_chan *chan = up->rxc;
  380. if (up->use_dma)
  381. chan_writel(chan, HSU_CH_CR, 0x2);
  382. else {
  383. up->ier &= ~UART_IER_RLSI;
  384. up->port.read_status_mask &= ~UART_LSR_DR;
  385. serial_out(up, UART_IER, up->ier);
  386. }
  387. }
  388. static inline void receive_chars(struct uart_hsu_port *up, int *status,
  389. unsigned long *flags)
  390. {
  391. unsigned int ch, flag;
  392. unsigned int max_count = 256;
  393. do {
  394. ch = serial_in(up, UART_RX);
  395. flag = TTY_NORMAL;
  396. up->port.icount.rx++;
  397. if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE |
  398. UART_LSR_FE | UART_LSR_OE))) {
  399. dev_warn(up->dev, "We really rush into ERR/BI case"
  400. "status = 0x%02x", *status);
  401. /* For statistics only */
  402. if (*status & UART_LSR_BI) {
  403. *status &= ~(UART_LSR_FE | UART_LSR_PE);
  404. up->port.icount.brk++;
  405. /*
  406. * We do the SysRQ and SAK checking
  407. * here because otherwise the break
  408. * may get masked by ignore_status_mask
  409. * or read_status_mask.
  410. */
  411. if (uart_handle_break(&up->port))
  412. goto ignore_char;
  413. } else if (*status & UART_LSR_PE)
  414. up->port.icount.parity++;
  415. else if (*status & UART_LSR_FE)
  416. up->port.icount.frame++;
  417. if (*status & UART_LSR_OE)
  418. up->port.icount.overrun++;
  419. /* Mask off conditions which should be ignored. */
  420. *status &= up->port.read_status_mask;
  421. #ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE
  422. if (up->port.cons &&
  423. up->port.cons->index == up->port.line) {
  424. /* Recover the break flag from console xmit */
  425. *status |= up->lsr_break_flag;
  426. up->lsr_break_flag = 0;
  427. }
  428. #endif
  429. if (*status & UART_LSR_BI) {
  430. flag = TTY_BREAK;
  431. } else if (*status & UART_LSR_PE)
  432. flag = TTY_PARITY;
  433. else if (*status & UART_LSR_FE)
  434. flag = TTY_FRAME;
  435. }
  436. if (uart_handle_sysrq_char(&up->port, ch))
  437. goto ignore_char;
  438. uart_insert_char(&up->port, *status, UART_LSR_OE, ch, flag);
  439. ignore_char:
  440. *status = serial_in(up, UART_LSR);
  441. } while ((*status & UART_LSR_DR) && max_count--);
  442. spin_unlock_irqrestore(&up->port.lock, *flags);
  443. tty_flip_buffer_push(&up->port.state->port);
  444. spin_lock_irqsave(&up->port.lock, *flags);
  445. }
  446. static void transmit_chars(struct uart_hsu_port *up)
  447. {
  448. struct circ_buf *xmit = &up->port.state->xmit;
  449. int count;
  450. if (up->port.x_char) {
  451. serial_out(up, UART_TX, up->port.x_char);
  452. up->port.icount.tx++;
  453. up->port.x_char = 0;
  454. return;
  455. }
  456. if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
  457. serial_hsu_stop_tx(&up->port);
  458. return;
  459. }
  460. /* The IRQ is for TX FIFO half-empty */
  461. count = up->port.fifosize / 2;
  462. do {
  463. serial_out(up, UART_TX, xmit->buf[xmit->tail]);
  464. xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
  465. up->port.icount.tx++;
  466. if (uart_circ_empty(xmit))
  467. break;
  468. } while (--count > 0);
  469. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  470. uart_write_wakeup(&up->port);
  471. if (uart_circ_empty(xmit))
  472. serial_hsu_stop_tx(&up->port);
  473. }
  474. static inline void check_modem_status(struct uart_hsu_port *up)
  475. {
  476. int status;
  477. status = serial_in(up, UART_MSR);
  478. if ((status & UART_MSR_ANY_DELTA) == 0)
  479. return;
  480. if (status & UART_MSR_TERI)
  481. up->port.icount.rng++;
  482. if (status & UART_MSR_DDSR)
  483. up->port.icount.dsr++;
  484. /* We may only get DDCD when HW init and reset */
  485. if (status & UART_MSR_DDCD)
  486. uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
  487. /* Will start/stop_tx accordingly */
  488. if (status & UART_MSR_DCTS)
  489. uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
  490. wake_up_interruptible(&up->port.state->port.delta_msr_wait);
  491. }
  492. /*
  493. * This handles the interrupt from one port.
  494. */
  495. static irqreturn_t port_irq(int irq, void *dev_id)
  496. {
  497. struct uart_hsu_port *up = dev_id;
  498. unsigned int iir, lsr;
  499. unsigned long flags;
  500. if (unlikely(!up->running))
  501. return IRQ_NONE;
  502. spin_lock_irqsave(&up->port.lock, flags);
  503. if (up->use_dma) {
  504. lsr = serial_in(up, UART_LSR);
  505. if (unlikely(lsr & (UART_LSR_BI | UART_LSR_PE |
  506. UART_LSR_FE | UART_LSR_OE)))
  507. dev_warn(up->dev,
  508. "Got lsr irq while using DMA, lsr = 0x%2x\n",
  509. lsr);
  510. check_modem_status(up);
  511. spin_unlock_irqrestore(&up->port.lock, flags);
  512. return IRQ_HANDLED;
  513. }
  514. iir = serial_in(up, UART_IIR);
  515. if (iir & UART_IIR_NO_INT) {
  516. spin_unlock_irqrestore(&up->port.lock, flags);
  517. return IRQ_NONE;
  518. }
  519. lsr = serial_in(up, UART_LSR);
  520. if (lsr & UART_LSR_DR)
  521. receive_chars(up, &lsr, &flags);
  522. check_modem_status(up);
  523. /* lsr will be renewed during the receive_chars */
  524. if (lsr & UART_LSR_THRE)
  525. transmit_chars(up);
  526. spin_unlock_irqrestore(&up->port.lock, flags);
  527. return IRQ_HANDLED;
  528. }
  529. static inline void dma_chan_irq(struct hsu_dma_chan *chan)
  530. {
  531. struct uart_hsu_port *up = chan->uport;
  532. unsigned long flags;
  533. u32 int_sts;
  534. spin_lock_irqsave(&up->port.lock, flags);
  535. if (!up->use_dma || !up->running)
  536. goto exit;
  537. /*
  538. * No matter what situation, need read clear the IRQ status
  539. * There is a bug, see Errata 5, HSD 2900918
  540. */
  541. int_sts = chan_readl(chan, HSU_CH_SR);
  542. /* Rx channel */
  543. if (chan->dirt == DMA_FROM_DEVICE)
  544. hsu_dma_rx(up, int_sts, &flags);
  545. /* Tx channel */
  546. if (chan->dirt == DMA_TO_DEVICE) {
  547. chan_writel(chan, HSU_CH_CR, 0x0);
  548. up->dma_tx_on = 0;
  549. hsu_dma_tx(up);
  550. }
  551. exit:
  552. spin_unlock_irqrestore(&up->port.lock, flags);
  553. return;
  554. }
  555. static irqreturn_t dma_irq(int irq, void *dev_id)
  556. {
  557. struct hsu_port *hsu = dev_id;
  558. u32 int_sts, i;
  559. int_sts = mfd_readl(hsu, HSU_GBL_DMAISR);
  560. /* Currently we only have 6 channels may be used */
  561. for (i = 0; i < 6; i++) {
  562. if (int_sts & 0x1)
  563. dma_chan_irq(&hsu->chans[i]);
  564. int_sts >>= 1;
  565. }
  566. return IRQ_HANDLED;
  567. }
  568. static unsigned int serial_hsu_tx_empty(struct uart_port *port)
  569. {
  570. struct uart_hsu_port *up =
  571. container_of(port, struct uart_hsu_port, port);
  572. unsigned long flags;
  573. unsigned int ret;
  574. spin_lock_irqsave(&up->port.lock, flags);
  575. ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
  576. spin_unlock_irqrestore(&up->port.lock, flags);
  577. return ret;
  578. }
  579. static unsigned int serial_hsu_get_mctrl(struct uart_port *port)
  580. {
  581. struct uart_hsu_port *up =
  582. container_of(port, struct uart_hsu_port, port);
  583. unsigned char status;
  584. unsigned int ret;
  585. status = serial_in(up, UART_MSR);
  586. ret = 0;
  587. if (status & UART_MSR_DCD)
  588. ret |= TIOCM_CAR;
  589. if (status & UART_MSR_RI)
  590. ret |= TIOCM_RNG;
  591. if (status & UART_MSR_DSR)
  592. ret |= TIOCM_DSR;
  593. if (status & UART_MSR_CTS)
  594. ret |= TIOCM_CTS;
  595. return ret;
  596. }
  597. static void serial_hsu_set_mctrl(struct uart_port *port, unsigned int mctrl)
  598. {
  599. struct uart_hsu_port *up =
  600. container_of(port, struct uart_hsu_port, port);
  601. unsigned char mcr = 0;
  602. if (mctrl & TIOCM_RTS)
  603. mcr |= UART_MCR_RTS;
  604. if (mctrl & TIOCM_DTR)
  605. mcr |= UART_MCR_DTR;
  606. if (mctrl & TIOCM_OUT1)
  607. mcr |= UART_MCR_OUT1;
  608. if (mctrl & TIOCM_OUT2)
  609. mcr |= UART_MCR_OUT2;
  610. if (mctrl & TIOCM_LOOP)
  611. mcr |= UART_MCR_LOOP;
  612. mcr |= up->mcr;
  613. serial_out(up, UART_MCR, mcr);
  614. }
  615. static void serial_hsu_break_ctl(struct uart_port *port, int break_state)
  616. {
  617. struct uart_hsu_port *up =
  618. container_of(port, struct uart_hsu_port, port);
  619. unsigned long flags;
  620. spin_lock_irqsave(&up->port.lock, flags);
  621. if (break_state == -1)
  622. up->lcr |= UART_LCR_SBC;
  623. else
  624. up->lcr &= ~UART_LCR_SBC;
  625. serial_out(up, UART_LCR, up->lcr);
  626. spin_unlock_irqrestore(&up->port.lock, flags);
  627. }
  628. /*
  629. * What special to do:
  630. * 1. chose the 64B fifo mode
  631. * 2. start dma or pio depends on configuration
  632. * 3. we only allocate dma memory when needed
  633. */
  634. static int serial_hsu_startup(struct uart_port *port)
  635. {
  636. struct uart_hsu_port *up =
  637. container_of(port, struct uart_hsu_port, port);
  638. unsigned long flags;
  639. pm_runtime_get_sync(up->dev);
  640. /*
  641. * Clear the FIFO buffers and disable them.
  642. * (they will be reenabled in set_termios())
  643. */
  644. serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
  645. serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
  646. UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
  647. serial_out(up, UART_FCR, 0);
  648. /* Clear the interrupt registers. */
  649. (void) serial_in(up, UART_LSR);
  650. (void) serial_in(up, UART_RX);
  651. (void) serial_in(up, UART_IIR);
  652. (void) serial_in(up, UART_MSR);
  653. /* Now, initialize the UART, default is 8n1 */
  654. serial_out(up, UART_LCR, UART_LCR_WLEN8);
  655. spin_lock_irqsave(&up->port.lock, flags);
  656. up->port.mctrl |= TIOCM_OUT2;
  657. serial_hsu_set_mctrl(&up->port, up->port.mctrl);
  658. /*
  659. * Finally, enable interrupts. Note: Modem status interrupts
  660. * are set via set_termios(), which will be occurring imminently
  661. * anyway, so we don't enable them here.
  662. */
  663. if (!up->use_dma)
  664. up->ier = UART_IER_RLSI | UART_IER_RDI | UART_IER_RTOIE;
  665. else
  666. up->ier = 0;
  667. serial_out(up, UART_IER, up->ier);
  668. spin_unlock_irqrestore(&up->port.lock, flags);
  669. /* DMA init */
  670. if (up->use_dma) {
  671. struct hsu_dma_buffer *dbuf;
  672. struct circ_buf *xmit = &port->state->xmit;
  673. up->dma_tx_on = 0;
  674. /* First allocate the RX buffer */
  675. dbuf = &up->rxbuf;
  676. dbuf->buf = kzalloc(HSU_DMA_BUF_SIZE, GFP_KERNEL);
  677. if (!dbuf->buf) {
  678. up->use_dma = 0;
  679. goto exit;
  680. }
  681. dbuf->dma_addr = dma_map_single(port->dev,
  682. dbuf->buf,
  683. HSU_DMA_BUF_SIZE,
  684. DMA_FROM_DEVICE);
  685. dbuf->dma_size = HSU_DMA_BUF_SIZE;
  686. /* Start the RX channel right now */
  687. hsu_dma_start_rx_chan(up->rxc, dbuf);
  688. /* Next init the TX DMA */
  689. dbuf = &up->txbuf;
  690. dbuf->buf = xmit->buf;
  691. dbuf->dma_addr = dma_map_single(port->dev,
  692. dbuf->buf,
  693. UART_XMIT_SIZE,
  694. DMA_TO_DEVICE);
  695. dbuf->dma_size = UART_XMIT_SIZE;
  696. /* This should not be changed all around */
  697. chan_writel(up->txc, HSU_CH_BSR, 32);
  698. chan_writel(up->txc, HSU_CH_MOTSR, 4);
  699. dbuf->ofs = 0;
  700. }
  701. exit:
  702. /* And clear the interrupt registers again for luck. */
  703. (void) serial_in(up, UART_LSR);
  704. (void) serial_in(up, UART_RX);
  705. (void) serial_in(up, UART_IIR);
  706. (void) serial_in(up, UART_MSR);
  707. up->running = 1;
  708. return 0;
  709. }
  710. static void serial_hsu_shutdown(struct uart_port *port)
  711. {
  712. struct uart_hsu_port *up =
  713. container_of(port, struct uart_hsu_port, port);
  714. unsigned long flags;
  715. /* Disable interrupts from this port */
  716. up->ier = 0;
  717. serial_out(up, UART_IER, 0);
  718. up->running = 0;
  719. spin_lock_irqsave(&up->port.lock, flags);
  720. up->port.mctrl &= ~TIOCM_OUT2;
  721. serial_hsu_set_mctrl(&up->port, up->port.mctrl);
  722. spin_unlock_irqrestore(&up->port.lock, flags);
  723. /* Disable break condition and FIFOs */
  724. serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
  725. serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
  726. UART_FCR_CLEAR_RCVR |
  727. UART_FCR_CLEAR_XMIT);
  728. serial_out(up, UART_FCR, 0);
  729. pm_runtime_put(up->dev);
  730. }
  731. static void
  732. serial_hsu_set_termios(struct uart_port *port, struct ktermios *termios,
  733. struct ktermios *old)
  734. {
  735. struct uart_hsu_port *up =
  736. container_of(port, struct uart_hsu_port, port);
  737. unsigned char cval, fcr = 0;
  738. unsigned long flags;
  739. unsigned int baud, quot;
  740. u32 ps, mul;
  741. switch (termios->c_cflag & CSIZE) {
  742. case CS5:
  743. cval = UART_LCR_WLEN5;
  744. break;
  745. case CS6:
  746. cval = UART_LCR_WLEN6;
  747. break;
  748. case CS7:
  749. cval = UART_LCR_WLEN7;
  750. break;
  751. default:
  752. case CS8:
  753. cval = UART_LCR_WLEN8;
  754. break;
  755. }
  756. /* CMSPAR isn't supported by this driver */
  757. termios->c_cflag &= ~CMSPAR;
  758. if (termios->c_cflag & CSTOPB)
  759. cval |= UART_LCR_STOP;
  760. if (termios->c_cflag & PARENB)
  761. cval |= UART_LCR_PARITY;
  762. if (!(termios->c_cflag & PARODD))
  763. cval |= UART_LCR_EPAR;
  764. /*
  765. * The base clk is 50Mhz, and the baud rate come from:
  766. * baud = 50M * MUL / (DIV * PS * DLAB)
  767. *
  768. * For those basic low baud rate we can get the direct
  769. * scalar from 2746800, like 115200 = 2746800/24. For those
  770. * higher baud rate, we handle them case by case, mainly by
  771. * adjusting the MUL/PS registers, and DIV register is kept
  772. * as default value 0x3d09 to make things simple
  773. */
  774. baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
  775. quot = 1;
  776. ps = 0x10;
  777. mul = 0x3600;
  778. switch (baud) {
  779. case 3500000:
  780. mul = 0x3345;
  781. ps = 0xC;
  782. break;
  783. case 1843200:
  784. mul = 0x2400;
  785. break;
  786. case 3000000:
  787. case 2500000:
  788. case 2000000:
  789. case 1500000:
  790. case 1000000:
  791. case 500000:
  792. /* mul/ps/quot = 0x9C4/0x10/0x1 will make a 500000 bps */
  793. mul = baud / 500000 * 0x9C4;
  794. break;
  795. default:
  796. /* Use uart_get_divisor to get quot for other baud rates */
  797. quot = 0;
  798. }
  799. if (!quot)
  800. quot = uart_get_divisor(port, baud);
  801. if ((up->port.uartclk / quot) < (2400 * 16))
  802. fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_1B;
  803. else if ((up->port.uartclk / quot) < (230400 * 16))
  804. fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_16B;
  805. else
  806. fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_32B;
  807. fcr |= UART_FCR_HSU_64B_FIFO;
  808. /*
  809. * Ok, we're now changing the port state. Do it with
  810. * interrupts disabled.
  811. */
  812. spin_lock_irqsave(&up->port.lock, flags);
  813. /* Update the per-port timeout */
  814. uart_update_timeout(port, termios->c_cflag, baud);
  815. up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
  816. if (termios->c_iflag & INPCK)
  817. up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
  818. if (termios->c_iflag & (BRKINT | PARMRK))
  819. up->port.read_status_mask |= UART_LSR_BI;
  820. /* Characters to ignore */
  821. up->port.ignore_status_mask = 0;
  822. if (termios->c_iflag & IGNPAR)
  823. up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
  824. if (termios->c_iflag & IGNBRK) {
  825. up->port.ignore_status_mask |= UART_LSR_BI;
  826. /*
  827. * If we're ignoring parity and break indicators,
  828. * ignore overruns too (for real raw support).
  829. */
  830. if (termios->c_iflag & IGNPAR)
  831. up->port.ignore_status_mask |= UART_LSR_OE;
  832. }
  833. /* Ignore all characters if CREAD is not set */
  834. if ((termios->c_cflag & CREAD) == 0)
  835. up->port.ignore_status_mask |= UART_LSR_DR;
  836. /*
  837. * CTS flow control flag and modem status interrupts, disable
  838. * MSI by default
  839. */
  840. up->ier &= ~UART_IER_MSI;
  841. if (UART_ENABLE_MS(&up->port, termios->c_cflag))
  842. up->ier |= UART_IER_MSI;
  843. serial_out(up, UART_IER, up->ier);
  844. if (termios->c_cflag & CRTSCTS)
  845. up->mcr |= UART_MCR_AFE | UART_MCR_RTS;
  846. else
  847. up->mcr &= ~UART_MCR_AFE;
  848. serial_out(up, UART_LCR, cval | UART_LCR_DLAB); /* set DLAB */
  849. serial_out(up, UART_DLL, quot & 0xff); /* LS of divisor */
  850. serial_out(up, UART_DLM, quot >> 8); /* MS of divisor */
  851. serial_out(up, UART_LCR, cval); /* reset DLAB */
  852. serial_out(up, UART_MUL, mul); /* set MUL */
  853. serial_out(up, UART_PS, ps); /* set PS */
  854. up->lcr = cval; /* Save LCR */
  855. serial_hsu_set_mctrl(&up->port, up->port.mctrl);
  856. serial_out(up, UART_FCR, fcr);
  857. spin_unlock_irqrestore(&up->port.lock, flags);
  858. }
  859. static void
  860. serial_hsu_pm(struct uart_port *port, unsigned int state,
  861. unsigned int oldstate)
  862. {
  863. }
  864. static void serial_hsu_release_port(struct uart_port *port)
  865. {
  866. }
  867. static int serial_hsu_request_port(struct uart_port *port)
  868. {
  869. return 0;
  870. }
  871. static void serial_hsu_config_port(struct uart_port *port, int flags)
  872. {
  873. struct uart_hsu_port *up =
  874. container_of(port, struct uart_hsu_port, port);
  875. up->port.type = PORT_MFD;
  876. }
  877. static int
  878. serial_hsu_verify_port(struct uart_port *port, struct serial_struct *ser)
  879. {
  880. /* We don't want the core code to modify any port params */
  881. return -EINVAL;
  882. }
  883. static const char *
  884. serial_hsu_type(struct uart_port *port)
  885. {
  886. struct uart_hsu_port *up =
  887. container_of(port, struct uart_hsu_port, port);
  888. return up->name;
  889. }
  890. /* Mainly for uart console use */
  891. static struct uart_hsu_port *serial_hsu_ports[3];
  892. static struct uart_driver serial_hsu_reg;
  893. #ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE
  894. #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
  895. /* Wait for transmitter & holding register to empty */
  896. static inline void wait_for_xmitr(struct uart_hsu_port *up)
  897. {
  898. unsigned int status, tmout = 1000;
  899. /* Wait up to 1ms for the character to be sent. */
  900. do {
  901. status = serial_in(up, UART_LSR);
  902. if (status & UART_LSR_BI)
  903. up->lsr_break_flag = UART_LSR_BI;
  904. if (--tmout == 0)
  905. break;
  906. udelay(1);
  907. } while (!(status & BOTH_EMPTY));
  908. /* Wait up to 1s for flow control if necessary */
  909. if (up->port.flags & UPF_CONS_FLOW) {
  910. tmout = 1000000;
  911. while (--tmout &&
  912. ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0))
  913. udelay(1);
  914. }
  915. }
  916. static void serial_hsu_console_putchar(struct uart_port *port, int ch)
  917. {
  918. struct uart_hsu_port *up =
  919. container_of(port, struct uart_hsu_port, port);
  920. wait_for_xmitr(up);
  921. serial_out(up, UART_TX, ch);
  922. }
  923. /*
  924. * Print a string to the serial port trying not to disturb
  925. * any possible real use of the port...
  926. *
  927. * The console_lock must be held when we get here.
  928. */
  929. static void
  930. serial_hsu_console_write(struct console *co, const char *s, unsigned int count)
  931. {
  932. struct uart_hsu_port *up = serial_hsu_ports[co->index];
  933. unsigned long flags;
  934. unsigned int ier;
  935. int locked = 1;
  936. touch_nmi_watchdog();
  937. local_irq_save(flags);
  938. if (up->port.sysrq)
  939. locked = 0;
  940. else if (oops_in_progress) {
  941. locked = spin_trylock(&up->port.lock);
  942. } else
  943. spin_lock(&up->port.lock);
  944. /* First save the IER then disable the interrupts */
  945. ier = serial_in(up, UART_IER);
  946. serial_out(up, UART_IER, 0);
  947. uart_console_write(&up->port, s, count, serial_hsu_console_putchar);
  948. /*
  949. * Finally, wait for transmitter to become empty
  950. * and restore the IER
  951. */
  952. wait_for_xmitr(up);
  953. serial_out(up, UART_IER, ier);
  954. if (locked)
  955. spin_unlock(&up->port.lock);
  956. local_irq_restore(flags);
  957. }
  958. static struct console serial_hsu_console;
  959. static int __init
  960. serial_hsu_console_setup(struct console *co, char *options)
  961. {
  962. struct uart_hsu_port *up;
  963. int baud = 115200;
  964. int bits = 8;
  965. int parity = 'n';
  966. int flow = 'n';
  967. if (co->index == -1 || co->index >= serial_hsu_reg.nr)
  968. co->index = 0;
  969. up = serial_hsu_ports[co->index];
  970. if (!up)
  971. return -ENODEV;
  972. if (options)
  973. uart_parse_options(options, &baud, &parity, &bits, &flow);
  974. return uart_set_options(&up->port, co, baud, parity, bits, flow);
  975. }
  976. static struct console serial_hsu_console = {
  977. .name = "ttyMFD",
  978. .write = serial_hsu_console_write,
  979. .device = uart_console_device,
  980. .setup = serial_hsu_console_setup,
  981. .flags = CON_PRINTBUFFER,
  982. .index = -1,
  983. .data = &serial_hsu_reg,
  984. };
  985. #define SERIAL_HSU_CONSOLE (&serial_hsu_console)
  986. #else
  987. #define SERIAL_HSU_CONSOLE NULL
  988. #endif
  989. struct uart_ops serial_hsu_pops = {
  990. .tx_empty = serial_hsu_tx_empty,
  991. .set_mctrl = serial_hsu_set_mctrl,
  992. .get_mctrl = serial_hsu_get_mctrl,
  993. .stop_tx = serial_hsu_stop_tx,
  994. .start_tx = serial_hsu_start_tx,
  995. .stop_rx = serial_hsu_stop_rx,
  996. .enable_ms = serial_hsu_enable_ms,
  997. .break_ctl = serial_hsu_break_ctl,
  998. .startup = serial_hsu_startup,
  999. .shutdown = serial_hsu_shutdown,
  1000. .set_termios = serial_hsu_set_termios,
  1001. .pm = serial_hsu_pm,
  1002. .type = serial_hsu_type,
  1003. .release_port = serial_hsu_release_port,
  1004. .request_port = serial_hsu_request_port,
  1005. .config_port = serial_hsu_config_port,
  1006. .verify_port = serial_hsu_verify_port,
  1007. };
  1008. static struct uart_driver serial_hsu_reg = {
  1009. .owner = THIS_MODULE,
  1010. .driver_name = "MFD serial",
  1011. .dev_name = "ttyMFD",
  1012. .major = TTY_MAJOR,
  1013. .minor = 128,
  1014. .nr = 3,
  1015. .cons = SERIAL_HSU_CONSOLE,
  1016. };
  1017. #ifdef CONFIG_PM
  1018. static int serial_hsu_suspend(struct pci_dev *pdev, pm_message_t state)
  1019. {
  1020. void *priv = pci_get_drvdata(pdev);
  1021. struct uart_hsu_port *up;
  1022. /* Make sure this is not the internal dma controller */
  1023. if (priv && (pdev->device != 0x081E)) {
  1024. up = priv;
  1025. uart_suspend_port(&serial_hsu_reg, &up->port);
  1026. }
  1027. pci_save_state(pdev);
  1028. pci_set_power_state(pdev, pci_choose_state(pdev, state));
  1029. return 0;
  1030. }
  1031. static int serial_hsu_resume(struct pci_dev *pdev)
  1032. {
  1033. void *priv = pci_get_drvdata(pdev);
  1034. struct uart_hsu_port *up;
  1035. int ret;
  1036. pci_set_power_state(pdev, PCI_D0);
  1037. pci_restore_state(pdev);
  1038. ret = pci_enable_device(pdev);
  1039. if (ret)
  1040. dev_warn(&pdev->dev,
  1041. "HSU: can't re-enable device, try to continue\n");
  1042. if (priv && (pdev->device != 0x081E)) {
  1043. up = priv;
  1044. uart_resume_port(&serial_hsu_reg, &up->port);
  1045. }
  1046. return 0;
  1047. }
  1048. #else
  1049. #define serial_hsu_suspend NULL
  1050. #define serial_hsu_resume NULL
  1051. #endif
  1052. #ifdef CONFIG_PM_RUNTIME
  1053. static int serial_hsu_runtime_idle(struct device *dev)
  1054. {
  1055. pm_schedule_suspend(dev, 500);
  1056. return -EBUSY;
  1057. }
  1058. static int serial_hsu_runtime_suspend(struct device *dev)
  1059. {
  1060. return 0;
  1061. }
  1062. static int serial_hsu_runtime_resume(struct device *dev)
  1063. {
  1064. return 0;
  1065. }
  1066. #else
  1067. #define serial_hsu_runtime_idle NULL
  1068. #define serial_hsu_runtime_suspend NULL
  1069. #define serial_hsu_runtime_resume NULL
  1070. #endif
  1071. static const struct dev_pm_ops serial_hsu_pm_ops = {
  1072. .runtime_suspend = serial_hsu_runtime_suspend,
  1073. .runtime_resume = serial_hsu_runtime_resume,
  1074. .runtime_idle = serial_hsu_runtime_idle,
  1075. };
  1076. /* temp global pointer before we settle down on using one or four PCI dev */
  1077. static struct hsu_port *phsu;
  1078. static int serial_hsu_probe(struct pci_dev *pdev,
  1079. const struct pci_device_id *ent)
  1080. {
  1081. struct uart_hsu_port *uport;
  1082. int index, ret;
  1083. printk(KERN_INFO "HSU: found PCI Serial controller(ID: %04x:%04x)\n",
  1084. pdev->vendor, pdev->device);
  1085. switch (pdev->device) {
  1086. case 0x081B:
  1087. index = 0;
  1088. break;
  1089. case 0x081C:
  1090. index = 1;
  1091. break;
  1092. case 0x081D:
  1093. index = 2;
  1094. break;
  1095. case 0x081E:
  1096. /* internal DMA controller */
  1097. index = 3;
  1098. break;
  1099. default:
  1100. dev_err(&pdev->dev, "HSU: out of index!");
  1101. return -ENODEV;
  1102. }
  1103. ret = pci_enable_device(pdev);
  1104. if (ret)
  1105. return ret;
  1106. if (index == 3) {
  1107. /* DMA controller */
  1108. ret = request_irq(pdev->irq, dma_irq, 0, "hsu_dma", phsu);
  1109. if (ret) {
  1110. dev_err(&pdev->dev, "can not get IRQ\n");
  1111. goto err_disable;
  1112. }
  1113. pci_set_drvdata(pdev, phsu);
  1114. } else {
  1115. /* UART port 0~2 */
  1116. uport = &phsu->port[index];
  1117. uport->port.irq = pdev->irq;
  1118. uport->port.dev = &pdev->dev;
  1119. uport->dev = &pdev->dev;
  1120. ret = request_irq(pdev->irq, port_irq, 0, uport->name, uport);
  1121. if (ret) {
  1122. dev_err(&pdev->dev, "can not get IRQ\n");
  1123. goto err_disable;
  1124. }
  1125. uart_add_one_port(&serial_hsu_reg, &uport->port);
  1126. pci_set_drvdata(pdev, uport);
  1127. }
  1128. pm_runtime_put_noidle(&pdev->dev);
  1129. pm_runtime_allow(&pdev->dev);
  1130. return 0;
  1131. err_disable:
  1132. pci_disable_device(pdev);
  1133. return ret;
  1134. }
  1135. static void hsu_global_init(void)
  1136. {
  1137. struct hsu_port *hsu;
  1138. struct uart_hsu_port *uport;
  1139. struct hsu_dma_chan *dchan;
  1140. int i, ret;
  1141. hsu = kzalloc(sizeof(struct hsu_port), GFP_KERNEL);
  1142. if (!hsu)
  1143. return;
  1144. /* Get basic io resource and map it */
  1145. hsu->paddr = 0xffa28000;
  1146. hsu->iolen = 0x1000;
  1147. if (!(request_mem_region(hsu->paddr, hsu->iolen, "HSU global")))
  1148. pr_warning("HSU: error in request mem region\n");
  1149. hsu->reg = ioremap_nocache((unsigned long)hsu->paddr, hsu->iolen);
  1150. if (!hsu->reg) {
  1151. pr_err("HSU: error in ioremap\n");
  1152. ret = -ENOMEM;
  1153. goto err_free_region;
  1154. }
  1155. /* Initialise the 3 UART ports */
  1156. uport = hsu->port;
  1157. for (i = 0; i < 3; i++) {
  1158. uport->port.type = PORT_MFD;
  1159. uport->port.iotype = UPIO_MEM;
  1160. uport->port.mapbase = (resource_size_t)hsu->paddr
  1161. + HSU_PORT_REG_OFFSET
  1162. + i * HSU_PORT_REG_LENGTH;
  1163. uport->port.membase = hsu->reg + HSU_PORT_REG_OFFSET
  1164. + i * HSU_PORT_REG_LENGTH;
  1165. sprintf(uport->name, "hsu_port%d", i);
  1166. uport->port.fifosize = 64;
  1167. uport->port.ops = &serial_hsu_pops;
  1168. uport->port.line = i;
  1169. uport->port.flags = UPF_IOREMAP;
  1170. /* set the scalable maxim support rate to 2746800 bps */
  1171. uport->port.uartclk = 115200 * 24 * 16;
  1172. uport->running = 0;
  1173. uport->txc = &hsu->chans[i * 2];
  1174. uport->rxc = &hsu->chans[i * 2 + 1];
  1175. serial_hsu_ports[i] = uport;
  1176. uport->index = i;
  1177. if (hsu_dma_enable & (1<<i))
  1178. uport->use_dma = 1;
  1179. else
  1180. uport->use_dma = 0;
  1181. uport++;
  1182. }
  1183. /* Initialise 6 dma channels */
  1184. dchan = hsu->chans;
  1185. for (i = 0; i < 6; i++) {
  1186. dchan->id = i;
  1187. dchan->dirt = (i & 0x1) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
  1188. dchan->uport = &hsu->port[i/2];
  1189. dchan->reg = hsu->reg + HSU_DMA_CHANS_REG_OFFSET +
  1190. i * HSU_DMA_CHANS_REG_LENGTH;
  1191. dchan++;
  1192. }
  1193. phsu = hsu;
  1194. hsu_debugfs_init(hsu);
  1195. return;
  1196. err_free_region:
  1197. release_mem_region(hsu->paddr, hsu->iolen);
  1198. kfree(hsu);
  1199. return;
  1200. }
  1201. static void serial_hsu_remove(struct pci_dev *pdev)
  1202. {
  1203. void *priv = pci_get_drvdata(pdev);
  1204. struct uart_hsu_port *up;
  1205. if (!priv)
  1206. return;
  1207. pm_runtime_forbid(&pdev->dev);
  1208. pm_runtime_get_noresume(&pdev->dev);
  1209. /* For port 0/1/2, priv is the address of uart_hsu_port */
  1210. if (pdev->device != 0x081E) {
  1211. up = priv;
  1212. uart_remove_one_port(&serial_hsu_reg, &up->port);
  1213. }
  1214. pci_set_drvdata(pdev, NULL);
  1215. free_irq(pdev->irq, priv);
  1216. pci_disable_device(pdev);
  1217. }
  1218. /* First 3 are UART ports, and the 4th is the DMA */
  1219. static const struct pci_device_id pci_ids[] = {
  1220. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081B) },
  1221. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081C) },
  1222. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081D) },
  1223. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081E) },
  1224. {},
  1225. };
  1226. static struct pci_driver hsu_pci_driver = {
  1227. .name = "HSU serial",
  1228. .id_table = pci_ids,
  1229. .probe = serial_hsu_probe,
  1230. .remove = serial_hsu_remove,
  1231. .suspend = serial_hsu_suspend,
  1232. .resume = serial_hsu_resume,
  1233. .driver = {
  1234. .pm = &serial_hsu_pm_ops,
  1235. },
  1236. };
  1237. static int __init hsu_pci_init(void)
  1238. {
  1239. int ret;
  1240. hsu_global_init();
  1241. ret = uart_register_driver(&serial_hsu_reg);
  1242. if (ret)
  1243. return ret;
  1244. return pci_register_driver(&hsu_pci_driver);
  1245. }
  1246. static void __exit hsu_pci_exit(void)
  1247. {
  1248. pci_unregister_driver(&hsu_pci_driver);
  1249. uart_unregister_driver(&serial_hsu_reg);
  1250. hsu_debugfs_remove(phsu);
  1251. kfree(phsu);
  1252. }
  1253. module_init(hsu_pci_init);
  1254. module_exit(hsu_pci_exit);
  1255. MODULE_LICENSE("GPL v2");
  1256. MODULE_ALIAS("platform:medfield-hsu");