/drivers/tty/serial/ucc_uart.c

http://github.com/mirrors/linux · C · 1549 lines · 990 code · 215 blank · 344 comment · 121 complexity · 379c27c8fef2a41641fb6e47fe3d2a77 MD5 · raw file

  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Freescale QUICC Engine UART device driver
  4. *
  5. * Author: Timur Tabi <timur@freescale.com>
  6. *
  7. * Copyright 2007 Freescale Semiconductor, Inc.
  8. *
  9. * This driver adds support for UART devices via Freescale's QUICC Engine
  10. * found on some Freescale SOCs.
  11. *
  12. * If Soft-UART support is needed but not already present, then this driver
  13. * will request and upload the "Soft-UART" microcode upon probe. The
  14. * filename of the microcode should be fsl_qe_ucode_uart_X_YZ.bin, where "X"
  15. * is the name of the SOC (e.g. 8323), and YZ is the revision of the SOC,
  16. * (e.g. "11" for 1.1).
  17. */
  18. #include <linux/module.h>
  19. #include <linux/serial.h>
  20. #include <linux/serial_core.h>
  21. #include <linux/slab.h>
  22. #include <linux/tty.h>
  23. #include <linux/tty_flip.h>
  24. #include <linux/io.h>
  25. #include <linux/of_address.h>
  26. #include <linux/of_irq.h>
  27. #include <linux/of_platform.h>
  28. #include <linux/dma-mapping.h>
  29. #include <linux/fs_uart_pd.h>
  30. #include <soc/fsl/qe/ucc_slow.h>
  31. #include <linux/firmware.h>
  32. #include <soc/fsl/cpm.h>
  33. #ifdef CONFIG_PPC32
  34. #include <asm/reg.h> /* mfspr, SPRN_SVR */
  35. #endif
  36. /*
  37. * The GUMR flag for Soft UART. This would normally be defined in qe.h,
  38. * but Soft-UART is a hack and we want to keep everything related to it in
  39. * this file.
  40. */
  41. #define UCC_SLOW_GUMR_H_SUART 0x00004000 /* Soft-UART */
  42. /*
  43. * soft_uart is 1 if we need to use Soft-UART mode
  44. */
  45. static int soft_uart;
  46. /*
  47. * firmware_loaded is 1 if the firmware has been loaded, 0 otherwise.
  48. */
  49. static int firmware_loaded;
  50. /* Enable this macro to configure all serial ports in internal loopback
  51. mode */
  52. /* #define LOOPBACK */
  53. /* The major and minor device numbers are defined in
  54. * http://www.lanana.org/docs/device-list/devices-2.6+.txt. For the QE
  55. * UART, we have major number 204 and minor numbers 46 - 49, which are the
  56. * same as for the CPM2. This decision was made because no Freescale part
  57. * has both a CPM and a QE.
  58. */
  59. #define SERIAL_QE_MAJOR 204
  60. #define SERIAL_QE_MINOR 46
  61. /* Since we only have minor numbers 46 - 49, there is a hard limit of 4 ports */
  62. #define UCC_MAX_UART 4
  63. /* The number of buffer descriptors for receiving characters. */
  64. #define RX_NUM_FIFO 4
  65. /* The number of buffer descriptors for transmitting characters. */
  66. #define TX_NUM_FIFO 4
  67. /* The maximum size of the character buffer for a single RX BD. */
  68. #define RX_BUF_SIZE 32
  69. /* The maximum size of the character buffer for a single TX BD. */
  70. #define TX_BUF_SIZE 32
  71. /*
  72. * The number of jiffies to wait after receiving a close command before the
  73. * device is actually closed. This allows the last few characters to be
  74. * sent over the wire.
  75. */
  76. #define UCC_WAIT_CLOSING 100
  77. struct ucc_uart_pram {
  78. struct ucc_slow_pram common;
  79. u8 res1[8]; /* reserved */
  80. __be16 maxidl; /* Maximum idle chars */
  81. __be16 idlc; /* temp idle counter */
  82. __be16 brkcr; /* Break count register */
  83. __be16 parec; /* receive parity error counter */
  84. __be16 frmec; /* receive framing error counter */
  85. __be16 nosec; /* receive noise counter */
  86. __be16 brkec; /* receive break condition counter */
  87. __be16 brkln; /* last received break length */
  88. __be16 uaddr[2]; /* UART address character 1 & 2 */
  89. __be16 rtemp; /* Temp storage */
  90. __be16 toseq; /* Transmit out of sequence char */
  91. __be16 cchars[8]; /* control characters 1-8 */
  92. __be16 rccm; /* receive control character mask */
  93. __be16 rccr; /* receive control character register */
  94. __be16 rlbc; /* receive last break character */
  95. __be16 res2; /* reserved */
  96. __be32 res3; /* reserved, should be cleared */
  97. u8 res4; /* reserved, should be cleared */
  98. u8 res5[3]; /* reserved, should be cleared */
  99. __be32 res6; /* reserved, should be cleared */
  100. __be32 res7; /* reserved, should be cleared */
  101. __be32 res8; /* reserved, should be cleared */
  102. __be32 res9; /* reserved, should be cleared */
  103. __be32 res10; /* reserved, should be cleared */
  104. __be32 res11; /* reserved, should be cleared */
  105. __be32 res12; /* reserved, should be cleared */
  106. __be32 res13; /* reserved, should be cleared */
  107. /* The rest is for Soft-UART only */
  108. __be16 supsmr; /* 0x90, Shadow UPSMR */
  109. __be16 res92; /* 0x92, reserved, initialize to 0 */
  110. __be32 rx_state; /* 0x94, RX state, initialize to 0 */
  111. __be32 rx_cnt; /* 0x98, RX count, initialize to 0 */
  112. u8 rx_length; /* 0x9C, Char length, set to 1+CL+PEN+1+SL */
  113. u8 rx_bitmark; /* 0x9D, reserved, initialize to 0 */
  114. u8 rx_temp_dlst_qe; /* 0x9E, reserved, initialize to 0 */
  115. u8 res14[0xBC - 0x9F]; /* reserved */
  116. __be32 dump_ptr; /* 0xBC, Dump pointer */
  117. __be32 rx_frame_rem; /* 0xC0, reserved, initialize to 0 */
  118. u8 rx_frame_rem_size; /* 0xC4, reserved, initialize to 0 */
  119. u8 tx_mode; /* 0xC5, mode, 0=AHDLC, 1=UART */
  120. __be16 tx_state; /* 0xC6, TX state */
  121. u8 res15[0xD0 - 0xC8]; /* reserved */
  122. __be32 resD0; /* 0xD0, reserved, initialize to 0 */
  123. u8 resD4; /* 0xD4, reserved, initialize to 0 */
  124. __be16 resD5; /* 0xD5, reserved, initialize to 0 */
  125. } __attribute__ ((packed));
  126. /* SUPSMR definitions, for Soft-UART only */
  127. #define UCC_UART_SUPSMR_SL 0x8000
  128. #define UCC_UART_SUPSMR_RPM_MASK 0x6000
  129. #define UCC_UART_SUPSMR_RPM_ODD 0x0000
  130. #define UCC_UART_SUPSMR_RPM_LOW 0x2000
  131. #define UCC_UART_SUPSMR_RPM_EVEN 0x4000
  132. #define UCC_UART_SUPSMR_RPM_HIGH 0x6000
  133. #define UCC_UART_SUPSMR_PEN 0x1000
  134. #define UCC_UART_SUPSMR_TPM_MASK 0x0C00
  135. #define UCC_UART_SUPSMR_TPM_ODD 0x0000
  136. #define UCC_UART_SUPSMR_TPM_LOW 0x0400
  137. #define UCC_UART_SUPSMR_TPM_EVEN 0x0800
  138. #define UCC_UART_SUPSMR_TPM_HIGH 0x0C00
  139. #define UCC_UART_SUPSMR_FRZ 0x0100
  140. #define UCC_UART_SUPSMR_UM_MASK 0x00c0
  141. #define UCC_UART_SUPSMR_UM_NORMAL 0x0000
  142. #define UCC_UART_SUPSMR_UM_MAN_MULTI 0x0040
  143. #define UCC_UART_SUPSMR_UM_AUTO_MULTI 0x00c0
  144. #define UCC_UART_SUPSMR_CL_MASK 0x0030
  145. #define UCC_UART_SUPSMR_CL_8 0x0030
  146. #define UCC_UART_SUPSMR_CL_7 0x0020
  147. #define UCC_UART_SUPSMR_CL_6 0x0010
  148. #define UCC_UART_SUPSMR_CL_5 0x0000
  149. #define UCC_UART_TX_STATE_AHDLC 0x00
  150. #define UCC_UART_TX_STATE_UART 0x01
  151. #define UCC_UART_TX_STATE_X1 0x00
  152. #define UCC_UART_TX_STATE_X16 0x80
  153. #define UCC_UART_PRAM_ALIGNMENT 0x100
  154. #define UCC_UART_SIZE_OF_BD UCC_SLOW_SIZE_OF_BD
  155. #define NUM_CONTROL_CHARS 8
  156. /* Private per-port data structure */
  157. struct uart_qe_port {
  158. struct uart_port port;
  159. struct ucc_slow __iomem *uccp;
  160. struct ucc_uart_pram __iomem *uccup;
  161. struct ucc_slow_info us_info;
  162. struct ucc_slow_private *us_private;
  163. struct device_node *np;
  164. unsigned int ucc_num; /* First ucc is 0, not 1 */
  165. u16 rx_nrfifos;
  166. u16 rx_fifosize;
  167. u16 tx_nrfifos;
  168. u16 tx_fifosize;
  169. int wait_closing;
  170. u32 flags;
  171. struct qe_bd *rx_bd_base;
  172. struct qe_bd *rx_cur;
  173. struct qe_bd *tx_bd_base;
  174. struct qe_bd *tx_cur;
  175. unsigned char *tx_buf;
  176. unsigned char *rx_buf;
  177. void *bd_virt; /* virtual address of the BD buffers */
  178. dma_addr_t bd_dma_addr; /* bus address of the BD buffers */
  179. unsigned int bd_size; /* size of BD buffer space */
  180. };
  181. static struct uart_driver ucc_uart_driver = {
  182. .owner = THIS_MODULE,
  183. .driver_name = "ucc_uart",
  184. .dev_name = "ttyQE",
  185. .major = SERIAL_QE_MAJOR,
  186. .minor = SERIAL_QE_MINOR,
  187. .nr = UCC_MAX_UART,
  188. };
  189. /*
  190. * Virtual to physical address translation.
  191. *
  192. * Given the virtual address for a character buffer, this function returns
  193. * the physical (DMA) equivalent.
  194. */
  195. static inline dma_addr_t cpu2qe_addr(void *addr, struct uart_qe_port *qe_port)
  196. {
  197. if (likely((addr >= qe_port->bd_virt)) &&
  198. (addr < (qe_port->bd_virt + qe_port->bd_size)))
  199. return qe_port->bd_dma_addr + (addr - qe_port->bd_virt);
  200. /* something nasty happened */
  201. printk(KERN_ERR "%s: addr=%p\n", __func__, addr);
  202. BUG();
  203. return 0;
  204. }
  205. /*
  206. * Physical to virtual address translation.
  207. *
  208. * Given the physical (DMA) address for a character buffer, this function
  209. * returns the virtual equivalent.
  210. */
  211. static inline void *qe2cpu_addr(dma_addr_t addr, struct uart_qe_port *qe_port)
  212. {
  213. /* sanity check */
  214. if (likely((addr >= qe_port->bd_dma_addr) &&
  215. (addr < (qe_port->bd_dma_addr + qe_port->bd_size))))
  216. return qe_port->bd_virt + (addr - qe_port->bd_dma_addr);
  217. /* something nasty happened */
  218. printk(KERN_ERR "%s: addr=%llx\n", __func__, (u64)addr);
  219. BUG();
  220. return NULL;
  221. }
  222. /*
  223. * Return 1 if the QE is done transmitting all buffers for this port
  224. *
  225. * This function scans each BD in sequence. If we find a BD that is not
  226. * ready (READY=1), then we return 0 indicating that the QE is still sending
  227. * data. If we reach the last BD (WRAP=1), then we know we've scanned
  228. * the entire list, and all BDs are done.
  229. */
  230. static unsigned int qe_uart_tx_empty(struct uart_port *port)
  231. {
  232. struct uart_qe_port *qe_port =
  233. container_of(port, struct uart_qe_port, port);
  234. struct qe_bd *bdp = qe_port->tx_bd_base;
  235. while (1) {
  236. if (qe_ioread16be(&bdp->status) & BD_SC_READY)
  237. /* This BD is not done, so return "not done" */
  238. return 0;
  239. if (qe_ioread16be(&bdp->status) & BD_SC_WRAP)
  240. /*
  241. * This BD is done and it's the last one, so return
  242. * "done"
  243. */
  244. return 1;
  245. bdp++;
  246. }
  247. }
  248. /*
  249. * Set the modem control lines
  250. *
  251. * Although the QE can control the modem control lines (e.g. CTS), we
  252. * don't need that support. This function must exist, however, otherwise
  253. * the kernel will panic.
  254. */
  255. void qe_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
  256. {
  257. }
  258. /*
  259. * Get the current modem control line status
  260. *
  261. * Although the QE can control the modem control lines (e.g. CTS), this
  262. * driver currently doesn't support that, so we always return Carrier
  263. * Detect, Data Set Ready, and Clear To Send.
  264. */
  265. static unsigned int qe_uart_get_mctrl(struct uart_port *port)
  266. {
  267. return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
  268. }
  269. /*
  270. * Disable the transmit interrupt.
  271. *
  272. * Although this function is called "stop_tx", it does not actually stop
  273. * transmission of data. Instead, it tells the QE to not generate an
  274. * interrupt when the UCC is finished sending characters.
  275. */
  276. static void qe_uart_stop_tx(struct uart_port *port)
  277. {
  278. struct uart_qe_port *qe_port =
  279. container_of(port, struct uart_qe_port, port);
  280. qe_clrbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX);
  281. }
  282. /*
  283. * Transmit as many characters to the HW as possible.
  284. *
  285. * This function will attempt to stuff of all the characters from the
  286. * kernel's transmit buffer into TX BDs.
  287. *
  288. * A return value of non-zero indicates that it successfully stuffed all
  289. * characters from the kernel buffer.
  290. *
  291. * A return value of zero indicates that there are still characters in the
  292. * kernel's buffer that have not been transmitted, but there are no more BDs
  293. * available. This function should be called again after a BD has been made
  294. * available.
  295. */
  296. static int qe_uart_tx_pump(struct uart_qe_port *qe_port)
  297. {
  298. struct qe_bd *bdp;
  299. unsigned char *p;
  300. unsigned int count;
  301. struct uart_port *port = &qe_port->port;
  302. struct circ_buf *xmit = &port->state->xmit;
  303. /* Handle xon/xoff */
  304. if (port->x_char) {
  305. /* Pick next descriptor and fill from buffer */
  306. bdp = qe_port->tx_cur;
  307. p = qe2cpu_addr(be32_to_cpu(bdp->buf), qe_port);
  308. *p++ = port->x_char;
  309. qe_iowrite16be(1, &bdp->length);
  310. qe_setbits_be16(&bdp->status, BD_SC_READY);
  311. /* Get next BD. */
  312. if (qe_ioread16be(&bdp->status) & BD_SC_WRAP)
  313. bdp = qe_port->tx_bd_base;
  314. else
  315. bdp++;
  316. qe_port->tx_cur = bdp;
  317. port->icount.tx++;
  318. port->x_char = 0;
  319. return 1;
  320. }
  321. if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
  322. qe_uart_stop_tx(port);
  323. return 0;
  324. }
  325. /* Pick next descriptor and fill from buffer */
  326. bdp = qe_port->tx_cur;
  327. while (!(qe_ioread16be(&bdp->status) & BD_SC_READY) &&
  328. (xmit->tail != xmit->head)) {
  329. count = 0;
  330. p = qe2cpu_addr(be32_to_cpu(bdp->buf), qe_port);
  331. while (count < qe_port->tx_fifosize) {
  332. *p++ = xmit->buf[xmit->tail];
  333. xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
  334. port->icount.tx++;
  335. count++;
  336. if (xmit->head == xmit->tail)
  337. break;
  338. }
  339. qe_iowrite16be(count, &bdp->length);
  340. qe_setbits_be16(&bdp->status, BD_SC_READY);
  341. /* Get next BD. */
  342. if (qe_ioread16be(&bdp->status) & BD_SC_WRAP)
  343. bdp = qe_port->tx_bd_base;
  344. else
  345. bdp++;
  346. }
  347. qe_port->tx_cur = bdp;
  348. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  349. uart_write_wakeup(port);
  350. if (uart_circ_empty(xmit)) {
  351. /* The kernel buffer is empty, so turn off TX interrupts. We
  352. don't need to be told when the QE is finished transmitting
  353. the data. */
  354. qe_uart_stop_tx(port);
  355. return 0;
  356. }
  357. return 1;
  358. }
  359. /*
  360. * Start transmitting data
  361. *
  362. * This function will start transmitting any available data, if the port
  363. * isn't already transmitting data.
  364. */
  365. static void qe_uart_start_tx(struct uart_port *port)
  366. {
  367. struct uart_qe_port *qe_port =
  368. container_of(port, struct uart_qe_port, port);
  369. /* If we currently are transmitting, then just return */
  370. if (qe_ioread16be(&qe_port->uccp->uccm) & UCC_UART_UCCE_TX)
  371. return;
  372. /* Otherwise, pump the port and start transmission */
  373. if (qe_uart_tx_pump(qe_port))
  374. qe_setbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX);
  375. }
  376. /*
  377. * Stop transmitting data
  378. */
  379. static void qe_uart_stop_rx(struct uart_port *port)
  380. {
  381. struct uart_qe_port *qe_port =
  382. container_of(port, struct uart_qe_port, port);
  383. qe_clrbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX);
  384. }
  385. /* Start or stop sending break signal
  386. *
  387. * This function controls the sending of a break signal. If break_state=1,
  388. * then we start sending a break signal. If break_state=0, then we stop
  389. * sending the break signal.
  390. */
  391. static void qe_uart_break_ctl(struct uart_port *port, int break_state)
  392. {
  393. struct uart_qe_port *qe_port =
  394. container_of(port, struct uart_qe_port, port);
  395. if (break_state)
  396. ucc_slow_stop_tx(qe_port->us_private);
  397. else
  398. ucc_slow_restart_tx(qe_port->us_private);
  399. }
  400. /* ISR helper function for receiving character.
  401. *
  402. * This function is called by the ISR to handling receiving characters
  403. */
  404. static void qe_uart_int_rx(struct uart_qe_port *qe_port)
  405. {
  406. int i;
  407. unsigned char ch, *cp;
  408. struct uart_port *port = &qe_port->port;
  409. struct tty_port *tport = &port->state->port;
  410. struct qe_bd *bdp;
  411. u16 status;
  412. unsigned int flg;
  413. /* Just loop through the closed BDs and copy the characters into
  414. * the buffer.
  415. */
  416. bdp = qe_port->rx_cur;
  417. while (1) {
  418. status = qe_ioread16be(&bdp->status);
  419. /* If this one is empty, then we assume we've read them all */
  420. if (status & BD_SC_EMPTY)
  421. break;
  422. /* get number of characters, and check space in RX buffer */
  423. i = qe_ioread16be(&bdp->length);
  424. /* If we don't have enough room in RX buffer for the entire BD,
  425. * then we try later, which will be the next RX interrupt.
  426. */
  427. if (tty_buffer_request_room(tport, i) < i) {
  428. dev_dbg(port->dev, "ucc-uart: no room in RX buffer\n");
  429. return;
  430. }
  431. /* get pointer */
  432. cp = qe2cpu_addr(be32_to_cpu(bdp->buf), qe_port);
  433. /* loop through the buffer */
  434. while (i-- > 0) {
  435. ch = *cp++;
  436. port->icount.rx++;
  437. flg = TTY_NORMAL;
  438. if (!i && status &
  439. (BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV))
  440. goto handle_error;
  441. if (uart_handle_sysrq_char(port, ch))
  442. continue;
  443. error_return:
  444. tty_insert_flip_char(tport, ch, flg);
  445. }
  446. /* This BD is ready to be used again. Clear status. get next */
  447. qe_clrsetbits_be16(&bdp->status,
  448. BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV | BD_SC_ID,
  449. BD_SC_EMPTY);
  450. if (qe_ioread16be(&bdp->status) & BD_SC_WRAP)
  451. bdp = qe_port->rx_bd_base;
  452. else
  453. bdp++;
  454. }
  455. /* Write back buffer pointer */
  456. qe_port->rx_cur = bdp;
  457. /* Activate BH processing */
  458. tty_flip_buffer_push(tport);
  459. return;
  460. /* Error processing */
  461. handle_error:
  462. /* Statistics */
  463. if (status & BD_SC_BR)
  464. port->icount.brk++;
  465. if (status & BD_SC_PR)
  466. port->icount.parity++;
  467. if (status & BD_SC_FR)
  468. port->icount.frame++;
  469. if (status & BD_SC_OV)
  470. port->icount.overrun++;
  471. /* Mask out ignored conditions */
  472. status &= port->read_status_mask;
  473. /* Handle the remaining ones */
  474. if (status & BD_SC_BR)
  475. flg = TTY_BREAK;
  476. else if (status & BD_SC_PR)
  477. flg = TTY_PARITY;
  478. else if (status & BD_SC_FR)
  479. flg = TTY_FRAME;
  480. /* Overrun does not affect the current character ! */
  481. if (status & BD_SC_OV)
  482. tty_insert_flip_char(tport, 0, TTY_OVERRUN);
  483. port->sysrq = 0;
  484. goto error_return;
  485. }
  486. /* Interrupt handler
  487. *
  488. * This interrupt handler is called after a BD is processed.
  489. */
  490. static irqreturn_t qe_uart_int(int irq, void *data)
  491. {
  492. struct uart_qe_port *qe_port = (struct uart_qe_port *) data;
  493. struct ucc_slow __iomem *uccp = qe_port->uccp;
  494. u16 events;
  495. /* Clear the interrupts */
  496. events = qe_ioread16be(&uccp->ucce);
  497. qe_iowrite16be(events, &uccp->ucce);
  498. if (events & UCC_UART_UCCE_BRKE)
  499. uart_handle_break(&qe_port->port);
  500. if (events & UCC_UART_UCCE_RX)
  501. qe_uart_int_rx(qe_port);
  502. if (events & UCC_UART_UCCE_TX)
  503. qe_uart_tx_pump(qe_port);
  504. return events ? IRQ_HANDLED : IRQ_NONE;
  505. }
  506. /* Initialize buffer descriptors
  507. *
  508. * This function initializes all of the RX and TX buffer descriptors.
  509. */
  510. static void qe_uart_initbd(struct uart_qe_port *qe_port)
  511. {
  512. int i;
  513. void *bd_virt;
  514. struct qe_bd *bdp;
  515. /* Set the physical address of the host memory buffers in the buffer
  516. * descriptors, and the virtual address for us to work with.
  517. */
  518. bd_virt = qe_port->bd_virt;
  519. bdp = qe_port->rx_bd_base;
  520. qe_port->rx_cur = qe_port->rx_bd_base;
  521. for (i = 0; i < (qe_port->rx_nrfifos - 1); i++) {
  522. qe_iowrite16be(BD_SC_EMPTY | BD_SC_INTRPT, &bdp->status);
  523. qe_iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
  524. qe_iowrite16be(0, &bdp->length);
  525. bd_virt += qe_port->rx_fifosize;
  526. bdp++;
  527. }
  528. /* */
  529. qe_iowrite16be(BD_SC_WRAP | BD_SC_EMPTY | BD_SC_INTRPT, &bdp->status);
  530. qe_iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
  531. qe_iowrite16be(0, &bdp->length);
  532. /* Set the physical address of the host memory
  533. * buffers in the buffer descriptors, and the
  534. * virtual address for us to work with.
  535. */
  536. bd_virt = qe_port->bd_virt +
  537. L1_CACHE_ALIGN(qe_port->rx_nrfifos * qe_port->rx_fifosize);
  538. qe_port->tx_cur = qe_port->tx_bd_base;
  539. bdp = qe_port->tx_bd_base;
  540. for (i = 0; i < (qe_port->tx_nrfifos - 1); i++) {
  541. qe_iowrite16be(BD_SC_INTRPT, &bdp->status);
  542. qe_iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
  543. qe_iowrite16be(0, &bdp->length);
  544. bd_virt += qe_port->tx_fifosize;
  545. bdp++;
  546. }
  547. /* Loopback requires the preamble bit to be set on the first TX BD */
  548. #ifdef LOOPBACK
  549. qe_setbits_be16(&qe_port->tx_cur->status, BD_SC_P);
  550. #endif
  551. qe_iowrite16be(BD_SC_WRAP | BD_SC_INTRPT, &bdp->status);
  552. qe_iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
  553. qe_iowrite16be(0, &bdp->length);
  554. }
  555. /*
  556. * Initialize a UCC for UART.
  557. *
  558. * This function configures a given UCC to be used as a UART device. Basic
  559. * UCC initialization is handled in qe_uart_request_port(). This function
  560. * does all the UART-specific stuff.
  561. */
  562. static void qe_uart_init_ucc(struct uart_qe_port *qe_port)
  563. {
  564. u32 cecr_subblock;
  565. struct ucc_slow __iomem *uccp = qe_port->uccp;
  566. struct ucc_uart_pram *uccup = qe_port->uccup;
  567. unsigned int i;
  568. /* First, disable TX and RX in the UCC */
  569. ucc_slow_disable(qe_port->us_private, COMM_DIR_RX_AND_TX);
  570. /* Program the UCC UART parameter RAM */
  571. qe_iowrite8(UCC_BMR_GBL | UCC_BMR_BO_BE, &uccup->common.rbmr);
  572. qe_iowrite8(UCC_BMR_GBL | UCC_BMR_BO_BE, &uccup->common.tbmr);
  573. qe_iowrite16be(qe_port->rx_fifosize, &uccup->common.mrblr);
  574. qe_iowrite16be(0x10, &uccup->maxidl);
  575. qe_iowrite16be(1, &uccup->brkcr);
  576. qe_iowrite16be(0, &uccup->parec);
  577. qe_iowrite16be(0, &uccup->frmec);
  578. qe_iowrite16be(0, &uccup->nosec);
  579. qe_iowrite16be(0, &uccup->brkec);
  580. qe_iowrite16be(0, &uccup->uaddr[0]);
  581. qe_iowrite16be(0, &uccup->uaddr[1]);
  582. qe_iowrite16be(0, &uccup->toseq);
  583. for (i = 0; i < 8; i++)
  584. qe_iowrite16be(0xC000, &uccup->cchars[i]);
  585. qe_iowrite16be(0xc0ff, &uccup->rccm);
  586. /* Configure the GUMR registers for UART */
  587. if (soft_uart) {
  588. /* Soft-UART requires a 1X multiplier for TX */
  589. qe_clrsetbits_be32(&uccp->gumr_l,
  590. UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK | UCC_SLOW_GUMR_L_RDCR_MASK,
  591. UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_1 | UCC_SLOW_GUMR_L_RDCR_16);
  592. qe_clrsetbits_be32(&uccp->gumr_h, UCC_SLOW_GUMR_H_RFW,
  593. UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX);
  594. } else {
  595. qe_clrsetbits_be32(&uccp->gumr_l,
  596. UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK | UCC_SLOW_GUMR_L_RDCR_MASK,
  597. UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_16 | UCC_SLOW_GUMR_L_RDCR_16);
  598. qe_clrsetbits_be32(&uccp->gumr_h,
  599. UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX,
  600. UCC_SLOW_GUMR_H_RFW);
  601. }
  602. #ifdef LOOPBACK
  603. qe_clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK,
  604. UCC_SLOW_GUMR_L_DIAG_LOOP);
  605. qe_clrsetbits_be32(&uccp->gumr_h,
  606. UCC_SLOW_GUMR_H_CTSP | UCC_SLOW_GUMR_H_RSYN,
  607. UCC_SLOW_GUMR_H_CDS);
  608. #endif
  609. /* Disable rx interrupts and clear all pending events. */
  610. qe_iowrite16be(0, &uccp->uccm);
  611. qe_iowrite16be(0xffff, &uccp->ucce);
  612. qe_iowrite16be(0x7e7e, &uccp->udsr);
  613. /* Initialize UPSMR */
  614. qe_iowrite16be(0, &uccp->upsmr);
  615. if (soft_uart) {
  616. qe_iowrite16be(0x30, &uccup->supsmr);
  617. qe_iowrite16be(0, &uccup->res92);
  618. qe_iowrite32be(0, &uccup->rx_state);
  619. qe_iowrite32be(0, &uccup->rx_cnt);
  620. qe_iowrite8(0, &uccup->rx_bitmark);
  621. qe_iowrite8(10, &uccup->rx_length);
  622. qe_iowrite32be(0x4000, &uccup->dump_ptr);
  623. qe_iowrite8(0, &uccup->rx_temp_dlst_qe);
  624. qe_iowrite32be(0, &uccup->rx_frame_rem);
  625. qe_iowrite8(0, &uccup->rx_frame_rem_size);
  626. /* Soft-UART requires TX to be 1X */
  627. qe_iowrite8(UCC_UART_TX_STATE_UART | UCC_UART_TX_STATE_X1,
  628. &uccup->tx_mode);
  629. qe_iowrite16be(0, &uccup->tx_state);
  630. qe_iowrite8(0, &uccup->resD4);
  631. qe_iowrite16be(0, &uccup->resD5);
  632. /* Set UART mode.
  633. * Enable receive and transmit.
  634. */
  635. /* From the microcode errata:
  636. * 1.GUMR_L register, set mode=0010 (QMC).
  637. * 2.Set GUMR_H[17] bit. (UART/AHDLC mode).
  638. * 3.Set GUMR_H[19:20] (Transparent mode)
  639. * 4.Clear GUMR_H[26] (RFW)
  640. * ...
  641. * 6.Receiver must use 16x over sampling
  642. */
  643. qe_clrsetbits_be32(&uccp->gumr_l,
  644. UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK | UCC_SLOW_GUMR_L_RDCR_MASK,
  645. UCC_SLOW_GUMR_L_MODE_QMC | UCC_SLOW_GUMR_L_TDCR_16 | UCC_SLOW_GUMR_L_RDCR_16);
  646. qe_clrsetbits_be32(&uccp->gumr_h,
  647. UCC_SLOW_GUMR_H_RFW | UCC_SLOW_GUMR_H_RSYN,
  648. UCC_SLOW_GUMR_H_SUART | UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX | UCC_SLOW_GUMR_H_TFL);
  649. #ifdef LOOPBACK
  650. qe_clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK,
  651. UCC_SLOW_GUMR_L_DIAG_LOOP);
  652. qe_clrbits_be32(&uccp->gumr_h,
  653. UCC_SLOW_GUMR_H_CTSP | UCC_SLOW_GUMR_H_CDS);
  654. #endif
  655. cecr_subblock = ucc_slow_get_qe_cr_subblock(qe_port->ucc_num);
  656. qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock,
  657. QE_CR_PROTOCOL_UNSPECIFIED, 0);
  658. } else {
  659. cecr_subblock = ucc_slow_get_qe_cr_subblock(qe_port->ucc_num);
  660. qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock,
  661. QE_CR_PROTOCOL_UART, 0);
  662. }
  663. }
  664. /*
  665. * Initialize the port.
  666. */
  667. static int qe_uart_startup(struct uart_port *port)
  668. {
  669. struct uart_qe_port *qe_port =
  670. container_of(port, struct uart_qe_port, port);
  671. int ret;
  672. /*
  673. * If we're using Soft-UART mode, then we need to make sure the
  674. * firmware has been uploaded first.
  675. */
  676. if (soft_uart && !firmware_loaded) {
  677. dev_err(port->dev, "Soft-UART firmware not uploaded\n");
  678. return -ENODEV;
  679. }
  680. qe_uart_initbd(qe_port);
  681. qe_uart_init_ucc(qe_port);
  682. /* Install interrupt handler. */
  683. ret = request_irq(port->irq, qe_uart_int, IRQF_SHARED, "ucc-uart",
  684. qe_port);
  685. if (ret) {
  686. dev_err(port->dev, "could not claim IRQ %u\n", port->irq);
  687. return ret;
  688. }
  689. /* Startup rx-int */
  690. qe_setbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX);
  691. ucc_slow_enable(qe_port->us_private, COMM_DIR_RX_AND_TX);
  692. return 0;
  693. }
  694. /*
  695. * Shutdown the port.
  696. */
  697. static void qe_uart_shutdown(struct uart_port *port)
  698. {
  699. struct uart_qe_port *qe_port =
  700. container_of(port, struct uart_qe_port, port);
  701. struct ucc_slow __iomem *uccp = qe_port->uccp;
  702. unsigned int timeout = 20;
  703. /* Disable RX and TX */
  704. /* Wait for all the BDs marked sent */
  705. while (!qe_uart_tx_empty(port)) {
  706. if (!--timeout) {
  707. dev_warn(port->dev, "shutdown timeout\n");
  708. break;
  709. }
  710. set_current_state(TASK_UNINTERRUPTIBLE);
  711. schedule_timeout(2);
  712. }
  713. if (qe_port->wait_closing) {
  714. /* Wait a bit longer */
  715. set_current_state(TASK_UNINTERRUPTIBLE);
  716. schedule_timeout(qe_port->wait_closing);
  717. }
  718. /* Stop uarts */
  719. ucc_slow_disable(qe_port->us_private, COMM_DIR_RX_AND_TX);
  720. qe_clrbits_be16(&uccp->uccm, UCC_UART_UCCE_TX | UCC_UART_UCCE_RX);
  721. /* Shut them really down and reinit buffer descriptors */
  722. ucc_slow_graceful_stop_tx(qe_port->us_private);
  723. qe_uart_initbd(qe_port);
  724. free_irq(port->irq, qe_port);
  725. }
  726. /*
  727. * Set the serial port parameters.
  728. */
  729. static void qe_uart_set_termios(struct uart_port *port,
  730. struct ktermios *termios, struct ktermios *old)
  731. {
  732. struct uart_qe_port *qe_port =
  733. container_of(port, struct uart_qe_port, port);
  734. struct ucc_slow __iomem *uccp = qe_port->uccp;
  735. unsigned int baud;
  736. unsigned long flags;
  737. u16 upsmr = qe_ioread16be(&uccp->upsmr);
  738. struct ucc_uart_pram __iomem *uccup = qe_port->uccup;
  739. u16 supsmr = qe_ioread16be(&uccup->supsmr);
  740. u8 char_length = 2; /* 1 + CL + PEN + 1 + SL */
  741. /* Character length programmed into the mode register is the
  742. * sum of: 1 start bit, number of data bits, 0 or 1 parity bit,
  743. * 1 or 2 stop bits, minus 1.
  744. * The value 'bits' counts this for us.
  745. */
  746. /* byte size */
  747. upsmr &= UCC_UART_UPSMR_CL_MASK;
  748. supsmr &= UCC_UART_SUPSMR_CL_MASK;
  749. switch (termios->c_cflag & CSIZE) {
  750. case CS5:
  751. upsmr |= UCC_UART_UPSMR_CL_5;
  752. supsmr |= UCC_UART_SUPSMR_CL_5;
  753. char_length += 5;
  754. break;
  755. case CS6:
  756. upsmr |= UCC_UART_UPSMR_CL_6;
  757. supsmr |= UCC_UART_SUPSMR_CL_6;
  758. char_length += 6;
  759. break;
  760. case CS7:
  761. upsmr |= UCC_UART_UPSMR_CL_7;
  762. supsmr |= UCC_UART_SUPSMR_CL_7;
  763. char_length += 7;
  764. break;
  765. default: /* case CS8 */
  766. upsmr |= UCC_UART_UPSMR_CL_8;
  767. supsmr |= UCC_UART_SUPSMR_CL_8;
  768. char_length += 8;
  769. break;
  770. }
  771. /* If CSTOPB is set, we want two stop bits */
  772. if (termios->c_cflag & CSTOPB) {
  773. upsmr |= UCC_UART_UPSMR_SL;
  774. supsmr |= UCC_UART_SUPSMR_SL;
  775. char_length++; /* + SL */
  776. }
  777. if (termios->c_cflag & PARENB) {
  778. upsmr |= UCC_UART_UPSMR_PEN;
  779. supsmr |= UCC_UART_SUPSMR_PEN;
  780. char_length++; /* + PEN */
  781. if (!(termios->c_cflag & PARODD)) {
  782. upsmr &= ~(UCC_UART_UPSMR_RPM_MASK |
  783. UCC_UART_UPSMR_TPM_MASK);
  784. upsmr |= UCC_UART_UPSMR_RPM_EVEN |
  785. UCC_UART_UPSMR_TPM_EVEN;
  786. supsmr &= ~(UCC_UART_SUPSMR_RPM_MASK |
  787. UCC_UART_SUPSMR_TPM_MASK);
  788. supsmr |= UCC_UART_SUPSMR_RPM_EVEN |
  789. UCC_UART_SUPSMR_TPM_EVEN;
  790. }
  791. }
  792. /*
  793. * Set up parity check flag
  794. */
  795. port->read_status_mask = BD_SC_EMPTY | BD_SC_OV;
  796. if (termios->c_iflag & INPCK)
  797. port->read_status_mask |= BD_SC_FR | BD_SC_PR;
  798. if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
  799. port->read_status_mask |= BD_SC_BR;
  800. /*
  801. * Characters to ignore
  802. */
  803. port->ignore_status_mask = 0;
  804. if (termios->c_iflag & IGNPAR)
  805. port->ignore_status_mask |= BD_SC_PR | BD_SC_FR;
  806. if (termios->c_iflag & IGNBRK) {
  807. port->ignore_status_mask |= BD_SC_BR;
  808. /*
  809. * If we're ignore parity and break indicators, ignore
  810. * overruns too. (For real raw support).
  811. */
  812. if (termios->c_iflag & IGNPAR)
  813. port->ignore_status_mask |= BD_SC_OV;
  814. }
  815. /*
  816. * !!! ignore all characters if CREAD is not set
  817. */
  818. if ((termios->c_cflag & CREAD) == 0)
  819. port->read_status_mask &= ~BD_SC_EMPTY;
  820. baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
  821. /* Do we really need a spinlock here? */
  822. spin_lock_irqsave(&port->lock, flags);
  823. /* Update the per-port timeout. */
  824. uart_update_timeout(port, termios->c_cflag, baud);
  825. qe_iowrite16be(upsmr, &uccp->upsmr);
  826. if (soft_uart) {
  827. qe_iowrite16be(supsmr, &uccup->supsmr);
  828. qe_iowrite8(char_length, &uccup->rx_length);
  829. /* Soft-UART requires a 1X multiplier for TX */
  830. qe_setbrg(qe_port->us_info.rx_clock, baud, 16);
  831. qe_setbrg(qe_port->us_info.tx_clock, baud, 1);
  832. } else {
  833. qe_setbrg(qe_port->us_info.rx_clock, baud, 16);
  834. qe_setbrg(qe_port->us_info.tx_clock, baud, 16);
  835. }
  836. spin_unlock_irqrestore(&port->lock, flags);
  837. }
  838. /*
  839. * Return a pointer to a string that describes what kind of port this is.
  840. */
  841. static const char *qe_uart_type(struct uart_port *port)
  842. {
  843. return "QE";
  844. }
  845. /*
  846. * Allocate any memory and I/O resources required by the port.
  847. */
  848. static int qe_uart_request_port(struct uart_port *port)
  849. {
  850. int ret;
  851. struct uart_qe_port *qe_port =
  852. container_of(port, struct uart_qe_port, port);
  853. struct ucc_slow_info *us_info = &qe_port->us_info;
  854. struct ucc_slow_private *uccs;
  855. unsigned int rx_size, tx_size;
  856. void *bd_virt;
  857. dma_addr_t bd_dma_addr = 0;
  858. ret = ucc_slow_init(us_info, &uccs);
  859. if (ret) {
  860. dev_err(port->dev, "could not initialize UCC%u\n",
  861. qe_port->ucc_num);
  862. return ret;
  863. }
  864. qe_port->us_private = uccs;
  865. qe_port->uccp = uccs->us_regs;
  866. qe_port->uccup = (struct ucc_uart_pram *) uccs->us_pram;
  867. qe_port->rx_bd_base = uccs->rx_bd;
  868. qe_port->tx_bd_base = uccs->tx_bd;
  869. /*
  870. * Allocate the transmit and receive data buffers.
  871. */
  872. rx_size = L1_CACHE_ALIGN(qe_port->rx_nrfifos * qe_port->rx_fifosize);
  873. tx_size = L1_CACHE_ALIGN(qe_port->tx_nrfifos * qe_port->tx_fifosize);
  874. bd_virt = dma_alloc_coherent(port->dev, rx_size + tx_size, &bd_dma_addr,
  875. GFP_KERNEL);
  876. if (!bd_virt) {
  877. dev_err(port->dev, "could not allocate buffer descriptors\n");
  878. return -ENOMEM;
  879. }
  880. qe_port->bd_virt = bd_virt;
  881. qe_port->bd_dma_addr = bd_dma_addr;
  882. qe_port->bd_size = rx_size + tx_size;
  883. qe_port->rx_buf = bd_virt;
  884. qe_port->tx_buf = qe_port->rx_buf + rx_size;
  885. return 0;
  886. }
  887. /*
  888. * Configure the port.
  889. *
  890. * We say we're a CPM-type port because that's mostly true. Once the device
  891. * is configured, this driver operates almost identically to the CPM serial
  892. * driver.
  893. */
  894. static void qe_uart_config_port(struct uart_port *port, int flags)
  895. {
  896. if (flags & UART_CONFIG_TYPE) {
  897. port->type = PORT_CPM;
  898. qe_uart_request_port(port);
  899. }
  900. }
  901. /*
  902. * Release any memory and I/O resources that were allocated in
  903. * qe_uart_request_port().
  904. */
  905. static void qe_uart_release_port(struct uart_port *port)
  906. {
  907. struct uart_qe_port *qe_port =
  908. container_of(port, struct uart_qe_port, port);
  909. struct ucc_slow_private *uccs = qe_port->us_private;
  910. dma_free_coherent(port->dev, qe_port->bd_size, qe_port->bd_virt,
  911. qe_port->bd_dma_addr);
  912. ucc_slow_free(uccs);
  913. }
  914. /*
  915. * Verify that the data in serial_struct is suitable for this device.
  916. */
  917. static int qe_uart_verify_port(struct uart_port *port,
  918. struct serial_struct *ser)
  919. {
  920. if (ser->type != PORT_UNKNOWN && ser->type != PORT_CPM)
  921. return -EINVAL;
  922. if (ser->irq < 0 || ser->irq >= nr_irqs)
  923. return -EINVAL;
  924. if (ser->baud_base < 9600)
  925. return -EINVAL;
  926. return 0;
  927. }
  928. /* UART operations
  929. *
  930. * Details on these functions can be found in Documentation/driver-api/serial/driver.rst
  931. */
  932. static const struct uart_ops qe_uart_pops = {
  933. .tx_empty = qe_uart_tx_empty,
  934. .set_mctrl = qe_uart_set_mctrl,
  935. .get_mctrl = qe_uart_get_mctrl,
  936. .stop_tx = qe_uart_stop_tx,
  937. .start_tx = qe_uart_start_tx,
  938. .stop_rx = qe_uart_stop_rx,
  939. .break_ctl = qe_uart_break_ctl,
  940. .startup = qe_uart_startup,
  941. .shutdown = qe_uart_shutdown,
  942. .set_termios = qe_uart_set_termios,
  943. .type = qe_uart_type,
  944. .release_port = qe_uart_release_port,
  945. .request_port = qe_uart_request_port,
  946. .config_port = qe_uart_config_port,
  947. .verify_port = qe_uart_verify_port,
  948. };
  949. #ifdef CONFIG_PPC32
  950. /*
  951. * Obtain the SOC model number and revision level
  952. *
  953. * This function parses the device tree to obtain the SOC model. It then
  954. * reads the SVR register to the revision.
  955. *
  956. * The device tree stores the SOC model two different ways.
  957. *
  958. * The new way is:
  959. *
  960. * cpu@0 {
  961. * compatible = "PowerPC,8323";
  962. * device_type = "cpu";
  963. * ...
  964. *
  965. *
  966. * The old way is:
  967. * PowerPC,8323@0 {
  968. * device_type = "cpu";
  969. * ...
  970. *
  971. * This code first checks the new way, and then the old way.
  972. */
  973. static unsigned int soc_info(unsigned int *rev_h, unsigned int *rev_l)
  974. {
  975. struct device_node *np;
  976. const char *soc_string;
  977. unsigned int svr;
  978. unsigned int soc;
  979. /* Find the CPU node */
  980. np = of_find_node_by_type(NULL, "cpu");
  981. if (!np)
  982. return 0;
  983. /* Find the compatible property */
  984. soc_string = of_get_property(np, "compatible", NULL);
  985. if (!soc_string)
  986. /* No compatible property, so try the name. */
  987. soc_string = np->name;
  988. /* Extract the SOC number from the "PowerPC," string */
  989. if ((sscanf(soc_string, "PowerPC,%u", &soc) != 1) || !soc)
  990. return 0;
  991. /* Get the revision from the SVR */
  992. svr = mfspr(SPRN_SVR);
  993. *rev_h = (svr >> 4) & 0xf;
  994. *rev_l = svr & 0xf;
  995. return soc;
  996. }
  997. /*
  998. * requst_firmware_nowait() callback function
  999. *
  1000. * This function is called by the kernel when a firmware is made available,
  1001. * or if it times out waiting for the firmware.
  1002. */
  1003. static void uart_firmware_cont(const struct firmware *fw, void *context)
  1004. {
  1005. struct qe_firmware *firmware;
  1006. struct device *dev = context;
  1007. int ret;
  1008. if (!fw) {
  1009. dev_err(dev, "firmware not found\n");
  1010. return;
  1011. }
  1012. firmware = (struct qe_firmware *) fw->data;
  1013. if (firmware->header.length != fw->size) {
  1014. dev_err(dev, "invalid firmware\n");
  1015. goto out;
  1016. }
  1017. ret = qe_upload_firmware(firmware);
  1018. if (ret) {
  1019. dev_err(dev, "could not load firmware\n");
  1020. goto out;
  1021. }
  1022. firmware_loaded = 1;
  1023. out:
  1024. release_firmware(fw);
  1025. }
  1026. static int soft_uart_init(struct platform_device *ofdev)
  1027. {
  1028. struct device_node *np = ofdev->dev.of_node;
  1029. struct qe_firmware_info *qe_fw_info;
  1030. int ret;
  1031. if (of_find_property(np, "soft-uart", NULL)) {
  1032. dev_dbg(&ofdev->dev, "using Soft-UART mode\n");
  1033. soft_uart = 1;
  1034. } else {
  1035. return 0;
  1036. }
  1037. qe_fw_info = qe_get_firmware_info();
  1038. /* Check if the firmware has been uploaded. */
  1039. if (qe_fw_info && strstr(qe_fw_info->id, "Soft-UART")) {
  1040. firmware_loaded = 1;
  1041. } else {
  1042. char filename[32];
  1043. unsigned int soc;
  1044. unsigned int rev_h;
  1045. unsigned int rev_l;
  1046. soc = soc_info(&rev_h, &rev_l);
  1047. if (!soc) {
  1048. dev_err(&ofdev->dev, "unknown CPU model\n");
  1049. return -ENXIO;
  1050. }
  1051. sprintf(filename, "fsl_qe_ucode_uart_%u_%u%u.bin",
  1052. soc, rev_h, rev_l);
  1053. dev_info(&ofdev->dev, "waiting for firmware %s\n",
  1054. filename);
  1055. /*
  1056. * We call request_firmware_nowait instead of
  1057. * request_firmware so that the driver can load and
  1058. * initialize the ports without holding up the rest of
  1059. * the kernel. If hotplug support is enabled in the
  1060. * kernel, then we use it.
  1061. */
  1062. ret = request_firmware_nowait(THIS_MODULE,
  1063. FW_ACTION_HOTPLUG, filename, &ofdev->dev,
  1064. GFP_KERNEL, &ofdev->dev, uart_firmware_cont);
  1065. if (ret) {
  1066. dev_err(&ofdev->dev,
  1067. "could not load firmware %s\n",
  1068. filename);
  1069. return ret;
  1070. }
  1071. }
  1072. return 0;
  1073. }
  1074. #else /* !CONFIG_PPC32 */
  1075. static int soft_uart_init(struct platform_device *ofdev)
  1076. {
  1077. return 0;
  1078. }
  1079. #endif
  1080. static int ucc_uart_probe(struct platform_device *ofdev)
  1081. {
  1082. struct device_node *np = ofdev->dev.of_node;
  1083. const char *sprop; /* String OF properties */
  1084. struct uart_qe_port *qe_port = NULL;
  1085. struct resource res;
  1086. u32 val;
  1087. int ret;
  1088. /*
  1089. * Determine if we need Soft-UART mode
  1090. */
  1091. ret = soft_uart_init(ofdev);
  1092. if (ret)
  1093. return ret;
  1094. qe_port = kzalloc(sizeof(struct uart_qe_port), GFP_KERNEL);
  1095. if (!qe_port) {
  1096. dev_err(&ofdev->dev, "can't allocate QE port structure\n");
  1097. return -ENOMEM;
  1098. }
  1099. /* Search for IRQ and mapbase */
  1100. ret = of_address_to_resource(np, 0, &res);
  1101. if (ret) {
  1102. dev_err(&ofdev->dev, "missing 'reg' property in device tree\n");
  1103. goto out_free;
  1104. }
  1105. if (!res.start) {
  1106. dev_err(&ofdev->dev, "invalid 'reg' property in device tree\n");
  1107. ret = -EINVAL;
  1108. goto out_free;
  1109. }
  1110. qe_port->port.mapbase = res.start;
  1111. /* Get the UCC number (device ID) */
  1112. /* UCCs are numbered 1-7 */
  1113. if (of_property_read_u32(np, "cell-index", &val)) {
  1114. if (of_property_read_u32(np, "device-id", &val)) {
  1115. dev_err(&ofdev->dev, "UCC is unspecified in device tree\n");
  1116. ret = -EINVAL;
  1117. goto out_free;
  1118. }
  1119. }
  1120. if (val < 1 || val > UCC_MAX_NUM) {
  1121. dev_err(&ofdev->dev, "no support for UCC%u\n", val);
  1122. ret = -ENODEV;
  1123. goto out_free;
  1124. }
  1125. qe_port->ucc_num = val - 1;
  1126. /*
  1127. * In the future, we should not require the BRG to be specified in the
  1128. * device tree. If no clock-source is specified, then just pick a BRG
  1129. * to use. This requires a new QE library function that manages BRG
  1130. * assignments.
  1131. */
  1132. sprop = of_get_property(np, "rx-clock-name", NULL);
  1133. if (!sprop) {
  1134. dev_err(&ofdev->dev, "missing rx-clock-name in device tree\n");
  1135. ret = -ENODEV;
  1136. goto out_free;
  1137. }
  1138. qe_port->us_info.rx_clock = qe_clock_source(sprop);
  1139. if ((qe_port->us_info.rx_clock < QE_BRG1) ||
  1140. (qe_port->us_info.rx_clock > QE_BRG16)) {
  1141. dev_err(&ofdev->dev, "rx-clock-name must be a BRG for UART\n");
  1142. ret = -ENODEV;
  1143. goto out_free;
  1144. }
  1145. #ifdef LOOPBACK
  1146. /* In internal loopback mode, TX and RX must use the same clock */
  1147. qe_port->us_info.tx_clock = qe_port->us_info.rx_clock;
  1148. #else
  1149. sprop = of_get_property(np, "tx-clock-name", NULL);
  1150. if (!sprop) {
  1151. dev_err(&ofdev->dev, "missing tx-clock-name in device tree\n");
  1152. ret = -ENODEV;
  1153. goto out_free;
  1154. }
  1155. qe_port->us_info.tx_clock = qe_clock_source(sprop);
  1156. #endif
  1157. if ((qe_port->us_info.tx_clock < QE_BRG1) ||
  1158. (qe_port->us_info.tx_clock > QE_BRG16)) {
  1159. dev_err(&ofdev->dev, "tx-clock-name must be a BRG for UART\n");
  1160. ret = -ENODEV;
  1161. goto out_free;
  1162. }
  1163. /* Get the port number, numbered 0-3 */
  1164. if (of_property_read_u32(np, "port-number", &val)) {
  1165. dev_err(&ofdev->dev, "missing port-number in device tree\n");
  1166. ret = -EINVAL;
  1167. goto out_free;
  1168. }
  1169. qe_port->port.line = val;
  1170. if (qe_port->port.line >= UCC_MAX_UART) {
  1171. dev_err(&ofdev->dev, "port-number must be 0-%u\n",
  1172. UCC_MAX_UART - 1);
  1173. ret = -EINVAL;
  1174. goto out_free;
  1175. }
  1176. qe_port->port.irq = irq_of_parse_and_map(np, 0);
  1177. if (qe_port->port.irq == 0) {
  1178. dev_err(&ofdev->dev, "could not map IRQ for UCC%u\n",
  1179. qe_port->ucc_num + 1);
  1180. ret = -EINVAL;
  1181. goto out_free;
  1182. }
  1183. /*
  1184. * Newer device trees have an "fsl,qe" compatible property for the QE
  1185. * node, but we still need to support older device trees.
  1186. */
  1187. np = of_find_compatible_node(NULL, NULL, "fsl,qe");
  1188. if (!np) {
  1189. np = of_find_node_by_type(NULL, "qe");
  1190. if (!np) {
  1191. dev_err(&ofdev->dev, "could not find 'qe' node\n");
  1192. ret = -EINVAL;
  1193. goto out_free;
  1194. }
  1195. }
  1196. if (of_property_read_u32(np, "brg-frequency", &val)) {
  1197. dev_err(&ofdev->dev,
  1198. "missing brg-frequency in device tree\n");
  1199. ret = -EINVAL;
  1200. goto out_np;
  1201. }
  1202. if (val)
  1203. qe_port->port.uartclk = val;
  1204. else {
  1205. if (!IS_ENABLED(CONFIG_PPC32)) {
  1206. dev_err(&ofdev->dev,
  1207. "invalid brg-frequency in device tree\n");
  1208. ret = -EINVAL;
  1209. goto out_np;
  1210. }
  1211. /*
  1212. * Older versions of U-Boot do not initialize the brg-frequency
  1213. * property, so in this case we assume the BRG frequency is
  1214. * half the QE bus frequency.
  1215. */
  1216. if (of_property_read_u32(np, "bus-frequency", &val)) {
  1217. dev_err(&ofdev->dev,
  1218. "missing QE bus-frequency in device tree\n");
  1219. ret = -EINVAL;
  1220. goto out_np;
  1221. }
  1222. if (val)
  1223. qe_port->port.uartclk = val / 2;
  1224. else {
  1225. dev_err(&ofdev->dev,
  1226. "invalid QE bus-frequency in device tree\n");
  1227. ret = -EINVAL;
  1228. goto out_np;
  1229. }
  1230. }
  1231. spin_lock_init(&qe_port->port.lock);
  1232. qe_port->np = np;
  1233. qe_port->port.dev = &ofdev->dev;
  1234. qe_port->port.ops = &qe_uart_pops;
  1235. qe_port->port.iotype = UPIO_MEM;
  1236. qe_port->tx_nrfifos = TX_NUM_FIFO;
  1237. qe_port->tx_fifosize = TX_BUF_SIZE;
  1238. qe_port->rx_nrfifos = RX_NUM_FIFO;
  1239. qe_port->rx_fifosize = RX_BUF_SIZE;
  1240. qe_port->wait_closing = UCC_WAIT_CLOSING;
  1241. qe_port->port.fifosize = 512;
  1242. qe_port->port.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP;
  1243. qe_port->us_info.ucc_num = qe_port->ucc_num;
  1244. qe_port->us_info.regs = (phys_addr_t) res.start;
  1245. qe_port->us_info.irq = qe_port->port.irq;
  1246. qe_port->us_info.rx_bd_ring_len = qe_port->rx_nrfifos;
  1247. qe_port->us_info.tx_bd_ring_len = qe_port->tx_nrfifos;
  1248. /* Make sure ucc_slow_init() initializes both TX and RX */
  1249. qe_port->us_info.init_tx = 1;
  1250. qe_port->us_info.init_rx = 1;
  1251. /* Add the port to the uart sub-system. This will cause
  1252. * qe_uart_config_port() to be called, so the us_info structure must
  1253. * be initialized.
  1254. */
  1255. ret = uart_add_one_port(&ucc_uart_driver, &qe_port->port);
  1256. if (ret) {
  1257. dev_err(&ofdev->dev, "could not add /dev/ttyQE%u\n",
  1258. qe_port->port.line);
  1259. goto out_np;
  1260. }
  1261. platform_set_drvdata(ofdev, qe_port);
  1262. dev_info(&ofdev->dev, "UCC%u assigned to /dev/ttyQE%u\n",
  1263. qe_port->ucc_num + 1, qe_port->port.line);
  1264. /* Display the mknod command for this device */
  1265. dev_dbg(&ofdev->dev, "mknod command is 'mknod /dev/ttyQE%u c %u %u'\n",
  1266. qe_port->port.line, SERIAL_QE_MAJOR,
  1267. SERIAL_QE_MINOR + qe_port->port.line);
  1268. return 0;
  1269. out_np:
  1270. of_node_put(np);
  1271. out_free:
  1272. kfree(qe_port);
  1273. return ret;
  1274. }
  1275. static int ucc_uart_remove(struct platform_device *ofdev)
  1276. {
  1277. struct uart_qe_port *qe_port = platform_get_drvdata(ofdev);
  1278. dev_info(&ofdev->dev, "removing /dev/ttyQE%u\n", qe_port->port.line);
  1279. uart_remove_one_port(&ucc_uart_driver, &qe_port->port);
  1280. kfree(qe_port);
  1281. return 0;
  1282. }
  1283. static const struct of_device_id ucc_uart_match[] = {
  1284. {
  1285. .type = "serial",
  1286. .compatible = "ucc_uart",
  1287. },
  1288. {
  1289. .compatible = "fsl,t1040-ucc-uart",
  1290. },
  1291. {},
  1292. };
  1293. MODULE_DEVICE_TABLE(of, ucc_uart_match);
  1294. static struct platform_driver ucc_uart_of_driver = {
  1295. .driver = {
  1296. .name = "ucc_uart",
  1297. .of_match_table = ucc_uart_match,
  1298. },
  1299. .probe = ucc_uart_probe,
  1300. .remove = ucc_uart_remove,
  1301. };
  1302. static int __init ucc_uart_init(void)
  1303. {
  1304. int ret;
  1305. printk(KERN_INFO "Freescale QUICC Engine UART device driver\n");
  1306. #ifdef LOOPBACK
  1307. printk(KERN_INFO "ucc-uart: Using loopback mode\n");
  1308. #endif
  1309. ret = uart_register_driver(&ucc_uart_driver);
  1310. if (ret) {
  1311. printk(KERN_ERR "ucc-uart: could not register UART driver\n");
  1312. return ret;
  1313. }
  1314. ret = platform_driver_register(&ucc_uart_of_driver);
  1315. if (ret) {
  1316. printk(KERN_ERR
  1317. "ucc-uart: could not register platform driver\n");
  1318. uart_unregister_driver(&ucc_uart_driver);
  1319. }
  1320. return ret;
  1321. }
  1322. static void __exit ucc_uart_exit(void)
  1323. {
  1324. printk(KERN_INFO
  1325. "Freescale QUICC Engine UART device driver unloading\n");
  1326. platform_driver_unregister(&ucc_uart_of_driver);
  1327. uart_unregister_driver(&ucc_uart_driver);
  1328. }
  1329. module_init(ucc_uart_init);
  1330. module_exit(ucc_uart_exit);
  1331. MODULE_DESCRIPTION("Freescale QUICC Engine (QE) UART");
  1332. MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
  1333. MODULE_LICENSE("GPL v2");
  1334. MODULE_ALIAS_CHARDEV_MAJOR(SERIAL_QE_MAJOR);