/drivers/tty/serial/ucc_uart.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Freescale QUICC Engine UART device driver
   4 *
   5 * Author: Timur Tabi <timur@freescale.com>
   6 *
   7 * Copyright 2007 Freescale Semiconductor, Inc.
   8 *
   9 * This driver adds support for UART devices via Freescale's QUICC Engine
  10 * found on some Freescale SOCs.
  11 *
  12 * If Soft-UART support is needed but not already present, then this driver
  13 * will request and upload the "Soft-UART" microcode upon probe.  The
  14 * filename of the microcode should be fsl_qe_ucode_uart_X_YZ.bin, where "X"
  15 * is the name of the SOC (e.g. 8323), and YZ is the revision of the SOC,
  16 * (e.g. "11" for 1.1).
  17 */
  18
  19#include <linux/module.h>
  20#include <linux/serial.h>
  21#include <linux/serial_core.h>
  22#include <linux/slab.h>
  23#include <linux/tty.h>
  24#include <linux/tty_flip.h>
  25#include <linux/io.h>
  26#include <linux/of_address.h>
  27#include <linux/of_irq.h>
  28#include <linux/of_platform.h>
  29#include <linux/dma-mapping.h>
  30
  31#include <linux/fs_uart_pd.h>
  32#include <soc/fsl/qe/ucc_slow.h>
  33
  34#include <linux/firmware.h>
  35#include <soc/fsl/cpm.h>
  36
  37#ifdef CONFIG_PPC32
  38#include <asm/reg.h> /* mfspr, SPRN_SVR */
  39#endif
  40
  41/*
  42 * The GUMR flag for Soft UART.  This would normally be defined in qe.h,
  43 * but Soft-UART is a hack and we want to keep everything related to it in
  44 * this file.
  45 */
  46#define UCC_SLOW_GUMR_H_SUART   	0x00004000      /* Soft-UART */
  47
  48/*
  49 * soft_uart is 1 if we need to use Soft-UART mode
  50 */
  51static int soft_uart;
  52/*
  53 * firmware_loaded is 1 if the firmware has been loaded, 0 otherwise.
  54 */
  55static int firmware_loaded;
  56
  57/* Enable this macro to configure all serial ports in internal loopback
  58   mode */
  59/* #define LOOPBACK */
  60
  61/* The major and minor device numbers are defined in
  62 * http://www.lanana.org/docs/device-list/devices-2.6+.txt.  For the QE
  63 * UART, we have major number 204 and minor numbers 46 - 49, which are the
  64 * same as for the CPM2.  This decision was made because no Freescale part
  65 * has both a CPM and a QE.
  66 */
  67#define SERIAL_QE_MAJOR 204
  68#define SERIAL_QE_MINOR 46
  69
  70/* Since we only have minor numbers 46 - 49, there is a hard limit of 4 ports */
  71#define UCC_MAX_UART    4
  72
  73/* The number of buffer descriptors for receiving characters. */
  74#define RX_NUM_FIFO     4
  75
  76/* The number of buffer descriptors for transmitting characters. */
  77#define TX_NUM_FIFO     4
  78
  79/* The maximum size of the character buffer for a single RX BD. */
  80#define RX_BUF_SIZE     32
  81
  82/* The maximum size of the character buffer for a single TX BD. */
  83#define TX_BUF_SIZE     32
  84
  85/*
  86 * The number of jiffies to wait after receiving a close command before the
  87 * device is actually closed.  This allows the last few characters to be
  88 * sent over the wire.
  89 */
  90#define UCC_WAIT_CLOSING 100
  91
  92struct ucc_uart_pram {
  93	struct ucc_slow_pram common;
  94	u8 res1[8];     	/* reserved */
  95	__be16 maxidl;  	/* Maximum idle chars */
  96	__be16 idlc;    	/* temp idle counter */
  97	__be16 brkcr;   	/* Break count register */
  98	__be16 parec;   	/* receive parity error counter */
  99	__be16 frmec;   	/* receive framing error counter */
 100	__be16 nosec;   	/* receive noise counter */
 101	__be16 brkec;   	/* receive break condition counter */
 102	__be16 brkln;   	/* last received break length */
 103	__be16 uaddr[2];	/* UART address character 1 & 2 */
 104	__be16 rtemp;   	/* Temp storage */
 105	__be16 toseq;   	/* Transmit out of sequence char */
 106	__be16 cchars[8];       /* control characters 1-8 */
 107	__be16 rccm;    	/* receive control character mask */
 108	__be16 rccr;    	/* receive control character register */
 109	__be16 rlbc;    	/* receive last break character */
 110	__be16 res2;    	/* reserved */
 111	__be32 res3;    	/* reserved, should be cleared */
 112	u8 res4;		/* reserved, should be cleared */
 113	u8 res5[3];     	/* reserved, should be cleared */
 114	__be32 res6;    	/* reserved, should be cleared */
 115	__be32 res7;    	/* reserved, should be cleared */
 116	__be32 res8;    	/* reserved, should be cleared */
 117	__be32 res9;    	/* reserved, should be cleared */
 118	__be32 res10;   	/* reserved, should be cleared */
 119	__be32 res11;   	/* reserved, should be cleared */
 120	__be32 res12;   	/* reserved, should be cleared */
 121	__be32 res13;   	/* reserved, should be cleared */
 122/* The rest is for Soft-UART only */
 123	__be16 supsmr;  	/* 0x90, Shadow UPSMR */
 124	__be16 res92;   	/* 0x92, reserved, initialize to 0 */
 125	__be32 rx_state;	/* 0x94, RX state, initialize to 0 */
 126	__be32 rx_cnt;  	/* 0x98, RX count, initialize to 0 */
 127	u8 rx_length;   	/* 0x9C, Char length, set to 1+CL+PEN+1+SL */
 128	u8 rx_bitmark;  	/* 0x9D, reserved, initialize to 0 */
 129	u8 rx_temp_dlst_qe;     /* 0x9E, reserved, initialize to 0 */
 130	u8 res14[0xBC - 0x9F];  /* reserved */
 131	__be32 dump_ptr;	/* 0xBC, Dump pointer */
 132	__be32 rx_frame_rem;    /* 0xC0, reserved, initialize to 0 */
 133	u8 rx_frame_rem_size;   /* 0xC4, reserved, initialize to 0 */
 134	u8 tx_mode;     	/* 0xC5, mode, 0=AHDLC, 1=UART */
 135	__be16 tx_state;	/* 0xC6, TX state */
 136	u8 res15[0xD0 - 0xC8];  /* reserved */
 137	__be32 resD0;   	/* 0xD0, reserved, initialize to 0 */
 138	u8 resD4;       	/* 0xD4, reserved, initialize to 0 */
 139	__be16 resD5;   	/* 0xD5, reserved, initialize to 0 */
 140} __attribute__ ((packed));
 141
 142/* SUPSMR definitions, for Soft-UART only */
 143#define UCC_UART_SUPSMR_SL      	0x8000
 144#define UCC_UART_SUPSMR_RPM_MASK	0x6000
 145#define UCC_UART_SUPSMR_RPM_ODD 	0x0000
 146#define UCC_UART_SUPSMR_RPM_LOW 	0x2000
 147#define UCC_UART_SUPSMR_RPM_EVEN	0x4000
 148#define UCC_UART_SUPSMR_RPM_HIGH	0x6000
 149#define UCC_UART_SUPSMR_PEN     	0x1000
 150#define UCC_UART_SUPSMR_TPM_MASK	0x0C00
 151#define UCC_UART_SUPSMR_TPM_ODD 	0x0000
 152#define UCC_UART_SUPSMR_TPM_LOW 	0x0400
 153#define UCC_UART_SUPSMR_TPM_EVEN	0x0800
 154#define UCC_UART_SUPSMR_TPM_HIGH	0x0C00
 155#define UCC_UART_SUPSMR_FRZ     	0x0100
 156#define UCC_UART_SUPSMR_UM_MASK 	0x00c0
 157#define UCC_UART_SUPSMR_UM_NORMAL       0x0000
 158#define UCC_UART_SUPSMR_UM_MAN_MULTI    0x0040
 159#define UCC_UART_SUPSMR_UM_AUTO_MULTI   0x00c0
 160#define UCC_UART_SUPSMR_CL_MASK 	0x0030
 161#define UCC_UART_SUPSMR_CL_8    	0x0030
 162#define UCC_UART_SUPSMR_CL_7    	0x0020
 163#define UCC_UART_SUPSMR_CL_6    	0x0010
 164#define UCC_UART_SUPSMR_CL_5    	0x0000
 165
 166#define UCC_UART_TX_STATE_AHDLC 	0x00
 167#define UCC_UART_TX_STATE_UART  	0x01
 168#define UCC_UART_TX_STATE_X1    	0x00
 169#define UCC_UART_TX_STATE_X16   	0x80
 170
 171#define UCC_UART_PRAM_ALIGNMENT 0x100
 172
 173#define UCC_UART_SIZE_OF_BD     UCC_SLOW_SIZE_OF_BD
 174#define NUM_CONTROL_CHARS       8
 175
 176/* Private per-port data structure */
 177struct uart_qe_port {
 178	struct uart_port port;
 179	struct ucc_slow __iomem *uccp;
 180	struct ucc_uart_pram __iomem *uccup;
 181	struct ucc_slow_info us_info;
 182	struct ucc_slow_private *us_private;
 183	struct device_node *np;
 184	unsigned int ucc_num;   /* First ucc is 0, not 1 */
 185
 186	u16 rx_nrfifos;
 187	u16 rx_fifosize;
 188	u16 tx_nrfifos;
 189	u16 tx_fifosize;
 190	int wait_closing;
 191	u32 flags;
 192	struct qe_bd *rx_bd_base;
 193	struct qe_bd *rx_cur;
 194	struct qe_bd *tx_bd_base;
 195	struct qe_bd *tx_cur;
 196	unsigned char *tx_buf;
 197	unsigned char *rx_buf;
 198	void *bd_virt;  	/* virtual address of the BD buffers */
 199	dma_addr_t bd_dma_addr; /* bus address of the BD buffers */
 200	unsigned int bd_size;   /* size of BD buffer space */
 201};
 202
 203static struct uart_driver ucc_uart_driver = {
 204	.owner  	= THIS_MODULE,
 205	.driver_name    = "ucc_uart",
 206	.dev_name       = "ttyQE",
 207	.major  	= SERIAL_QE_MAJOR,
 208	.minor  	= SERIAL_QE_MINOR,
 209	.nr     	= UCC_MAX_UART,
 210};
 211
 212/*
 213 * Virtual to physical address translation.
 214 *
 215 * Given the virtual address for a character buffer, this function returns
 216 * the physical (DMA) equivalent.
 217 */
 218static inline dma_addr_t cpu2qe_addr(void *addr, struct uart_qe_port *qe_port)
 219{
 220	if (likely((addr >= qe_port->bd_virt)) &&
 221	    (addr < (qe_port->bd_virt + qe_port->bd_size)))
 222		return qe_port->bd_dma_addr + (addr - qe_port->bd_virt);
 223
 224	/* something nasty happened */
 225	printk(KERN_ERR "%s: addr=%p\n", __func__, addr);
 226	BUG();
 227	return 0;
 228}
 229
 230/*
 231 * Physical to virtual address translation.
 232 *
 233 * Given the physical (DMA) address for a character buffer, this function
 234 * returns the virtual equivalent.
 235 */
 236static inline void *qe2cpu_addr(dma_addr_t addr, struct uart_qe_port *qe_port)
 237{
 238	/* sanity check */
 239	if (likely((addr >= qe_port->bd_dma_addr) &&
 240		   (addr < (qe_port->bd_dma_addr + qe_port->bd_size))))
 241		return qe_port->bd_virt + (addr - qe_port->bd_dma_addr);
 242
 243	/* something nasty happened */
 244	printk(KERN_ERR "%s: addr=%llx\n", __func__, (u64)addr);
 245	BUG();
 246	return NULL;
 247}
 248
 249/*
 250 * Return 1 if the QE is done transmitting all buffers for this port
 251 *
 252 * This function scans each BD in sequence.  If we find a BD that is not
 253 * ready (READY=1), then we return 0 indicating that the QE is still sending
 254 * data.  If we reach the last BD (WRAP=1), then we know we've scanned
 255 * the entire list, and all BDs are done.
 256 */
 257static unsigned int qe_uart_tx_empty(struct uart_port *port)
 258{
 259	struct uart_qe_port *qe_port =
 260		container_of(port, struct uart_qe_port, port);
 261	struct qe_bd *bdp = qe_port->tx_bd_base;
 262
 263	while (1) {
 264		if (qe_ioread16be(&bdp->status) & BD_SC_READY)
 265			/* This BD is not done, so return "not done" */
 266			return 0;
 267
 268		if (qe_ioread16be(&bdp->status) & BD_SC_WRAP)
 269			/*
 270			 * This BD is done and it's the last one, so return
 271			 * "done"
 272			 */
 273			return 1;
 274
 275		bdp++;
 276	}
 277}
 278
 279/*
 280 * Set the modem control lines
 281 *
 282 * Although the QE can control the modem control lines (e.g. CTS), we
 283 * don't need that support. This function must exist, however, otherwise
 284 * the kernel will panic.
 285 */
 286void qe_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
 287{
 288}
 289
 290/*
 291 * Get the current modem control line status
 292 *
 293 * Although the QE can control the modem control lines (e.g. CTS), this
 294 * driver currently doesn't support that, so we always return Carrier
 295 * Detect, Data Set Ready, and Clear To Send.
 296 */
 297static unsigned int qe_uart_get_mctrl(struct uart_port *port)
 298{
 299	return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
 300}
 301
 302/*
 303 * Disable the transmit interrupt.
 304 *
 305 * Although this function is called "stop_tx", it does not actually stop
 306 * transmission of data.  Instead, it tells the QE to not generate an
 307 * interrupt when the UCC is finished sending characters.
 308 */
 309static void qe_uart_stop_tx(struct uart_port *port)
 310{
 311	struct uart_qe_port *qe_port =
 312		container_of(port, struct uart_qe_port, port);
 313
 314	qe_clrbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX);
 315}
 316
 317/*
 318 * Transmit as many characters to the HW as possible.
 319 *
 320 * This function will attempt to stuff of all the characters from the
 321 * kernel's transmit buffer into TX BDs.
 322 *
 323 * A return value of non-zero indicates that it successfully stuffed all
 324 * characters from the kernel buffer.
 325 *
 326 * A return value of zero indicates that there are still characters in the
 327 * kernel's buffer that have not been transmitted, but there are no more BDs
 328 * available.  This function should be called again after a BD has been made
 329 * available.
 330 */
 331static int qe_uart_tx_pump(struct uart_qe_port *qe_port)
 332{
 333	struct qe_bd *bdp;
 334	unsigned char *p;
 335	unsigned int count;
 336	struct uart_port *port = &qe_port->port;
 337	struct circ_buf *xmit = &port->state->xmit;
 338
 339	/* Handle xon/xoff */
 340	if (port->x_char) {
 341		/* Pick next descriptor and fill from buffer */
 342		bdp = qe_port->tx_cur;
 343
 344		p = qe2cpu_addr(be32_to_cpu(bdp->buf), qe_port);
 345
 346		*p++ = port->x_char;
 347		qe_iowrite16be(1, &bdp->length);
 348		qe_setbits_be16(&bdp->status, BD_SC_READY);
 349		/* Get next BD. */
 350		if (qe_ioread16be(&bdp->status) & BD_SC_WRAP)
 351			bdp = qe_port->tx_bd_base;
 352		else
 353			bdp++;
 354		qe_port->tx_cur = bdp;
 355
 356		port->icount.tx++;
 357		port->x_char = 0;
 358		return 1;
 359	}
 360
 361	if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
 362		qe_uart_stop_tx(port);
 363		return 0;
 364	}
 365
 366	/* Pick next descriptor and fill from buffer */
 367	bdp = qe_port->tx_cur;
 368
 369	while (!(qe_ioread16be(&bdp->status) & BD_SC_READY) &&
 370	       (xmit->tail != xmit->head)) {
 371		count = 0;
 372		p = qe2cpu_addr(be32_to_cpu(bdp->buf), qe_port);
 373		while (count < qe_port->tx_fifosize) {
 374			*p++ = xmit->buf[xmit->tail];
 375			xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 376			port->icount.tx++;
 377			count++;
 378			if (xmit->head == xmit->tail)
 379				break;
 380		}
 381
 382		qe_iowrite16be(count, &bdp->length);
 383		qe_setbits_be16(&bdp->status, BD_SC_READY);
 384
 385		/* Get next BD. */
 386		if (qe_ioread16be(&bdp->status) & BD_SC_WRAP)
 387			bdp = qe_port->tx_bd_base;
 388		else
 389			bdp++;
 390	}
 391	qe_port->tx_cur = bdp;
 392
 393	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 394		uart_write_wakeup(port);
 395
 396	if (uart_circ_empty(xmit)) {
 397		/* The kernel buffer is empty, so turn off TX interrupts.  We
 398		   don't need to be told when the QE is finished transmitting
 399		   the data. */
 400		qe_uart_stop_tx(port);
 401		return 0;
 402	}
 403
 404	return 1;
 405}
 406
 407/*
 408 * Start transmitting data
 409 *
 410 * This function will start transmitting any available data, if the port
 411 * isn't already transmitting data.
 412 */
 413static void qe_uart_start_tx(struct uart_port *port)
 414{
 415	struct uart_qe_port *qe_port =
 416		container_of(port, struct uart_qe_port, port);
 417
 418	/* If we currently are transmitting, then just return */
 419	if (qe_ioread16be(&qe_port->uccp->uccm) & UCC_UART_UCCE_TX)
 420		return;
 421
 422	/* Otherwise, pump the port and start transmission */
 423	if (qe_uart_tx_pump(qe_port))
 424		qe_setbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX);
 425}
 426
 427/*
 428 * Stop transmitting data
 429 */
 430static void qe_uart_stop_rx(struct uart_port *port)
 431{
 432	struct uart_qe_port *qe_port =
 433		container_of(port, struct uart_qe_port, port);
 434
 435	qe_clrbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX);
 436}
 437
 438/* Start or stop sending  break signal
 439 *
 440 * This function controls the sending of a break signal.  If break_state=1,
 441 * then we start sending a break signal.  If break_state=0, then we stop
 442 * sending the break signal.
 443 */
 444static void qe_uart_break_ctl(struct uart_port *port, int break_state)
 445{
 446	struct uart_qe_port *qe_port =
 447		container_of(port, struct uart_qe_port, port);
 448
 449	if (break_state)
 450		ucc_slow_stop_tx(qe_port->us_private);
 451	else
 452		ucc_slow_restart_tx(qe_port->us_private);
 453}
 454
 455/* ISR helper function for receiving character.
 456 *
 457 * This function is called by the ISR to handling receiving characters
 458 */
 459static void qe_uart_int_rx(struct uart_qe_port *qe_port)
 460{
 461	int i;
 462	unsigned char ch, *cp;
 463	struct uart_port *port = &qe_port->port;
 464	struct tty_port *tport = &port->state->port;
 465	struct qe_bd *bdp;
 466	u16 status;
 467	unsigned int flg;
 468
 469	/* Just loop through the closed BDs and copy the characters into
 470	 * the buffer.
 471	 */
 472	bdp = qe_port->rx_cur;
 473	while (1) {
 474		status = qe_ioread16be(&bdp->status);
 475
 476		/* If this one is empty, then we assume we've read them all */
 477		if (status & BD_SC_EMPTY)
 478			break;
 479
 480		/* get number of characters, and check space in RX buffer */
 481		i = qe_ioread16be(&bdp->length);
 482
 483		/* If we don't have enough room in RX buffer for the entire BD,
 484		 * then we try later, which will be the next RX interrupt.
 485		 */
 486		if (tty_buffer_request_room(tport, i) < i) {
 487			dev_dbg(port->dev, "ucc-uart: no room in RX buffer\n");
 488			return;
 489		}
 490
 491		/* get pointer */
 492		cp = qe2cpu_addr(be32_to_cpu(bdp->buf), qe_port);
 493
 494		/* loop through the buffer */
 495		while (i-- > 0) {
 496			ch = *cp++;
 497			port->icount.rx++;
 498			flg = TTY_NORMAL;
 499
 500			if (!i && status &
 501			    (BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV))
 502				goto handle_error;
 503			if (uart_handle_sysrq_char(port, ch))
 504				continue;
 505
 506error_return:
 507			tty_insert_flip_char(tport, ch, flg);
 508
 509		}
 510
 511		/* This BD is ready to be used again. Clear status. get next */
 512		qe_clrsetbits_be16(&bdp->status,
 513				   BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV | BD_SC_ID,
 514				   BD_SC_EMPTY);
 515		if (qe_ioread16be(&bdp->status) & BD_SC_WRAP)
 516			bdp = qe_port->rx_bd_base;
 517		else
 518			bdp++;
 519
 520	}
 521
 522	/* Write back buffer pointer */
 523	qe_port->rx_cur = bdp;
 524
 525	/* Activate BH processing */
 526	tty_flip_buffer_push(tport);
 527
 528	return;
 529
 530	/* Error processing */
 531
 532handle_error:
 533	/* Statistics */
 534	if (status & BD_SC_BR)
 535		port->icount.brk++;
 536	if (status & BD_SC_PR)
 537		port->icount.parity++;
 538	if (status & BD_SC_FR)
 539		port->icount.frame++;
 540	if (status & BD_SC_OV)
 541		port->icount.overrun++;
 542
 543	/* Mask out ignored conditions */
 544	status &= port->read_status_mask;
 545
 546	/* Handle the remaining ones */
 547	if (status & BD_SC_BR)
 548		flg = TTY_BREAK;
 549	else if (status & BD_SC_PR)
 550		flg = TTY_PARITY;
 551	else if (status & BD_SC_FR)
 552		flg = TTY_FRAME;
 553
 554	/* Overrun does not affect the current character ! */
 555	if (status & BD_SC_OV)
 556		tty_insert_flip_char(tport, 0, TTY_OVERRUN);
 557	port->sysrq = 0;
 558	goto error_return;
 559}
 560
 561/* Interrupt handler
 562 *
 563 * This interrupt handler is called after a BD is processed.
 564 */
 565static irqreturn_t qe_uart_int(int irq, void *data)
 566{
 567	struct uart_qe_port *qe_port = (struct uart_qe_port *) data;
 568	struct ucc_slow __iomem *uccp = qe_port->uccp;
 569	u16 events;
 570
 571	/* Clear the interrupts */
 572	events = qe_ioread16be(&uccp->ucce);
 573	qe_iowrite16be(events, &uccp->ucce);
 574
 575	if (events & UCC_UART_UCCE_BRKE)
 576		uart_handle_break(&qe_port->port);
 577
 578	if (events & UCC_UART_UCCE_RX)
 579		qe_uart_int_rx(qe_port);
 580
 581	if (events & UCC_UART_UCCE_TX)
 582		qe_uart_tx_pump(qe_port);
 583
 584	return events ? IRQ_HANDLED : IRQ_NONE;
 585}
 586
 587/* Initialize buffer descriptors
 588 *
 589 * This function initializes all of the RX and TX buffer descriptors.
 590 */
 591static void qe_uart_initbd(struct uart_qe_port *qe_port)
 592{
 593	int i;
 594	void *bd_virt;
 595	struct qe_bd *bdp;
 596
 597	/* Set the physical address of the host memory buffers in the buffer
 598	 * descriptors, and the virtual address for us to work with.
 599	 */
 600	bd_virt = qe_port->bd_virt;
 601	bdp = qe_port->rx_bd_base;
 602	qe_port->rx_cur = qe_port->rx_bd_base;
 603	for (i = 0; i < (qe_port->rx_nrfifos - 1); i++) {
 604		qe_iowrite16be(BD_SC_EMPTY | BD_SC_INTRPT, &bdp->status);
 605		qe_iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
 606		qe_iowrite16be(0, &bdp->length);
 607		bd_virt += qe_port->rx_fifosize;
 608		bdp++;
 609	}
 610
 611	/* */
 612	qe_iowrite16be(BD_SC_WRAP | BD_SC_EMPTY | BD_SC_INTRPT, &bdp->status);
 613	qe_iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
 614	qe_iowrite16be(0, &bdp->length);
 615
 616	/* Set the physical address of the host memory
 617	 * buffers in the buffer descriptors, and the
 618	 * virtual address for us to work with.
 619	 */
 620	bd_virt = qe_port->bd_virt +
 621		L1_CACHE_ALIGN(qe_port->rx_nrfifos * qe_port->rx_fifosize);
 622	qe_port->tx_cur = qe_port->tx_bd_base;
 623	bdp = qe_port->tx_bd_base;
 624	for (i = 0; i < (qe_port->tx_nrfifos - 1); i++) {
 625		qe_iowrite16be(BD_SC_INTRPT, &bdp->status);
 626		qe_iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
 627		qe_iowrite16be(0, &bdp->length);
 628		bd_virt += qe_port->tx_fifosize;
 629		bdp++;
 630	}
 631
 632	/* Loopback requires the preamble bit to be set on the first TX BD */
 633#ifdef LOOPBACK
 634	qe_setbits_be16(&qe_port->tx_cur->status, BD_SC_P);
 635#endif
 636
 637	qe_iowrite16be(BD_SC_WRAP | BD_SC_INTRPT, &bdp->status);
 638	qe_iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
 639	qe_iowrite16be(0, &bdp->length);
 640}
 641
 642/*
 643 * Initialize a UCC for UART.
 644 *
 645 * This function configures a given UCC to be used as a UART device. Basic
 646 * UCC initialization is handled in qe_uart_request_port().  This function
 647 * does all the UART-specific stuff.
 648 */
 649static void qe_uart_init_ucc(struct uart_qe_port *qe_port)
 650{
 651	u32 cecr_subblock;
 652	struct ucc_slow __iomem *uccp = qe_port->uccp;
 653	struct ucc_uart_pram *uccup = qe_port->uccup;
 654
 655	unsigned int i;
 656
 657	/* First, disable TX and RX in the UCC */
 658	ucc_slow_disable(qe_port->us_private, COMM_DIR_RX_AND_TX);
 659
 660	/* Program the UCC UART parameter RAM */
 661	qe_iowrite8(UCC_BMR_GBL | UCC_BMR_BO_BE, &uccup->common.rbmr);
 662	qe_iowrite8(UCC_BMR_GBL | UCC_BMR_BO_BE, &uccup->common.tbmr);
 663	qe_iowrite16be(qe_port->rx_fifosize, &uccup->common.mrblr);
 664	qe_iowrite16be(0x10, &uccup->maxidl);
 665	qe_iowrite16be(1, &uccup->brkcr);
 666	qe_iowrite16be(0, &uccup->parec);
 667	qe_iowrite16be(0, &uccup->frmec);
 668	qe_iowrite16be(0, &uccup->nosec);
 669	qe_iowrite16be(0, &uccup->brkec);
 670	qe_iowrite16be(0, &uccup->uaddr[0]);
 671	qe_iowrite16be(0, &uccup->uaddr[1]);
 672	qe_iowrite16be(0, &uccup->toseq);
 673	for (i = 0; i < 8; i++)
 674		qe_iowrite16be(0xC000, &uccup->cchars[i]);
 675	qe_iowrite16be(0xc0ff, &uccup->rccm);
 676
 677	/* Configure the GUMR registers for UART */
 678	if (soft_uart) {
 679		/* Soft-UART requires a 1X multiplier for TX */
 680		qe_clrsetbits_be32(&uccp->gumr_l,
 681				   UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK | UCC_SLOW_GUMR_L_RDCR_MASK,
 682				   UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_1 | UCC_SLOW_GUMR_L_RDCR_16);
 683
 684		qe_clrsetbits_be32(&uccp->gumr_h, UCC_SLOW_GUMR_H_RFW,
 685				   UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX);
 686	} else {
 687		qe_clrsetbits_be32(&uccp->gumr_l,
 688				   UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK | UCC_SLOW_GUMR_L_RDCR_MASK,
 689				   UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_16 | UCC_SLOW_GUMR_L_RDCR_16);
 690
 691		qe_clrsetbits_be32(&uccp->gumr_h,
 692				   UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX,
 693				   UCC_SLOW_GUMR_H_RFW);
 694	}
 695
 696#ifdef LOOPBACK
 697	qe_clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK,
 698			   UCC_SLOW_GUMR_L_DIAG_LOOP);
 699	qe_clrsetbits_be32(&uccp->gumr_h,
 700			   UCC_SLOW_GUMR_H_CTSP | UCC_SLOW_GUMR_H_RSYN,
 701			   UCC_SLOW_GUMR_H_CDS);
 702#endif
 703
 704	/* Disable rx interrupts  and clear all pending events.  */
 705	qe_iowrite16be(0, &uccp->uccm);
 706	qe_iowrite16be(0xffff, &uccp->ucce);
 707	qe_iowrite16be(0x7e7e, &uccp->udsr);
 708
 709	/* Initialize UPSMR */
 710	qe_iowrite16be(0, &uccp->upsmr);
 711
 712	if (soft_uart) {
 713		qe_iowrite16be(0x30, &uccup->supsmr);
 714		qe_iowrite16be(0, &uccup->res92);
 715		qe_iowrite32be(0, &uccup->rx_state);
 716		qe_iowrite32be(0, &uccup->rx_cnt);
 717		qe_iowrite8(0, &uccup->rx_bitmark);
 718		qe_iowrite8(10, &uccup->rx_length);
 719		qe_iowrite32be(0x4000, &uccup->dump_ptr);
 720		qe_iowrite8(0, &uccup->rx_temp_dlst_qe);
 721		qe_iowrite32be(0, &uccup->rx_frame_rem);
 722		qe_iowrite8(0, &uccup->rx_frame_rem_size);
 723		/* Soft-UART requires TX to be 1X */
 724		qe_iowrite8(UCC_UART_TX_STATE_UART | UCC_UART_TX_STATE_X1,
 725			    &uccup->tx_mode);
 726		qe_iowrite16be(0, &uccup->tx_state);
 727		qe_iowrite8(0, &uccup->resD4);
 728		qe_iowrite16be(0, &uccup->resD5);
 729
 730		/* Set UART mode.
 731		 * Enable receive and transmit.
 732		 */
 733
 734		/* From the microcode errata:
 735		 * 1.GUMR_L register, set mode=0010 (QMC).
 736		 * 2.Set GUMR_H[17] bit. (UART/AHDLC mode).
 737		 * 3.Set GUMR_H[19:20] (Transparent mode)
 738		 * 4.Clear GUMR_H[26] (RFW)
 739		 * ...
 740		 * 6.Receiver must use 16x over sampling
 741		 */
 742		qe_clrsetbits_be32(&uccp->gumr_l,
 743				   UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK | UCC_SLOW_GUMR_L_RDCR_MASK,
 744				   UCC_SLOW_GUMR_L_MODE_QMC | UCC_SLOW_GUMR_L_TDCR_16 | UCC_SLOW_GUMR_L_RDCR_16);
 745
 746		qe_clrsetbits_be32(&uccp->gumr_h,
 747				   UCC_SLOW_GUMR_H_RFW | UCC_SLOW_GUMR_H_RSYN,
 748				   UCC_SLOW_GUMR_H_SUART | UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX | UCC_SLOW_GUMR_H_TFL);
 749
 750#ifdef LOOPBACK
 751		qe_clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK,
 752				   UCC_SLOW_GUMR_L_DIAG_LOOP);
 753		qe_clrbits_be32(&uccp->gumr_h,
 754				UCC_SLOW_GUMR_H_CTSP | UCC_SLOW_GUMR_H_CDS);
 755#endif
 756
 757		cecr_subblock = ucc_slow_get_qe_cr_subblock(qe_port->ucc_num);
 758		qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock,
 759			QE_CR_PROTOCOL_UNSPECIFIED, 0);
 760	} else {
 761		cecr_subblock = ucc_slow_get_qe_cr_subblock(qe_port->ucc_num);
 762		qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock,
 763			QE_CR_PROTOCOL_UART, 0);
 764	}
 765}
 766
 767/*
 768 * Initialize the port.
 769 */
 770static int qe_uart_startup(struct uart_port *port)
 771{
 772	struct uart_qe_port *qe_port =
 773		container_of(port, struct uart_qe_port, port);
 774	int ret;
 775
 776	/*
 777	 * If we're using Soft-UART mode, then we need to make sure the
 778	 * firmware has been uploaded first.
 779	 */
 780	if (soft_uart && !firmware_loaded) {
 781		dev_err(port->dev, "Soft-UART firmware not uploaded\n");
 782		return -ENODEV;
 783	}
 784
 785	qe_uart_initbd(qe_port);
 786	qe_uart_init_ucc(qe_port);
 787
 788	/* Install interrupt handler. */
 789	ret = request_irq(port->irq, qe_uart_int, IRQF_SHARED, "ucc-uart",
 790		qe_port);
 791	if (ret) {
 792		dev_err(port->dev, "could not claim IRQ %u\n", port->irq);
 793		return ret;
 794	}
 795
 796	/* Startup rx-int */
 797	qe_setbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX);
 798	ucc_slow_enable(qe_port->us_private, COMM_DIR_RX_AND_TX);
 799
 800	return 0;
 801}
 802
 803/*
 804 * Shutdown the port.
 805 */
 806static void qe_uart_shutdown(struct uart_port *port)
 807{
 808	struct uart_qe_port *qe_port =
 809		container_of(port, struct uart_qe_port, port);
 810	struct ucc_slow __iomem *uccp = qe_port->uccp;
 811	unsigned int timeout = 20;
 812
 813	/* Disable RX and TX */
 814
 815	/* Wait for all the BDs marked sent */
 816	while (!qe_uart_tx_empty(port)) {
 817		if (!--timeout) {
 818			dev_warn(port->dev, "shutdown timeout\n");
 819			break;
 820		}
 821		set_current_state(TASK_UNINTERRUPTIBLE);
 822		schedule_timeout(2);
 823	}
 824
 825	if (qe_port->wait_closing) {
 826		/* Wait a bit longer */
 827		set_current_state(TASK_UNINTERRUPTIBLE);
 828		schedule_timeout(qe_port->wait_closing);
 829	}
 830
 831	/* Stop uarts */
 832	ucc_slow_disable(qe_port->us_private, COMM_DIR_RX_AND_TX);
 833	qe_clrbits_be16(&uccp->uccm, UCC_UART_UCCE_TX | UCC_UART_UCCE_RX);
 834
 835	/* Shut them really down and reinit buffer descriptors */
 836	ucc_slow_graceful_stop_tx(qe_port->us_private);
 837	qe_uart_initbd(qe_port);
 838
 839	free_irq(port->irq, qe_port);
 840}
 841
 842/*
 843 * Set the serial port parameters.
 844 */
 845static void qe_uart_set_termios(struct uart_port *port,
 846				struct ktermios *termios, struct ktermios *old)
 847{
 848	struct uart_qe_port *qe_port =
 849		container_of(port, struct uart_qe_port, port);
 850	struct ucc_slow __iomem *uccp = qe_port->uccp;
 851	unsigned int baud;
 852	unsigned long flags;
 853	u16 upsmr = qe_ioread16be(&uccp->upsmr);
 854	struct ucc_uart_pram __iomem *uccup = qe_port->uccup;
 855	u16 supsmr = qe_ioread16be(&uccup->supsmr);
 856	u8 char_length = 2; /* 1 + CL + PEN + 1 + SL */
 857
 858	/* Character length programmed into the mode register is the
 859	 * sum of: 1 start bit, number of data bits, 0 or 1 parity bit,
 860	 * 1 or 2 stop bits, minus 1.
 861	 * The value 'bits' counts this for us.
 862	 */
 863
 864	/* byte size */
 865	upsmr &= UCC_UART_UPSMR_CL_MASK;
 866	supsmr &= UCC_UART_SUPSMR_CL_MASK;
 867
 868	switch (termios->c_cflag & CSIZE) {
 869	case CS5:
 870		upsmr |= UCC_UART_UPSMR_CL_5;
 871		supsmr |= UCC_UART_SUPSMR_CL_5;
 872		char_length += 5;
 873		break;
 874	case CS6:
 875		upsmr |= UCC_UART_UPSMR_CL_6;
 876		supsmr |= UCC_UART_SUPSMR_CL_6;
 877		char_length += 6;
 878		break;
 879	case CS7:
 880		upsmr |= UCC_UART_UPSMR_CL_7;
 881		supsmr |= UCC_UART_SUPSMR_CL_7;
 882		char_length += 7;
 883		break;
 884	default:	/* case CS8 */
 885		upsmr |= UCC_UART_UPSMR_CL_8;
 886		supsmr |= UCC_UART_SUPSMR_CL_8;
 887		char_length += 8;
 888		break;
 889	}
 890
 891	/* If CSTOPB is set, we want two stop bits */
 892	if (termios->c_cflag & CSTOPB) {
 893		upsmr |= UCC_UART_UPSMR_SL;
 894		supsmr |= UCC_UART_SUPSMR_SL;
 895		char_length++;  /* + SL */
 896	}
 897
 898	if (termios->c_cflag & PARENB) {
 899		upsmr |= UCC_UART_UPSMR_PEN;
 900		supsmr |= UCC_UART_SUPSMR_PEN;
 901		char_length++;  /* + PEN */
 902
 903		if (!(termios->c_cflag & PARODD)) {
 904			upsmr &= ~(UCC_UART_UPSMR_RPM_MASK |
 905				   UCC_UART_UPSMR_TPM_MASK);
 906			upsmr |= UCC_UART_UPSMR_RPM_EVEN |
 907				UCC_UART_UPSMR_TPM_EVEN;
 908			supsmr &= ~(UCC_UART_SUPSMR_RPM_MASK |
 909				    UCC_UART_SUPSMR_TPM_MASK);
 910			supsmr |= UCC_UART_SUPSMR_RPM_EVEN |
 911				UCC_UART_SUPSMR_TPM_EVEN;
 912		}
 913	}
 914
 915	/*
 916	 * Set up parity check flag
 917	 */
 918	port->read_status_mask = BD_SC_EMPTY | BD_SC_OV;
 919	if (termios->c_iflag & INPCK)
 920		port->read_status_mask |= BD_SC_FR | BD_SC_PR;
 921	if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
 922		port->read_status_mask |= BD_SC_BR;
 923
 924	/*
 925	 * Characters to ignore
 926	 */
 927	port->ignore_status_mask = 0;
 928	if (termios->c_iflag & IGNPAR)
 929		port->ignore_status_mask |= BD_SC_PR | BD_SC_FR;
 930	if (termios->c_iflag & IGNBRK) {
 931		port->ignore_status_mask |= BD_SC_BR;
 932		/*
 933		 * If we're ignore parity and break indicators, ignore
 934		 * overruns too.  (For real raw support).
 935		 */
 936		if (termios->c_iflag & IGNPAR)
 937			port->ignore_status_mask |= BD_SC_OV;
 938	}
 939	/*
 940	 * !!! ignore all characters if CREAD is not set
 941	 */
 942	if ((termios->c_cflag & CREAD) == 0)
 943		port->read_status_mask &= ~BD_SC_EMPTY;
 944
 945	baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
 946
 947	/* Do we really need a spinlock here? */
 948	spin_lock_irqsave(&port->lock, flags);
 949
 950	/* Update the per-port timeout. */
 951	uart_update_timeout(port, termios->c_cflag, baud);
 952
 953	qe_iowrite16be(upsmr, &uccp->upsmr);
 954	if (soft_uart) {
 955		qe_iowrite16be(supsmr, &uccup->supsmr);
 956		qe_iowrite8(char_length, &uccup->rx_length);
 957
 958		/* Soft-UART requires a 1X multiplier for TX */
 959		qe_setbrg(qe_port->us_info.rx_clock, baud, 16);
 960		qe_setbrg(qe_port->us_info.tx_clock, baud, 1);
 961	} else {
 962		qe_setbrg(qe_port->us_info.rx_clock, baud, 16);
 963		qe_setbrg(qe_port->us_info.tx_clock, baud, 16);
 964	}
 965
 966	spin_unlock_irqrestore(&port->lock, flags);
 967}
 968
 969/*
 970 * Return a pointer to a string that describes what kind of port this is.
 971 */
 972static const char *qe_uart_type(struct uart_port *port)
 973{
 974	return "QE";
 975}
 976
 977/*
 978 * Allocate any memory and I/O resources required by the port.
 979 */
 980static int qe_uart_request_port(struct uart_port *port)
 981{
 982	int ret;
 983	struct uart_qe_port *qe_port =
 984		container_of(port, struct uart_qe_port, port);
 985	struct ucc_slow_info *us_info = &qe_port->us_info;
 986	struct ucc_slow_private *uccs;
 987	unsigned int rx_size, tx_size;
 988	void *bd_virt;
 989	dma_addr_t bd_dma_addr = 0;
 990
 991	ret = ucc_slow_init(us_info, &uccs);
 992	if (ret) {
 993		dev_err(port->dev, "could not initialize UCC%u\n",
 994		       qe_port->ucc_num);
 995		return ret;
 996	}
 997
 998	qe_port->us_private = uccs;
 999	qe_port->uccp = uccs->us_regs;
1000	qe_port->uccup = (struct ucc_uart_pram *) uccs->us_pram;
1001	qe_port->rx_bd_base = uccs->rx_bd;
1002	qe_port->tx_bd_base = uccs->tx_bd;
1003
1004	/*
1005	 * Allocate the transmit and receive data buffers.
1006	 */
1007
1008	rx_size = L1_CACHE_ALIGN(qe_port->rx_nrfifos * qe_port->rx_fifosize);
1009	tx_size = L1_CACHE_ALIGN(qe_port->tx_nrfifos * qe_port->tx_fifosize);
1010
1011	bd_virt = dma_alloc_coherent(port->dev, rx_size + tx_size, &bd_dma_addr,
1012		GFP_KERNEL);
1013	if (!bd_virt) {
1014		dev_err(port->dev, "could not allocate buffer descriptors\n");
1015		return -ENOMEM;
1016	}
1017
1018	qe_port->bd_virt = bd_virt;
1019	qe_port->bd_dma_addr = bd_dma_addr;
1020	qe_port->bd_size = rx_size + tx_size;
1021
1022	qe_port->rx_buf = bd_virt;
1023	qe_port->tx_buf = qe_port->rx_buf + rx_size;
1024
1025	return 0;
1026}
1027
1028/*
1029 * Configure the port.
1030 *
1031 * We say we're a CPM-type port because that's mostly true.  Once the device
1032 * is configured, this driver operates almost identically to the CPM serial
1033 * driver.
1034 */
1035static void qe_uart_config_port(struct uart_port *port, int flags)
1036{
1037	if (flags & UART_CONFIG_TYPE) {
1038		port->type = PORT_CPM;
1039		qe_uart_request_port(port);
1040	}
1041}
1042
1043/*
1044 * Release any memory and I/O resources that were allocated in
1045 * qe_uart_request_port().
1046 */
1047static void qe_uart_release_port(struct uart_port *port)
1048{
1049	struct uart_qe_port *qe_port =
1050		container_of(port, struct uart_qe_port, port);
1051	struct ucc_slow_private *uccs = qe_port->us_private;
1052
1053	dma_free_coherent(port->dev, qe_port->bd_size, qe_port->bd_virt,
1054			  qe_port->bd_dma_addr);
1055
1056	ucc_slow_free(uccs);
1057}
1058
1059/*
1060 * Verify that the data in serial_struct is suitable for this device.
1061 */
1062static int qe_uart_verify_port(struct uart_port *port,
1063			       struct serial_struct *ser)
1064{
1065	if (ser->type != PORT_UNKNOWN && ser->type != PORT_CPM)
1066		return -EINVAL;
1067
1068	if (ser->irq < 0 || ser->irq >= nr_irqs)
1069		return -EINVAL;
1070
1071	if (ser->baud_base < 9600)
1072		return -EINVAL;
1073
1074	return 0;
1075}
1076/* UART operations
1077 *
1078 * Details on these functions can be found in Documentation/driver-api/serial/driver.rst
1079 */
1080static const struct uart_ops qe_uart_pops = {
1081	.tx_empty       = qe_uart_tx_empty,
1082	.set_mctrl      = qe_uart_set_mctrl,
1083	.get_mctrl      = qe_uart_get_mctrl,
1084	.stop_tx	= qe_uart_stop_tx,
1085	.start_tx       = qe_uart_start_tx,
1086	.stop_rx	= qe_uart_stop_rx,
1087	.break_ctl      = qe_uart_break_ctl,
1088	.startup	= qe_uart_startup,
1089	.shutdown       = qe_uart_shutdown,
1090	.set_termios    = qe_uart_set_termios,
1091	.type   	= qe_uart_type,
1092	.release_port   = qe_uart_release_port,
1093	.request_port   = qe_uart_request_port,
1094	.config_port    = qe_uart_config_port,
1095	.verify_port    = qe_uart_verify_port,
1096};
1097
1098
1099#ifdef CONFIG_PPC32
1100/*
1101 * Obtain the SOC model number and revision level
1102 *
1103 * This function parses the device tree to obtain the SOC model.  It then
1104 * reads the SVR register to the revision.
1105 *
1106 * The device tree stores the SOC model two different ways.
1107 *
1108 * The new way is:
1109 *
1110 *      	cpu@0 {
1111 *      		compatible = "PowerPC,8323";
1112 *      		device_type = "cpu";
1113 *      		...
1114 *
1115 *
1116 * The old way is:
1117 *      	 PowerPC,8323@0 {
1118 *      		device_type = "cpu";
1119 *      		...
1120 *
1121 * This code first checks the new way, and then the old way.
1122 */
1123static unsigned int soc_info(unsigned int *rev_h, unsigned int *rev_l)
1124{
1125	struct device_node *np;
1126	const char *soc_string;
1127	unsigned int svr;
1128	unsigned int soc;
1129
1130	/* Find the CPU node */
1131	np = of_find_node_by_type(NULL, "cpu");
1132	if (!np)
1133		return 0;
1134	/* Find the compatible property */
1135	soc_string = of_get_property(np, "compatible", NULL);
1136	if (!soc_string)
1137		/* No compatible property, so try the name. */
1138		soc_string = np->name;
1139
1140	/* Extract the SOC number from the "PowerPC," string */
1141	if ((sscanf(soc_string, "PowerPC,%u", &soc) != 1) || !soc)
1142		return 0;
1143
1144	/* Get the revision from the SVR */
1145	svr = mfspr(SPRN_SVR);
1146	*rev_h = (svr >> 4) & 0xf;
1147	*rev_l = svr & 0xf;
1148
1149	return soc;
1150}
1151
1152/*
1153 * requst_firmware_nowait() callback function
1154 *
1155 * This function is called by the kernel when a firmware is made available,
1156 * or if it times out waiting for the firmware.
1157 */
1158static void uart_firmware_cont(const struct firmware *fw, void *context)
1159{
1160	struct qe_firmware *firmware;
1161	struct device *dev = context;
1162	int ret;
1163
1164	if (!fw) {
1165		dev_err(dev, "firmware not found\n");
1166		return;
1167	}
1168
1169	firmware = (struct qe_firmware *) fw->data;
1170
1171	if (firmware->header.length != fw->size) {
1172		dev_err(dev, "invalid firmware\n");
1173		goto out;
1174	}
1175
1176	ret = qe_upload_firmware(firmware);
1177	if (ret) {
1178		dev_err(dev, "could not load firmware\n");
1179		goto out;
1180	}
1181
1182	firmware_loaded = 1;
1183 out:
1184	release_firmware(fw);
1185}
1186
1187static int soft_uart_init(struct platform_device *ofdev)
1188{
1189	struct device_node *np = ofdev->dev.of_node;
1190	struct qe_firmware_info *qe_fw_info;
1191	int ret;
1192
1193	if (of_find_property(np, "soft-uart", NULL)) {
1194		dev_dbg(&ofdev->dev, "using Soft-UART mode\n");
1195		soft_uart = 1;
1196	} else {
1197		return 0;
1198	}
1199
1200	qe_fw_info = qe_get_firmware_info();
1201
1202	/* Check if the firmware has been uploaded. */
1203	if (qe_fw_info && strstr(qe_fw_info->id, "Soft-UART")) {
1204		firmware_loaded = 1;
1205	} else {
1206		char filename[32];
1207		unsigned int soc;
1208		unsigned int rev_h;
1209		unsigned int rev_l;
1210
1211		soc = soc_info(&rev_h, &rev_l);
1212		if (!soc) {
1213			dev_err(&ofdev->dev, "unknown CPU model\n");
1214			return -ENXIO;
1215		}
1216		sprintf(filename, "fsl_qe_ucode_uart_%u_%u%u.bin",
1217			soc, rev_h, rev_l);
1218
1219		dev_info(&ofdev->dev, "waiting for firmware %s\n",
1220			 filename);
1221
1222		/*
1223		 * We call request_firmware_nowait instead of
1224		 * request_firmware so that the driver can load and
1225		 * initialize the ports without holding up the rest of
1226		 * the kernel.  If hotplug support is enabled in the
1227		 * kernel, then we use it.
1228		 */
1229		ret = request_firmware_nowait(THIS_MODULE,
1230					      FW_ACTION_HOTPLUG, filename, &ofdev->dev,
1231					      GFP_KERNEL, &ofdev->dev, uart_firmware_cont);
1232		if (ret) {
1233			dev_err(&ofdev->dev,
1234				"could not load firmware %s\n",
1235				filename);
1236			return ret;
1237		}
1238	}
1239	return 0;
1240}
1241
1242#else /* !CONFIG_PPC32 */
1243
1244static int soft_uart_init(struct platform_device *ofdev)
1245{
1246	return 0;
1247}
1248
1249#endif
1250
1251
1252static int ucc_uart_probe(struct platform_device *ofdev)
1253{
1254	struct device_node *np = ofdev->dev.of_node;
1255	const char *sprop;      /* String OF properties */
1256	struct uart_qe_port *qe_port = NULL;
1257	struct resource res;
1258	u32 val;
1259	int ret;
1260
1261	/*
1262	 * Determine if we need Soft-UART mode
1263	 */
1264	ret = soft_uart_init(ofdev);
1265	if (ret)
1266		return ret;
1267
1268	qe_port = kzalloc(sizeof(struct uart_qe_port), GFP_KERNEL);
1269	if (!qe_port) {
1270		dev_err(&ofdev->dev, "can't allocate QE port structure\n");
1271		return -ENOMEM;
1272	}
1273
1274	/* Search for IRQ and mapbase */
1275	ret = of_address_to_resource(np, 0, &res);
1276	if (ret) {
1277		dev_err(&ofdev->dev, "missing 'reg' property in device tree\n");
1278		goto out_free;
1279	}
1280	if (!res.start) {
1281		dev_err(&ofdev->dev, "invalid 'reg' property in device tree\n");
1282		ret = -EINVAL;
1283		goto out_free;
1284	}
1285	qe_port->port.mapbase = res.start;
1286
1287	/* Get the UCC number (device ID) */
1288	/* UCCs are numbered 1-7 */
1289	if (of_property_read_u32(np, "cell-index", &val)) {
1290		if (of_property_read_u32(np, "device-id", &val)) {
1291			dev_err(&ofdev->dev, "UCC is unspecified in device tree\n");
1292			ret = -EINVAL;
1293			goto out_free;
1294		}
1295	}
1296
1297	if (val < 1 || val > UCC_MAX_NUM) {
1298		dev_err(&ofdev->dev, "no support for UCC%u\n", val);
1299		ret = -ENODEV;
1300		goto out_free;
1301	}
1302	qe_port->ucc_num = val - 1;
1303
1304	/*
1305	 * In the future, we should not require the BRG to be specified in the
1306	 * device tree.  If no clock-source is specified, then just pick a BRG
1307	 * to use.  This requires a new QE library function that manages BRG
1308	 * assignments.
1309	 */
1310
1311	sprop = of_get_property(np, "rx-clock-name", NULL);
1312	if (!sprop) {
1313		dev_err(&ofdev->dev, "missing rx-clock-name in device tree\n");
1314		ret = -ENODEV;
1315		goto out_free;
1316	}
1317
1318	qe_port->us_info.rx_clock = qe_clock_source(sprop);
1319	if ((qe_port->us_info.rx_clock < QE_BRG1) ||
1320	    (qe_port->us_info.rx_clock > QE_BRG16)) {
1321		dev_err(&ofdev->dev, "rx-clock-name must be a BRG for UART\n");
1322		ret = -ENODEV;
1323		goto out_free;
1324	}
1325
1326#ifdef LOOPBACK
1327	/* In internal loopback mode, TX and RX must use the same clock */
1328	qe_port->us_info.tx_clock = qe_port->us_info.rx_clock;
1329#else
1330	sprop = of_get_property(np, "tx-clock-name", NULL);
1331	if (!sprop) {
1332		dev_err(&ofdev->dev, "missing tx-clock-name in device tree\n");
1333		ret = -ENODEV;
1334		goto out_free;
1335	}
1336	qe_port->us_info.tx_clock = qe_clock_source(sprop);
1337#endif
1338	if ((qe_port->us_info.tx_clock < QE_BRG1) ||
1339	    (qe_port->us_info.tx_clock > QE_BRG16)) {
1340		dev_err(&ofdev->dev, "tx-clock-name must be a BRG for UART\n");
1341		ret = -ENODEV;
1342		goto out_free;
1343	}
1344
1345	/* Get the port number, numbered 0-3 */
1346	if (of_property_read_u32(np, "port-number", &val)) {
1347		dev_err(&ofdev->dev, "missing port-number in device tree\n");
1348		ret = -EINVAL;
1349		goto out_free;
1350	}
1351	qe_port->port.line = val;
1352	if (qe_port->port.line >= UCC_MAX_UART) {
1353		dev_err(&ofdev->dev, "port-number must be 0-%u\n",
1354			UCC_MAX_UART - 1);
1355		ret = -EINVAL;
1356		goto out_free;
1357	}
1358
1359	qe_port->port.irq = irq_of_parse_and_map(np, 0);
1360	if (qe_port->port.irq == 0) {
1361		dev_err(&ofdev->dev, "could not map IRQ for UCC%u\n",
1362		       qe_port->ucc_num + 1);
1363		ret = -EINVAL;
1364		goto out_free;
1365	}
1366
1367	/*
1368	 * Newer device trees have an "fsl,qe" compatible property for the QE
1369	 * node, but we still need to support older device trees.
1370	 */
1371	np = of_find_compatible_node(NULL, NULL, "fsl,qe");
1372	if (!np) {
1373		np = of_find_node_by_type(NULL, "qe");
1374		if (!np) {
1375			dev_err(&ofdev->dev, "could not find 'qe' node\n");
1376			ret = -EINVAL;
1377			goto out_free;
1378		}
1379	}
1380
1381	if (of_property_read_u32(np, "brg-frequency", &val)) {
1382		dev_err(&ofdev->dev,
1383		       "missing brg-frequency in device tree\n");
1384		ret = -EINVAL;
1385		goto out_np;
1386	}
1387
1388	if (val)
1389		qe_port->port.uartclk = val;
1390	else {
1391		if (!IS_ENABLED(CONFIG_PPC32)) {
1392			dev_err(&ofdev->dev,
1393				"invalid brg-frequency in device tree\n");
1394			ret = -EINVAL;
1395			goto out_np;
1396		}
1397
1398		/*
1399		 * Older versions of U-Boot do not initialize the brg-frequency
1400		 * property, so in this case we assume the BRG frequency is
1401		 * half the QE bus frequency.
1402		 */
1403		if (of_property_read_u32(np, "bus-frequency", &val)) {
1404			dev_err(&ofdev->dev,
1405				"missing QE bus-frequency in device tree\n");
1406			ret = -EINVAL;
1407			goto out_np;
1408		}
1409		if (val)
1410			qe_port->port.uartclk = val / 2;
1411		else {
1412			dev_err(&ofdev->dev,
1413				"invalid QE bus-frequency in device tree\n");
1414			ret = -EINVAL;
1415			goto out_np;
1416		}
1417	}
1418
1419	spin_lock_init(&qe_port->port.lock);
1420	qe_port->np = np;
1421	qe_port->port.dev = &ofdev->dev;
1422	qe_port->port.ops = &qe_uart_pops;
1423	qe_port->port.iotype = UPIO_MEM;
1424
1425	qe_port->tx_nrfifos = TX_NUM_FIFO;
1426	qe_port->tx_fifosize = TX_BUF_SIZE;
1427	qe_port->rx_nrfifos = RX_NUM_FIFO;
1428	qe_port->rx_fifosize = RX_BUF_SIZE;
1429
1430	qe_port->wait_closing = UCC_WAIT_CLOSING;
1431	qe_port->port.fifosize = 512;
1432	qe_port->port.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP;
1433
1434	qe_port->us_info.ucc_num = qe_port->ucc_num;
1435	qe_port->us_info.regs = (phys_addr_t) res.start;
1436	qe_port->us_info.irq = qe_port->port.irq;
1437
1438	qe_port->us_info.rx_bd_ring_len = qe_port->rx_nrfifos;
1439	qe_port->us_info.tx_bd_ring_len = qe_port->tx_nrfifos;
1440
1441	/* Make sure ucc_slow_init() initializes both TX and RX */
1442	qe_port->us_info.init_tx = 1;
1443	qe_port->us_info.init_rx = 1;
1444
1445	/* Add the port to the uart sub-system.  This will cause
1446	 * qe_uart_config_port() to be called, so the us_info structure must
1447	 * be initialized.
1448	 */
1449	ret = uart_add_one_port(&ucc_uart_driver, &qe_port->port);
1450	if (ret) {
1451		dev_err(&ofdev->dev, "could not add /dev/ttyQE%u\n",
1452		       qe_port->port.line);
1453		goto out_np;
1454	}
1455
1456	platform_set_drvdata(ofdev, qe_port);
1457
1458	dev_info(&ofdev->dev, "UCC%u assigned to /dev/ttyQE%u\n",
1459		qe_port->ucc_num + 1, qe_port->port.line);
1460
1461	/* Display the mknod command for this device */
1462	dev_dbg(&ofdev->dev, "mknod command is 'mknod /dev/ttyQE%u c %u %u'\n",
1463	       qe_port->port.line, SERIAL_QE_MAJOR,
1464	       SERIAL_QE_MINOR + qe_port->port.line);
1465
1466	return 0;
1467out_np:
1468	of_node_put(np);
1469out_free:
1470	kfree(qe_port);
1471	return ret;
1472}
1473
1474static int ucc_uart_remove(struct platform_device *ofdev)
1475{
1476	struct uart_qe_port *qe_port = platform_get_drvdata(ofdev);
1477
1478	dev_info(&ofdev->dev, "removing /dev/ttyQE%u\n", qe_port->port.line);
1479
1480	uart_remove_one_port(&ucc_uart_driver, &qe_port->port);
1481
1482	kfree(qe_port);
1483
1484	return 0;
1485}
1486
1487static const struct of_device_id ucc_uart_match[] = {
1488	{
1489		.type = "serial",
1490		.compatible = "ucc_uart",
1491	},
1492	{
1493		.compatible = "fsl,t1040-ucc-uart",
1494	},
1495	{},
1496};
1497MODULE_DEVICE_TABLE(of, ucc_uart_match);
1498
1499static struct platform_driver ucc_uart_of_driver = {
1500	.driver = {
1501		.name = "ucc_uart",
1502		.of_match_table    = ucc_uart_match,
1503	},
1504	.probe  	= ucc_uart_probe,
1505	.remove 	= ucc_uart_remove,
1506};
1507
1508static int __init ucc_uart_init(void)
1509{
1510	int ret;
1511
1512	printk(KERN_INFO "Freescale QUICC Engine UART device driver\n");
1513#ifdef LOOPBACK
1514	printk(KERN_INFO "ucc-uart: Using loopback mode\n");
1515#endif
1516
1517	ret = uart_register_driver(&ucc_uart_driver);
1518	if (ret) {
1519		printk(KERN_ERR "ucc-uart: could not register UART driver\n");
1520		return ret;
1521	}
1522
1523	ret = platform_driver_register(&ucc_uart_of_driver);
1524	if (ret) {
1525		printk(KERN_ERR
1526		       "ucc-uart: could not register platform driver\n");
1527		uart_unregister_driver(&ucc_uart_driver);
1528	}
1529
1530	return ret;
1531}
1532
1533static void __exit ucc_uart_exit(void)
1534{
1535	printk(KERN_INFO
1536	       "Freescale QUICC Engine UART device driver unloading\n");
1537
1538	platform_driver_unregister(&ucc_uart_of_driver);
1539	uart_unregister_driver(&ucc_uart_driver);
1540}
1541
1542module_init(ucc_uart_init);
1543module_exit(ucc_uart_exit);
1544
1545MODULE_DESCRIPTION("Freescale QUICC Engine (QE) UART");
1546MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
1547MODULE_LICENSE("GPL v2");
1548MODULE_ALIAS_CHARDEV_MAJOR(SERIAL_QE_MAJOR);
1549