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/drivers/tty/serial/msm_serial.h

http://github.com/mirrors/linux
C++ Header | 178 lines | 130 code | 23 blank | 25 comment | 5 complexity | e40b84a91edb50a01a14df1ec332d24f MD5 | raw file
  1/*
  2 * Copyright (C) 2007 Google, Inc.
  3 * Author: Robert Love <rlove@google.com>
  4 * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
  5 *
  6 * This software is licensed under the terms of the GNU General Public
  7 * License version 2, as published by the Free Software Foundation, and
  8 * may be copied, distributed, and modified under those terms.
  9 *
 10 * This program is distributed in the hope that it will be useful,
 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 13 * GNU General Public License for more details.
 14 */
 15
 16#ifndef __DRIVERS_SERIAL_MSM_SERIAL_H
 17#define __DRIVERS_SERIAL_MSM_SERIAL_H
 18
 19#define UART_MR1			0x0000
 20
 21#define UART_MR1_AUTO_RFR_LEVEL0	0x3F
 22#define UART_MR1_AUTO_RFR_LEVEL1	0x3FF00
 23#define UART_MR1_RX_RDY_CTL    		(1 << 7)
 24#define UART_MR1_CTS_CTL       		(1 << 6)
 25
 26#define UART_MR2			0x0004
 27#define UART_MR2_ERROR_MODE		(1 << 6)
 28#define UART_MR2_BITS_PER_CHAR		0x30
 29#define UART_MR2_BITS_PER_CHAR_5	(0x0 << 4)
 30#define UART_MR2_BITS_PER_CHAR_6	(0x1 << 4)
 31#define UART_MR2_BITS_PER_CHAR_7	(0x2 << 4)
 32#define UART_MR2_BITS_PER_CHAR_8	(0x3 << 4)
 33#define UART_MR2_STOP_BIT_LEN_ONE	(0x1 << 2)
 34#define UART_MR2_STOP_BIT_LEN_TWO	(0x3 << 2)
 35#define UART_MR2_PARITY_MODE_NONE	0x0
 36#define UART_MR2_PARITY_MODE_ODD	0x1
 37#define UART_MR2_PARITY_MODE_EVEN	0x2
 38#define UART_MR2_PARITY_MODE_SPACE	0x3
 39#define UART_MR2_PARITY_MODE		0x3
 40
 41#define UART_CSR			0x0008
 42
 43#define UART_TF		0x000C
 44#define UARTDM_TF	0x0070
 45
 46#define UART_CR				0x0010
 47#define UART_CR_CMD_NULL		(0 << 4)
 48#define UART_CR_CMD_RESET_RX		(1 << 4)
 49#define UART_CR_CMD_RESET_TX		(2 << 4)
 50#define UART_CR_CMD_RESET_ERR		(3 << 4)
 51#define UART_CR_CMD_RESET_BREAK_INT	(4 << 4)
 52#define UART_CR_CMD_START_BREAK		(5 << 4)
 53#define UART_CR_CMD_STOP_BREAK		(6 << 4)
 54#define UART_CR_CMD_RESET_CTS		(7 << 4)
 55#define UART_CR_CMD_RESET_STALE_INT	(8 << 4)
 56#define UART_CR_CMD_PACKET_MODE		(9 << 4)
 57#define UART_CR_CMD_MODE_RESET		(12 << 4)
 58#define UART_CR_CMD_SET_RFR		(13 << 4)
 59#define UART_CR_CMD_RESET_RFR		(14 << 4)
 60#define UART_CR_CMD_PROTECTION_EN	(16 << 4)
 61#define UART_CR_CMD_STALE_EVENT_ENABLE	(80 << 4)
 62#define UART_CR_CMD_RESET_TX_READY	(3 << 8)
 63#define UART_CR_TX_DISABLE		(1 << 3)
 64#define UART_CR_TX_ENABLE		(1 << 2)
 65#define UART_CR_RX_DISABLE		(1 << 1)
 66#define UART_CR_RX_ENABLE		(1 << 0)
 67
 68#define UART_IMR		0x0014
 69#define UART_IMR_TXLEV		(1 << 0)
 70#define UART_IMR_RXSTALE	(1 << 3)
 71#define UART_IMR_RXLEV		(1 << 4)
 72#define UART_IMR_DELTA_CTS	(1 << 5)
 73#define UART_IMR_CURRENT_CTS	(1 << 6)
 74
 75#define UART_IPR_RXSTALE_LAST		0x20
 76#define UART_IPR_STALE_LSB		0x1F
 77#define UART_IPR_STALE_TIMEOUT_MSB	0x3FF80
 78
 79#define UART_IPR	0x0018
 80#define UART_TFWR	0x001C
 81#define UART_RFWR	0x0020
 82#define UART_HCR	0x0024
 83
 84#define UART_MREG		0x0028
 85#define UART_NREG		0x002C
 86#define UART_DREG		0x0030
 87#define UART_MNDREG		0x0034
 88#define UART_IRDA		0x0038
 89#define UART_MISR_MODE		0x0040
 90#define UART_MISR_RESET		0x0044
 91#define UART_MISR_EXPORT	0x0048
 92#define UART_MISR_VAL		0x004C
 93#define UART_TEST_CTRL		0x0050
 94
 95#define UART_SR			0x0008
 96#define UART_SR_HUNT_CHAR	(1 << 7)
 97#define UART_SR_RX_BREAK	(1 << 6)
 98#define UART_SR_PAR_FRAME_ERR	(1 << 5)
 99#define UART_SR_OVERRUN		(1 << 4)
100#define UART_SR_TX_EMPTY	(1 << 3)
101#define UART_SR_TX_READY	(1 << 2)
102#define UART_SR_RX_FULL		(1 << 1)
103#define UART_SR_RX_READY	(1 << 0)
104
105#define UART_RF			0x000C
106#define UARTDM_RF		0x0070
107#define UART_MISR		0x0010
108#define UART_ISR		0x0014
109#define UART_ISR_TX_READY	(1 << 7)
110
111#define GSBI_CONTROL		0x0
112#define GSBI_PROTOCOL_CODE	0x30
113#define GSBI_PROTOCOL_UART	0x40
114#define GSBI_PROTOCOL_IDLE	0x0
115
116#define UARTDM_DMRX		0x34
117#define UARTDM_NCF_TX		0x40
118#define UARTDM_RX_TOTAL_SNAP	0x38
119
120#define UART_TO_MSM(uart_port)	((struct msm_port *) uart_port)
121
122static inline
123void msm_write(struct uart_port *port, unsigned int val, unsigned int off)
124{
125	__raw_writel(val, port->membase + off);
126}
127
128static inline
129unsigned int msm_read(struct uart_port *port, unsigned int off)
130{
131	return __raw_readl(port->membase + off);
132}
133
134/*
135 * Setup the MND registers to use the TCXO clock.
136 */
137static inline void msm_serial_set_mnd_regs_tcxo(struct uart_port *port)
138{
139	msm_write(port, 0x06, UART_MREG);
140	msm_write(port, 0xF1, UART_NREG);
141	msm_write(port, 0x0F, UART_DREG);
142	msm_write(port, 0x1A, UART_MNDREG);
143	port->uartclk = 1843200;
144}
145
146/*
147 * Setup the MND registers to use the TCXO clock divided by 4.
148 */
149static inline void msm_serial_set_mnd_regs_tcxoby4(struct uart_port *port)
150{
151	msm_write(port, 0x18, UART_MREG);
152	msm_write(port, 0xF6, UART_NREG);
153	msm_write(port, 0x0F, UART_DREG);
154	msm_write(port, 0x0A, UART_MNDREG);
155	port->uartclk = 1843200;
156}
157
158static inline
159void msm_serial_set_mnd_regs_from_uartclk(struct uart_port *port)
160{
161	if (port->uartclk == 19200000)
162		msm_serial_set_mnd_regs_tcxo(port);
163	else if (port->uartclk == 4800000)
164		msm_serial_set_mnd_regs_tcxoby4(port);
165}
166
167/*
168 * TROUT has a specific defect that makes it report it's uartclk
169 * as 19.2Mhz (TCXO) when it's actually 4.8Mhz (TCXO/4). This special
170 * cases TROUT to use the right clock.
171 */
172#ifdef CONFIG_MACH_TROUT
173#define msm_serial_set_mnd_regs msm_serial_set_mnd_regs_tcxoby4
174#else
175#define msm_serial_set_mnd_regs msm_serial_set_mnd_regs_from_uartclk
176#endif
177
178#endif	/* __DRIVERS_SERIAL_MSM_SERIAL_H */