/drivers/tty/serial/msm_serial.h

http://github.com/mirrors/linux · C Header · 178 lines · 130 code · 23 blank · 25 comment · 5 complexity · e40b84a91edb50a01a14df1ec332d24f MD5 · raw file

  1. /*
  2. * Copyright (C) 2007 Google, Inc.
  3. * Author: Robert Love <rlove@google.com>
  4. * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
  5. *
  6. * This software is licensed under the terms of the GNU General Public
  7. * License version 2, as published by the Free Software Foundation, and
  8. * may be copied, distributed, and modified under those terms.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. */
  15. #ifndef __DRIVERS_SERIAL_MSM_SERIAL_H
  16. #define __DRIVERS_SERIAL_MSM_SERIAL_H
  17. #define UART_MR1 0x0000
  18. #define UART_MR1_AUTO_RFR_LEVEL0 0x3F
  19. #define UART_MR1_AUTO_RFR_LEVEL1 0x3FF00
  20. #define UART_MR1_RX_RDY_CTL (1 << 7)
  21. #define UART_MR1_CTS_CTL (1 << 6)
  22. #define UART_MR2 0x0004
  23. #define UART_MR2_ERROR_MODE (1 << 6)
  24. #define UART_MR2_BITS_PER_CHAR 0x30
  25. #define UART_MR2_BITS_PER_CHAR_5 (0x0 << 4)
  26. #define UART_MR2_BITS_PER_CHAR_6 (0x1 << 4)
  27. #define UART_MR2_BITS_PER_CHAR_7 (0x2 << 4)
  28. #define UART_MR2_BITS_PER_CHAR_8 (0x3 << 4)
  29. #define UART_MR2_STOP_BIT_LEN_ONE (0x1 << 2)
  30. #define UART_MR2_STOP_BIT_LEN_TWO (0x3 << 2)
  31. #define UART_MR2_PARITY_MODE_NONE 0x0
  32. #define UART_MR2_PARITY_MODE_ODD 0x1
  33. #define UART_MR2_PARITY_MODE_EVEN 0x2
  34. #define UART_MR2_PARITY_MODE_SPACE 0x3
  35. #define UART_MR2_PARITY_MODE 0x3
  36. #define UART_CSR 0x0008
  37. #define UART_TF 0x000C
  38. #define UARTDM_TF 0x0070
  39. #define UART_CR 0x0010
  40. #define UART_CR_CMD_NULL (0 << 4)
  41. #define UART_CR_CMD_RESET_RX (1 << 4)
  42. #define UART_CR_CMD_RESET_TX (2 << 4)
  43. #define UART_CR_CMD_RESET_ERR (3 << 4)
  44. #define UART_CR_CMD_RESET_BREAK_INT (4 << 4)
  45. #define UART_CR_CMD_START_BREAK (5 << 4)
  46. #define UART_CR_CMD_STOP_BREAK (6 << 4)
  47. #define UART_CR_CMD_RESET_CTS (7 << 4)
  48. #define UART_CR_CMD_RESET_STALE_INT (8 << 4)
  49. #define UART_CR_CMD_PACKET_MODE (9 << 4)
  50. #define UART_CR_CMD_MODE_RESET (12 << 4)
  51. #define UART_CR_CMD_SET_RFR (13 << 4)
  52. #define UART_CR_CMD_RESET_RFR (14 << 4)
  53. #define UART_CR_CMD_PROTECTION_EN (16 << 4)
  54. #define UART_CR_CMD_STALE_EVENT_ENABLE (80 << 4)
  55. #define UART_CR_CMD_RESET_TX_READY (3 << 8)
  56. #define UART_CR_TX_DISABLE (1 << 3)
  57. #define UART_CR_TX_ENABLE (1 << 2)
  58. #define UART_CR_RX_DISABLE (1 << 1)
  59. #define UART_CR_RX_ENABLE (1 << 0)
  60. #define UART_IMR 0x0014
  61. #define UART_IMR_TXLEV (1 << 0)
  62. #define UART_IMR_RXSTALE (1 << 3)
  63. #define UART_IMR_RXLEV (1 << 4)
  64. #define UART_IMR_DELTA_CTS (1 << 5)
  65. #define UART_IMR_CURRENT_CTS (1 << 6)
  66. #define UART_IPR_RXSTALE_LAST 0x20
  67. #define UART_IPR_STALE_LSB 0x1F
  68. #define UART_IPR_STALE_TIMEOUT_MSB 0x3FF80
  69. #define UART_IPR 0x0018
  70. #define UART_TFWR 0x001C
  71. #define UART_RFWR 0x0020
  72. #define UART_HCR 0x0024
  73. #define UART_MREG 0x0028
  74. #define UART_NREG 0x002C
  75. #define UART_DREG 0x0030
  76. #define UART_MNDREG 0x0034
  77. #define UART_IRDA 0x0038
  78. #define UART_MISR_MODE 0x0040
  79. #define UART_MISR_RESET 0x0044
  80. #define UART_MISR_EXPORT 0x0048
  81. #define UART_MISR_VAL 0x004C
  82. #define UART_TEST_CTRL 0x0050
  83. #define UART_SR 0x0008
  84. #define UART_SR_HUNT_CHAR (1 << 7)
  85. #define UART_SR_RX_BREAK (1 << 6)
  86. #define UART_SR_PAR_FRAME_ERR (1 << 5)
  87. #define UART_SR_OVERRUN (1 << 4)
  88. #define UART_SR_TX_EMPTY (1 << 3)
  89. #define UART_SR_TX_READY (1 << 2)
  90. #define UART_SR_RX_FULL (1 << 1)
  91. #define UART_SR_RX_READY (1 << 0)
  92. #define UART_RF 0x000C
  93. #define UARTDM_RF 0x0070
  94. #define UART_MISR 0x0010
  95. #define UART_ISR 0x0014
  96. #define UART_ISR_TX_READY (1 << 7)
  97. #define GSBI_CONTROL 0x0
  98. #define GSBI_PROTOCOL_CODE 0x30
  99. #define GSBI_PROTOCOL_UART 0x40
  100. #define GSBI_PROTOCOL_IDLE 0x0
  101. #define UARTDM_DMRX 0x34
  102. #define UARTDM_NCF_TX 0x40
  103. #define UARTDM_RX_TOTAL_SNAP 0x38
  104. #define UART_TO_MSM(uart_port) ((struct msm_port *) uart_port)
  105. static inline
  106. void msm_write(struct uart_port *port, unsigned int val, unsigned int off)
  107. {
  108. __raw_writel(val, port->membase + off);
  109. }
  110. static inline
  111. unsigned int msm_read(struct uart_port *port, unsigned int off)
  112. {
  113. return __raw_readl(port->membase + off);
  114. }
  115. /*
  116. * Setup the MND registers to use the TCXO clock.
  117. */
  118. static inline void msm_serial_set_mnd_regs_tcxo(struct uart_port *port)
  119. {
  120. msm_write(port, 0x06, UART_MREG);
  121. msm_write(port, 0xF1, UART_NREG);
  122. msm_write(port, 0x0F, UART_DREG);
  123. msm_write(port, 0x1A, UART_MNDREG);
  124. port->uartclk = 1843200;
  125. }
  126. /*
  127. * Setup the MND registers to use the TCXO clock divided by 4.
  128. */
  129. static inline void msm_serial_set_mnd_regs_tcxoby4(struct uart_port *port)
  130. {
  131. msm_write(port, 0x18, UART_MREG);
  132. msm_write(port, 0xF6, UART_NREG);
  133. msm_write(port, 0x0F, UART_DREG);
  134. msm_write(port, 0x0A, UART_MNDREG);
  135. port->uartclk = 1843200;
  136. }
  137. static inline
  138. void msm_serial_set_mnd_regs_from_uartclk(struct uart_port *port)
  139. {
  140. if (port->uartclk == 19200000)
  141. msm_serial_set_mnd_regs_tcxo(port);
  142. else if (port->uartclk == 4800000)
  143. msm_serial_set_mnd_regs_tcxoby4(port);
  144. }
  145. /*
  146. * TROUT has a specific defect that makes it report it's uartclk
  147. * as 19.2Mhz (TCXO) when it's actually 4.8Mhz (TCXO/4). This special
  148. * cases TROUT to use the right clock.
  149. */
  150. #ifdef CONFIG_MACH_TROUT
  151. #define msm_serial_set_mnd_regs msm_serial_set_mnd_regs_tcxoby4
  152. #else
  153. #define msm_serial_set_mnd_regs msm_serial_set_mnd_regs_from_uartclk
  154. #endif
  155. #endif /* __DRIVERS_SERIAL_MSM_SERIAL_H */