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/drivers/net/fddi/defxx.h

http://github.com/mirrors/linux
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   1/*
   2 * File Name:
   3 *   defxx.h
   4 *
   5 * Copyright Information:
   6 *   Copyright Digital Equipment Corporation 1996.
   7 *
   8 *   This software may be used and distributed according to the terms of
   9 *   the GNU General Public License, incorporated herein by reference.
  10 *
  11 * Abstract:
  12 *   Contains all definitions specified by port specification and required
  13 *   by the defxx.c driver.
  14 *
  15 * The original author:
  16 *   LVS	Lawrence V. Stefani <lstefani@yahoo.com>
  17 *
  18 * Maintainers:
  19 *   macro	Maciej W. Rozycki <macro@linux-mips.org>
  20 *
  21 * Modification History:
  22 *		Date		Name	Description
  23 *		16-Aug-96	LVS		Created.
  24 *		09-Sep-96	LVS		Added group_prom field.  Moved read/write I/O
  25 *							macros to DEFXX.C.
  26 *		12-Sep-96	LVS		Removed packet request header pointers.
  27 *		04 Aug 2003	macro		Converted to the DMA API.
  28 *		23 Oct 2006	macro		Big-endian host support.
  29 *		14 Dec 2006	macro		TURBOchannel support.
  30 */
  31
  32#ifndef _DEFXX_H_
  33#define _DEFXX_H_
  34
  35/* Define basic types for unsigned chars, shorts, longs */
  36
  37typedef u8	PI_UINT8;
  38typedef u16	PI_UINT16;
  39typedef u32	PI_UINT32;
  40
  41/* Define general structures */
  42
  43typedef struct							/* 64-bit counter */
  44	{
  45	PI_UINT32  ms;
  46	PI_UINT32  ls;
  47	} PI_CNTR;
  48
  49typedef struct							/* LAN address */
  50	{
  51	PI_UINT32  lwrd_0;
  52	PI_UINT32  lwrd_1;
  53	} PI_LAN_ADDR;
  54
  55typedef struct							/* Station ID address */
  56	{
  57	PI_UINT32  octet_7_4;
  58	PI_UINT32  octet_3_0;
  59	} PI_STATION_ID;
  60
  61
  62/* Define general constants */
  63
  64#define PI_ALIGN_K_DESC_BLK	  			8192	/* Descriptor block boundary		*/
  65#define PI_ALIGN_K_CONS_BLK	  	 		64		/* Consumer block boundary		  	*/
  66#define PI_ALIGN_K_CMD_REQ_BUFF  		128	 	/* Xmt Command que buffer alignment */
  67#define PI_ALIGN_K_CMD_RSP_BUFF	 		128	 	/* Rcv Command que buffer alignment */
  68#define PI_ALIGN_K_UNSOL_BUFF	 		128	 	/* Unsol que buffer alignment	   	*/
  69#define PI_ALIGN_K_XMT_DATA_BUFF 		0	   	/* Xmt data que buffer alignment	*/
  70#define PI_ALIGN_K_RCV_DATA_BUFF 		128	 	/* Rcv que buffer alignment			*/
  71
  72/* Define PHY index values */
  73
  74#define PI_PHY_K_S						0		/* Index to S phy */
  75#define PI_PHY_K_A						0		/* Index to A phy */
  76#define PI_PHY_K_B						1		/* Index to B phy */
  77#define PI_PHY_K_MAX					2		/* Max number of phys */
  78
  79/* Define FMC descriptor fields */
  80
  81#define PI_FMC_DESCR_V_SOP				31
  82#define PI_FMC_DESCR_V_EOP				30
  83#define PI_FMC_DESCR_V_FSC				27
  84#define PI_FMC_DESCR_V_FSB_ERROR		26
  85#define PI_FMC_DESCR_V_FSB_ADDR_RECOG	25
  86#define PI_FMC_DESCR_V_FSB_ADDR_COPIED	24
  87#define PI_FMC_DESCR_V_FSB				22
  88#define PI_FMC_DESCR_V_RCC_FLUSH		21
  89#define PI_FMC_DESCR_V_RCC_CRC			20
  90#define PI_FMC_DESCR_V_RCC_RRR			17
  91#define PI_FMC_DESCR_V_RCC_DD			15
  92#define PI_FMC_DESCR_V_RCC_SS			13
  93#define PI_FMC_DESCR_V_RCC				13
  94#define PI_FMC_DESCR_V_LEN				0
  95
  96#define PI_FMC_DESCR_M_SOP				0x80000000
  97#define PI_FMC_DESCR_M_EOP				0x40000000
  98#define PI_FMC_DESCR_M_FSC				0x38000000
  99#define PI_FMC_DESCR_M_FSB_ERROR		0x04000000
 100#define PI_FMC_DESCR_M_FSB_ADDR_RECOG	0x02000000
 101#define PI_FMC_DESCR_M_FSB_ADDR_COPIED	0x01000000
 102#define PI_FMC_DESCR_M_FSB				0x07C00000
 103#define PI_FMC_DESCR_M_RCC_FLUSH		0x00200000
 104#define PI_FMC_DESCR_M_RCC_CRC			0x00100000
 105#define PI_FMC_DESCR_M_RCC_RRR			0x000E0000
 106#define PI_FMC_DESCR_M_RCC_DD			0x00018000
 107#define PI_FMC_DESCR_M_RCC_SS			0x00006000
 108#define PI_FMC_DESCR_M_RCC				0x003FE000
 109#define PI_FMC_DESCR_M_LEN				0x00001FFF
 110
 111#define PI_FMC_DESCR_K_RCC_FMC_INT_ERR	0x01AA
 112
 113#define PI_FMC_DESCR_K_RRR_SUCCESS		0x00
 114#define PI_FMC_DESCR_K_RRR_SA_MATCH		0x01
 115#define PI_FMC_DESCR_K_RRR_DA_MATCH		0x02
 116#define PI_FMC_DESCR_K_RRR_FMC_ABORT	0x03
 117#define PI_FMC_DESCR_K_RRR_LENGTH_BAD	0x04
 118#define PI_FMC_DESCR_K_RRR_FRAGMENT		0x05
 119#define PI_FMC_DESCR_K_RRR_FORMAT_ERR	0x06
 120#define PI_FMC_DESCR_K_RRR_MAC_RESET	0x07
 121
 122#define PI_FMC_DESCR_K_DD_NO_MATCH		0x0
 123#define PI_FMC_DESCR_K_DD_PROMISCUOUS	0x1
 124#define PI_FMC_DESCR_K_DD_CAM_MATCH		0x2
 125#define PI_FMC_DESCR_K_DD_LOCAL_MATCH	0x3
 126
 127#define PI_FMC_DESCR_K_SS_NO_MATCH		0x0
 128#define PI_FMC_DESCR_K_SS_BRIDGE_MATCH	0x1
 129#define PI_FMC_DESCR_K_SS_NOT_POSSIBLE	0x2
 130#define PI_FMC_DESCR_K_SS_LOCAL_MATCH	0x3
 131
 132/* Define some max buffer sizes */
 133
 134#define PI_CMD_REQ_K_SIZE_MAX			512
 135#define PI_CMD_RSP_K_SIZE_MAX			512
 136#define PI_UNSOL_K_SIZE_MAX				512
 137#define PI_SMT_HOST_K_SIZE_MAX			4608		/* 4 1/2 K */
 138#define PI_RCV_DATA_K_SIZE_MAX			4608		/* 4 1/2 K */
 139#define PI_XMT_DATA_K_SIZE_MAX			4608		/* 4 1/2 K */
 140
 141/* Define adapter states */
 142
 143#define PI_STATE_K_RESET				0
 144#define PI_STATE_K_UPGRADE		  		1
 145#define PI_STATE_K_DMA_UNAVAIL			2
 146#define PI_STATE_K_DMA_AVAIL			3
 147#define PI_STATE_K_LINK_AVAIL			4
 148#define PI_STATE_K_LINK_UNAVAIL	 		5
 149#define PI_STATE_K_HALTED		   		6
 150#define PI_STATE_K_RING_MEMBER			7
 151#define PI_STATE_K_NUMBER				8
 152
 153/* Define codes for command type */
 154
 155#define PI_CMD_K_START					0x00
 156#define PI_CMD_K_FILTERS_SET			0x01
 157#define PI_CMD_K_FILTERS_GET			0x02
 158#define PI_CMD_K_CHARS_SET				0x03
 159#define PI_CMD_K_STATUS_CHARS_GET		0x04
 160#define PI_CMD_K_CNTRS_GET				0x05
 161#define PI_CMD_K_CNTRS_SET				0x06
 162#define PI_CMD_K_ADDR_FILTER_SET		0x07
 163#define PI_CMD_K_ADDR_FILTER_GET		0x08
 164#define PI_CMD_K_ERROR_LOG_CLEAR		0x09
 165#define PI_CMD_K_ERROR_LOG_GET			0x0A
 166#define PI_CMD_K_FDDI_MIB_GET			0x0B
 167#define PI_CMD_K_DEC_EXT_MIB_GET		0x0C
 168#define PI_CMD_K_DEVICE_SPECIFIC_GET	0x0D
 169#define PI_CMD_K_SNMP_SET				0x0E
 170#define PI_CMD_K_UNSOL_TEST				0x0F
 171#define PI_CMD_K_SMT_MIB_GET			0x10
 172#define PI_CMD_K_SMT_MIB_SET			0x11
 173#define PI_CMD_K_MAX					0x11	/* Must match last */
 174
 175/* Define item codes for Chars_Set and Filters_Set commands */
 176
 177#define PI_ITEM_K_EOL					0x00 	/* End-of-Item list 		  */
 178#define PI_ITEM_K_T_REQ					0x01 	/* DECnet T_REQ 			  */
 179#define PI_ITEM_K_TVX					0x02 	/* DECnet TVX 				  */
 180#define PI_ITEM_K_RESTRICTED_TOKEN		0x03 	/* DECnet Restricted Token 	  */
 181#define PI_ITEM_K_LEM_THRESHOLD			0x04 	/* DECnet LEM Threshold 	  */
 182#define PI_ITEM_K_RING_PURGER			0x05 	/* DECnet Ring Purger Enable  */
 183#define PI_ITEM_K_CNTR_INTERVAL			0x06 	/* Chars_Set 				  */
 184#define PI_ITEM_K_IND_GROUP_PROM		0x07 	/* Filters_Set 				  */
 185#define PI_ITEM_K_GROUP_PROM			0x08 	/* Filters_Set 				  */
 186#define PI_ITEM_K_BROADCAST				0x09 	/* Filters_Set 				  */
 187#define PI_ITEM_K_SMT_PROM				0x0A 	/* Filters_Set				  */
 188#define PI_ITEM_K_SMT_USER				0x0B 	/* Filters_Set 				  */
 189#define PI_ITEM_K_RESERVED				0x0C 	/* Filters_Set 				  */
 190#define PI_ITEM_K_IMPLEMENTOR			0x0D 	/* Filters_Set 				  */
 191#define PI_ITEM_K_LOOPBACK_MODE			0x0E 	/* Chars_Set 				  */
 192#define PI_ITEM_K_CONFIG_POLICY			0x10 	/* SMTConfigPolicy 			  */
 193#define PI_ITEM_K_CON_POLICY			0x11 	/* SMTConnectionPolicy 		  */
 194#define PI_ITEM_K_T_NOTIFY				0x12 	/* SMTTNotify 				  */
 195#define PI_ITEM_K_STATION_ACTION		0x13 	/* SMTStationAction			  */
 196#define PI_ITEM_K_MAC_PATHS_REQ	   		0x15 	/* MACPathsRequested 		  */
 197#define PI_ITEM_K_MAC_ACTION			0x17 	/* MACAction 				  */
 198#define PI_ITEM_K_CON_POLICIES			0x18 	/* PORTConnectionPolicies	  */
 199#define PI_ITEM_K_PORT_PATHS_REQ		0x19 	/* PORTPathsRequested 		  */
 200#define PI_ITEM_K_MAC_LOOP_TIME			0x1A 	/* PORTMACLoopTime 			  */
 201#define PI_ITEM_K_TB_MAX				0x1B 	/* PORTTBMax 				  */
 202#define PI_ITEM_K_LER_CUTOFF			0x1C 	/* PORTLerCutoff 			  */
 203#define PI_ITEM_K_LER_ALARM				0x1D 	/* PORTLerAlarm 			  */
 204#define PI_ITEM_K_PORT_ACTION			0x1E 	/* PORTAction 				  */
 205#define PI_ITEM_K_FLUSH_TIME			0x20 	/* Chars_Set 				  */
 206#define PI_ITEM_K_MAC_T_REQ				0x29 	/* MACTReq 					  */
 207#define PI_ITEM_K_EMAC_RING_PURGER		0x2A 	/* eMACRingPurgerEnable		  */
 208#define PI_ITEM_K_EMAC_RTOKEN_TIMEOUT	0x2B 	/* eMACRestrictedTokenTimeout */
 209#define PI_ITEM_K_FDX_ENB_DIS			0x2C 	/* eFDXEnable				  */
 210#define PI_ITEM_K_MAX					0x2C 	/* Must equal high item		  */
 211
 212/* Values for some of the items */
 213
 214#define PI_K_FALSE						0	   /* Generic false */
 215#define PI_K_TRUE						1	   /* Generic true  */
 216
 217#define PI_SNMP_K_TRUE					1	   /* SNMP true/false values */
 218#define PI_SNMP_K_FALSE					2
 219
 220#define PI_FSTATE_K_BLOCK				0	   /* Filter State */
 221#define PI_FSTATE_K_PASS				1
 222
 223/* Define command return codes */
 224
 225#define PI_RSP_K_SUCCESS				0x00
 226#define PI_RSP_K_FAILURE				0x01
 227#define PI_RSP_K_WARNING				0x02
 228#define PI_RSP_K_LOOP_MODE_BAD			0x03
 229#define PI_RSP_K_ITEM_CODE_BAD			0x04
 230#define PI_RSP_K_TVX_BAD				0x05
 231#define PI_RSP_K_TREQ_BAD				0x06
 232#define PI_RSP_K_TOKEN_BAD				0x07
 233#define PI_RSP_K_NO_EOL					0x0C
 234#define PI_RSP_K_FILTER_STATE_BAD		0x0D
 235#define PI_RSP_K_CMD_TYPE_BAD			0x0E
 236#define PI_RSP_K_ADAPTER_STATE_BAD		0x0F
 237#define PI_RSP_K_RING_PURGER_BAD		0x10
 238#define PI_RSP_K_LEM_THRESHOLD_BAD		0x11
 239#define PI_RSP_K_LOOP_NOT_SUPPORTED		0x12
 240#define PI_RSP_K_FLUSH_TIME_BAD			0x13
 241#define PI_RSP_K_NOT_IMPLEMENTED		0x14
 242#define PI_RSP_K_CONFIG_POLICY_BAD		0x15
 243#define PI_RSP_K_STATION_ACTION_BAD		0x16
 244#define PI_RSP_K_MAC_ACTION_BAD			0x17
 245#define PI_RSP_K_CON_POLICIES_BAD		0x18
 246#define PI_RSP_K_MAC_LOOP_TIME_BAD		0x19
 247#define PI_RSP_K_TB_MAX_BAD				0x1A
 248#define PI_RSP_K_LER_CUTOFF_BAD			0x1B
 249#define PI_RSP_K_LER_ALARM_BAD			0x1C
 250#define PI_RSP_K_MAC_PATHS_REQ_BAD		0x1D
 251#define PI_RSP_K_MAC_T_REQ_BAD			0x1E
 252#define PI_RSP_K_EMAC_RING_PURGER_BAD	0x1F
 253#define PI_RSP_K_EMAC_RTOKEN_TIME_BAD	0x20
 254#define PI_RSP_K_NO_SUCH_ENTRY			0x21
 255#define PI_RSP_K_T_NOTIFY_BAD			0x22
 256#define PI_RSP_K_TR_MAX_EXP_BAD			0x23
 257#define PI_RSP_K_MAC_FRM_ERR_THR_BAD	0x24
 258#define PI_RSP_K_MAX_T_REQ_BAD			0x25
 259#define PI_RSP_K_FDX_ENB_DIS_BAD		0x26
 260#define PI_RSP_K_ITEM_INDEX_BAD			0x27
 261#define PI_RSP_K_PORT_ACTION_BAD		0x28
 262
 263/* Commonly used structures */
 264
 265typedef struct									/* Item list */
 266	{
 267	PI_UINT32  item_code;
 268	PI_UINT32  value;
 269	} PI_ITEM_LIST;
 270
 271typedef struct									/* Response header */
 272	{
 273	PI_UINT32  reserved;
 274	PI_UINT32  cmd_type;
 275	PI_UINT32  status;
 276	} PI_RSP_HEADER;
 277
 278
 279/* Start Command */
 280
 281typedef struct
 282	{
 283	PI_UINT32  cmd_type;
 284	} PI_CMD_START_REQ;
 285
 286/* Start Response */
 287
 288typedef struct
 289	{
 290	PI_RSP_HEADER   header;
 291	} PI_CMD_START_RSP;
 292
 293/* Filters_Set Request */
 294
 295#define PI_CMD_FILTERS_SET_K_ITEMS_MAX  63		/* Fits in a 512 byte buffer */
 296
 297typedef struct
 298	{
 299	PI_UINT32		cmd_type;
 300	PI_ITEM_LIST	item[PI_CMD_FILTERS_SET_K_ITEMS_MAX];
 301	} PI_CMD_FILTERS_SET_REQ;
 302
 303/* Filters_Set Response */
 304
 305typedef struct
 306	{
 307	PI_RSP_HEADER   header;
 308	} PI_CMD_FILTERS_SET_RSP;
 309
 310/* Filters_Get Request */
 311
 312typedef struct
 313	{
 314	PI_UINT32		cmd_type;
 315	} PI_CMD_FILTERS_GET_REQ;
 316
 317/* Filters_Get Response */
 318
 319typedef struct
 320	{
 321	PI_RSP_HEADER   header;
 322	PI_UINT32		ind_group_prom;
 323	PI_UINT32		group_prom;
 324	PI_UINT32		broadcast_all;
 325	PI_UINT32		smt_all;
 326	PI_UINT32		smt_user;
 327	PI_UINT32		reserved_all;
 328	PI_UINT32		implementor_all;
 329	} PI_CMD_FILTERS_GET_RSP;
 330
 331
 332/* Chars_Set Request */
 333
 334#define PI_CMD_CHARS_SET_K_ITEMS_MAX 42		/* Fits in a 512 byte buffer */
 335
 336typedef struct
 337	{
 338	PI_UINT32		cmd_type;
 339	struct							  		/* Item list */
 340		{
 341		PI_UINT32	item_code;
 342		PI_UINT32	value;
 343		PI_UINT32	item_index;
 344		} item[PI_CMD_CHARS_SET_K_ITEMS_MAX];
 345	} PI_CMD_CHARS_SET_REQ;
 346
 347/* Chars_Set Response */
 348
 349typedef struct
 350	{
 351	PI_RSP_HEADER   header;
 352	} PI_CMD_CHARS_SET_RSP;
 353
 354
 355/* SNMP_Set Request */
 356
 357#define PI_CMD_SNMP_SET_K_ITEMS_MAX 42	   	/* Fits in a 512 byte buffer */
 358
 359typedef struct
 360	{
 361	PI_UINT32		cmd_type;
 362	struct							   		/* Item list */
 363		{
 364		PI_UINT32	item_code;
 365		PI_UINT32	value;
 366		PI_UINT32	item_index;
 367		} item[PI_CMD_SNMP_SET_K_ITEMS_MAX];
 368	} PI_CMD_SNMP_SET_REQ;
 369
 370/* SNMP_Set Response */
 371
 372typedef struct
 373	{
 374	PI_RSP_HEADER   header;
 375	} PI_CMD_SNMP_SET_RSP;
 376
 377
 378/* SMT_MIB_Set Request */
 379
 380#define PI_CMD_SMT_MIB_SET_K_ITEMS_MAX 42	/* Max number of items */
 381
 382typedef struct
 383	{
 384	PI_UINT32	cmd_type;
 385	struct
 386		{
 387		PI_UINT32	item_code;
 388		PI_UINT32	value;
 389		PI_UINT32	item_index;
 390		} item[PI_CMD_SMT_MIB_SET_K_ITEMS_MAX];
 391	} PI_CMD_SMT_MIB_SET_REQ;
 392
 393/* SMT_MIB_Set Response */
 394
 395typedef struct
 396	{
 397	PI_RSP_HEADER   header;
 398	} PI_CMD_SMT_MIB_SET_RSP;
 399
 400/* SMT_MIB_Get Request */
 401
 402typedef struct
 403	{
 404	PI_UINT32  cmd_type;
 405	} PI_CMD_SMT_MIB_GET_REQ;
 406
 407/* SMT_MIB_Get Response */
 408
 409typedef struct						  /* Refer to ANSI FDDI SMT Rev. 7.3 */
 410	{
 411	PI_RSP_HEADER  header;
 412
 413	/* SMT GROUP */
 414
 415	PI_STATION_ID  	smt_station_id;
 416	PI_UINT32 		smt_op_version_id;
 417	PI_UINT32	   	smt_hi_version_id;
 418	PI_UINT32	   	smt_lo_version_id;
 419	PI_UINT32	   	smt_user_data[8];
 420	PI_UINT32	   	smt_mib_version_id;
 421	PI_UINT32	   	smt_mac_ct;
 422	PI_UINT32	   	smt_non_master_ct;
 423	PI_UINT32	   	smt_master_ct;
 424	PI_UINT32	   	smt_available_paths;
 425	PI_UINT32	   	smt_config_capabilities;
 426	PI_UINT32	   	smt_config_policy;
 427	PI_UINT32	   	smt_connection_policy;
 428	PI_UINT32	   	smt_t_notify;
 429	PI_UINT32	   	smt_stat_rpt_policy;
 430	PI_UINT32	   	smt_trace_max_expiration;
 431	PI_UINT32	   	smt_bypass_present;
 432	PI_UINT32	  	smt_ecm_state;
 433	PI_UINT32	   	smt_cf_state;
 434	PI_UINT32	   	smt_remote_disconnect_flag;
 435	PI_UINT32	   	smt_station_status;
 436	PI_UINT32	   	smt_peer_wrap_flag;
 437	PI_CNTR	   		smt_msg_time_stamp;
 438	PI_CNTR	  		smt_transition_time_stamp;
 439
 440	/* MAC GROUP */
 441
 442	PI_UINT32		mac_frame_status_functions;
 443	PI_UINT32		mac_t_max_capability;
 444	PI_UINT32		mac_tvx_capability;
 445	PI_UINT32		mac_available_paths;
 446	PI_UINT32		mac_current_path;
 447	PI_LAN_ADDR		mac_upstream_nbr;
 448	PI_LAN_ADDR		mac_downstream_nbr;
 449	PI_LAN_ADDR		mac_old_upstream_nbr;
 450	PI_LAN_ADDR		mac_old_downstream_nbr;
 451	PI_UINT32	   	mac_dup_address_test;
 452	PI_UINT32	   	mac_requested_paths;
 453	PI_UINT32	   	mac_downstream_port_type;
 454	PI_LAN_ADDR		mac_smt_address;
 455	PI_UINT32		mac_t_req;
 456	PI_UINT32		mac_t_neg;
 457	PI_UINT32		mac_t_max;
 458	PI_UINT32		mac_tvx_value;
 459	PI_UINT32		mac_frame_error_threshold;
 460	PI_UINT32		mac_frame_error_ratio;
 461	PI_UINT32		mac_rmt_state;
 462	PI_UINT32		mac_da_flag;
 463	PI_UINT32		mac_unda_flag;
 464	PI_UINT32		mac_frame_error_flag;
 465	PI_UINT32		mac_ma_unitdata_available;
 466	PI_UINT32		mac_hardware_present;
 467	PI_UINT32		mac_ma_unitdata_enable;
 468
 469	/* PATH GROUP */
 470
 471	PI_UINT32		path_configuration[8];
 472	PI_UINT32		path_tvx_lower_bound;
 473	PI_UINT32		path_t_max_lower_bound;
 474	PI_UINT32		path_max_t_req;
 475
 476	/* PORT GROUP */
 477
 478	PI_UINT32		port_my_type[PI_PHY_K_MAX];
 479	PI_UINT32		port_neighbor_type[PI_PHY_K_MAX];
 480	PI_UINT32		port_connection_policies[PI_PHY_K_MAX];
 481	PI_UINT32		port_mac_indicated[PI_PHY_K_MAX];
 482	PI_UINT32		port_current_path[PI_PHY_K_MAX];
 483	PI_UINT32		port_requested_paths[PI_PHY_K_MAX];
 484	PI_UINT32		port_mac_placement[PI_PHY_K_MAX];
 485	PI_UINT32		port_available_paths[PI_PHY_K_MAX];
 486	PI_UINT32		port_pmd_class[PI_PHY_K_MAX];
 487	PI_UINT32		port_connection_capabilities[PI_PHY_K_MAX];
 488	PI_UINT32		port_bs_flag[PI_PHY_K_MAX];
 489	PI_UINT32		port_ler_estimate[PI_PHY_K_MAX];
 490	PI_UINT32		port_ler_cutoff[PI_PHY_K_MAX];
 491	PI_UINT32		port_ler_alarm[PI_PHY_K_MAX];
 492	PI_UINT32		port_connect_state[PI_PHY_K_MAX];
 493	PI_UINT32		port_pcm_state[PI_PHY_K_MAX];
 494	PI_UINT32		port_pc_withhold[PI_PHY_K_MAX];
 495	PI_UINT32		port_ler_flag[PI_PHY_K_MAX];
 496	PI_UINT32		port_hardware_present[PI_PHY_K_MAX];
 497
 498	/* GROUP for things that were added later, so must be at the end. */
 499
 500	PI_CNTR	   		path_ring_latency;
 501
 502	} PI_CMD_SMT_MIB_GET_RSP;
 503
 504
 505/*
 506 *  Item and group code definitions for SMT 7.3 mandatory objects.  These
 507 *  definitions are to be used as appropriate in SMT_MIB_SET commands and
 508 *  certain host-sent SMT frames such as PMF Get and Set requests.  The
 509 *  codes have been taken from the MIB summary section of ANSI SMT 7.3.
 510 */
 511
 512#define PI_GRP_K_SMT_STATION_ID			0x100A
 513#define PI_ITEM_K_SMT_STATION_ID		0x100B
 514#define PI_ITEM_K_SMT_OP_VERS_ID		0x100D
 515#define PI_ITEM_K_SMT_HI_VERS_ID		0x100E
 516#define PI_ITEM_K_SMT_LO_VERS_ID		0x100F
 517#define PI_ITEM_K_SMT_USER_DATA			0x1011
 518#define PI_ITEM_K_SMT_MIB_VERS_ID	  	0x1012
 519
 520#define PI_GRP_K_SMT_STATION_CONFIG		0x1014
 521#define PI_ITEM_K_SMT_MAC_CT			0x1015
 522#define PI_ITEM_K_SMT_NON_MASTER_CT		0x1016
 523#define PI_ITEM_K_SMT_MASTER_CT			0x1017
 524#define PI_ITEM_K_SMT_AVAIL_PATHS		0x1018
 525#define PI_ITEM_K_SMT_CONFIG_CAPS		0x1019
 526#define PI_ITEM_K_SMT_CONFIG_POL		0x101A
 527#define PI_ITEM_K_SMT_CONN_POL			0x101B
 528#define PI_ITEM_K_SMT_T_NOTIFY			0x101D
 529#define PI_ITEM_K_SMT_STAT_POL			0x101E
 530#define PI_ITEM_K_SMT_TR_MAX_EXP		0x101F
 531#define PI_ITEM_K_SMT_PORT_INDEXES		0x1020
 532#define PI_ITEM_K_SMT_MAC_INDEXES		0x1021
 533#define PI_ITEM_K_SMT_BYPASS_PRESENT	0x1022
 534
 535#define PI_GRP_K_SMT_STATUS				0x1028
 536#define PI_ITEM_K_SMT_ECM_STATE			0x1029
 537#define PI_ITEM_K_SMT_CF_STATE		 	0x102A
 538#define PI_ITEM_K_SMT_REM_DISC_FLAG		0x102C
 539#define PI_ITEM_K_SMT_STATION_STATUS	0x102D
 540#define PI_ITEM_K_SMT_PEER_WRAP_FLAG	0x102E
 541
 542#define PI_GRP_K_SMT_MIB_OPERATION	 	0x1032
 543#define PI_ITEM_K_SMT_MSG_TIME_STAMP 	0x1033
 544#define PI_ITEM_K_SMT_TRN_TIME_STAMP 	0x1034
 545
 546#define PI_ITEM_K_SMT_STATION_ACT		0x103C
 547
 548#define PI_GRP_K_MAC_CAPABILITIES	  	0x200A
 549#define PI_ITEM_K_MAC_FRM_STAT_FUNC		0x200B
 550#define PI_ITEM_K_MAC_T_MAX_CAP			0x200D
 551#define PI_ITEM_K_MAC_TVX_CAP		  	0x200E
 552
 553#define PI_GRP_K_MAC_CONFIG				0x2014
 554#define PI_ITEM_K_MAC_AVAIL_PATHS	  	0x2016
 555#define PI_ITEM_K_MAC_CURRENT_PATH	 	0x2017
 556#define PI_ITEM_K_MAC_UP_NBR			0x2018
 557#define PI_ITEM_K_MAC_DOWN_NBR			0x2019
 558#define PI_ITEM_K_MAC_OLD_UP_NBR	 	0x201A
 559#define PI_ITEM_K_MAC_OLD_DOWN_NBR	 	0x201B
 560#define PI_ITEM_K_MAC_DUP_ADDR_TEST		0x201D
 561#define PI_ITEM_K_MAC_REQ_PATHS			0x2020
 562#define PI_ITEM_K_MAC_DOWN_PORT_TYPE   	0x2021
 563#define PI_ITEM_K_MAC_INDEX				0x2022
 564
 565#define PI_GRP_K_MAC_ADDRESS			0x2028
 566#define PI_ITEM_K_MAC_SMT_ADDRESS		0x2029
 567
 568#define PI_GRP_K_MAC_OPERATION			0x2032
 569#define PI_ITEM_K_MAC_TREQ				0x2033
 570#define PI_ITEM_K_MAC_TNEG				0x2034
 571#define PI_ITEM_K_MAC_TMAX				0x2035
 572#define PI_ITEM_K_MAC_TVX_VALUE			0x2036
 573
 574#define PI_GRP_K_MAC_COUNTERS			0x2046
 575#define PI_ITEM_K_MAC_FRAME_CT			0x2047
 576#define PI_ITEM_K_MAC_COPIED_CT			0x2048
 577#define PI_ITEM_K_MAC_TRANSMIT_CT		0x2049
 578#define PI_ITEM_K_MAC_ERROR_CT			0x2051
 579#define PI_ITEM_K_MAC_LOST_CT			0x2052
 580
 581#define PI_GRP_K_MAC_FRM_ERR_COND		0x205A
 582#define PI_ITEM_K_MAC_FRM_ERR_THR		0x205F
 583#define PI_ITEM_K_MAC_FRM_ERR_RAT		0x2060
 584
 585#define PI_GRP_K_MAC_STATUS				0x206E
 586#define PI_ITEM_K_MAC_RMT_STATE			0x206F
 587#define PI_ITEM_K_MAC_DA_FLAG			0x2070
 588#define PI_ITEM_K_MAC_UNDA_FLAG			0x2071
 589#define PI_ITEM_K_MAC_FRM_ERR_FLAG		0x2072
 590#define PI_ITEM_K_MAC_MA_UNIT_AVAIL		0x2074
 591#define PI_ITEM_K_MAC_HW_PRESENT		0x2075
 592#define PI_ITEM_K_MAC_MA_UNIT_ENAB		0x2076
 593
 594#define PI_GRP_K_PATH_CONFIG			0x320A
 595#define PI_ITEM_K_PATH_INDEX			0x320B
 596#define PI_ITEM_K_PATH_CONFIGURATION 	0x3212
 597#define PI_ITEM_K_PATH_TVX_LB			0x3215
 598#define PI_ITEM_K_PATH_T_MAX_LB			0x3216
 599#define PI_ITEM_K_PATH_MAX_T_REQ		0x3217
 600
 601#define PI_GRP_K_PORT_CONFIG			0x400A
 602#define PI_ITEM_K_PORT_MY_TYPE			0x400C
 603#define PI_ITEM_K_PORT_NBR_TYPE			0x400D
 604#define PI_ITEM_K_PORT_CONN_POLS		0x400E
 605#define PI_ITEM_K_PORT_MAC_INDICATED  	0x400F
 606#define PI_ITEM_K_PORT_CURRENT_PATH		0x4010
 607#define PI_ITEM_K_PORT_REQ_PATHS		0x4011
 608#define PI_ITEM_K_PORT_MAC_PLACEMENT 	0x4012
 609#define PI_ITEM_K_PORT_AVAIL_PATHS		0x4013
 610#define PI_ITEM_K_PORT_PMD_CLASS		0x4016
 611#define PI_ITEM_K_PORT_CONN_CAPS		0x4017
 612#define PI_ITEM_K_PORT_INDEX			0x401D
 613
 614#define PI_GRP_K_PORT_OPERATION			0x401E
 615#define PI_ITEM_K_PORT_BS_FLAG		 	0x4021
 616
 617#define PI_GRP_K_PORT_ERR_CNTRS			0x4028
 618#define PI_ITEM_K_PORT_LCT_FAIL_CT	 	0x402A
 619
 620#define PI_GRP_K_PORT_LER			  	0x4032
 621#define PI_ITEM_K_PORT_LER_ESTIMATE		0x4033
 622#define PI_ITEM_K_PORT_LEM_REJ_CT		0x4034
 623#define PI_ITEM_K_PORT_LEM_CT			0x4035
 624#define PI_ITEM_K_PORT_LER_CUTOFF		0x403A
 625#define PI_ITEM_K_PORT_LER_ALARM		0x403B
 626
 627#define PI_GRP_K_PORT_STATUS			0x403C
 628#define PI_ITEM_K_PORT_CONNECT_STATE	0x403D
 629#define PI_ITEM_K_PORT_PCM_STATE		0x403E
 630#define PI_ITEM_K_PORT_PC_WITHHOLD		0x403F
 631#define PI_ITEM_K_PORT_LER_FLAG			0x4040
 632#define PI_ITEM_K_PORT_HW_PRESENT		0x4041
 633
 634#define PI_ITEM_K_PORT_ACT				0x4046
 635
 636/* Addr_Filter_Set Request */
 637
 638#define PI_CMD_ADDR_FILTER_K_SIZE   62
 639
 640typedef struct
 641	{
 642	PI_UINT32	cmd_type;
 643	PI_LAN_ADDR	entry[PI_CMD_ADDR_FILTER_K_SIZE];
 644	} PI_CMD_ADDR_FILTER_SET_REQ;
 645
 646/* Addr_Filter_Set Response */
 647
 648typedef struct
 649	{
 650	PI_RSP_HEADER   header;
 651	} PI_CMD_ADDR_FILTER_SET_RSP;
 652
 653/* Addr_Filter_Get Request */
 654
 655typedef struct
 656	{
 657	PI_UINT32	cmd_type;
 658	} PI_CMD_ADDR_FILTER_GET_REQ;
 659
 660/* Addr_Filter_Get Response */
 661
 662typedef struct
 663	{
 664	PI_RSP_HEADER   header;
 665	PI_LAN_ADDR		entry[PI_CMD_ADDR_FILTER_K_SIZE];
 666	} PI_CMD_ADDR_FILTER_GET_RSP;
 667
 668/* Status_Chars_Get Request */
 669
 670typedef struct
 671	{
 672	PI_UINT32  cmd_type;
 673	} PI_CMD_STATUS_CHARS_GET_REQ;
 674
 675/* Status_Chars_Get Response */
 676
 677typedef struct
 678	{
 679	PI_RSP_HEADER   header;
 680	PI_STATION_ID   station_id;						/* Station */
 681	PI_UINT32		station_type;
 682	PI_UINT32		smt_ver_id;
 683	PI_UINT32		smt_ver_id_max;
 684	PI_UINT32		smt_ver_id_min;
 685	PI_UINT32		station_state;
 686	PI_LAN_ADDR		link_addr;						/* Link */
 687	PI_UINT32		t_req;
 688	PI_UINT32		tvx;
 689	PI_UINT32		token_timeout;
 690	PI_UINT32		purger_enb;
 691	PI_UINT32		link_state;
 692	PI_UINT32		tneg;
 693	PI_UINT32		dup_addr_flag;
 694	PI_LAN_ADDR		una;
 695	PI_LAN_ADDR		una_old;
 696	PI_UINT32		un_dup_addr_flag;
 697	PI_LAN_ADDR		dna;
 698	PI_LAN_ADDR		dna_old;
 699	PI_UINT32		purger_state;
 700	PI_UINT32		fci_mode;
 701	PI_UINT32		error_reason;
 702	PI_UINT32		loopback;
 703	PI_UINT32		ring_latency;
 704	PI_LAN_ADDR		last_dir_beacon_sa;
 705	PI_LAN_ADDR		last_dir_beacon_una;
 706	PI_UINT32		phy_type[PI_PHY_K_MAX];			/* Phy */
 707	PI_UINT32		pmd_type[PI_PHY_K_MAX];
 708	PI_UINT32		lem_threshold[PI_PHY_K_MAX];
 709	PI_UINT32		phy_state[PI_PHY_K_MAX];
 710	PI_UINT32		nbor_phy_type[PI_PHY_K_MAX];
 711	PI_UINT32		link_error_est[PI_PHY_K_MAX];
 712	PI_UINT32		broken_reason[PI_PHY_K_MAX];
 713	PI_UINT32		reject_reason[PI_PHY_K_MAX];
 714	PI_UINT32		cntr_interval;					/* Miscellaneous */
 715	PI_UINT32		module_rev;
 716	PI_UINT32		firmware_rev;
 717	PI_UINT32		mop_device_type;
 718	PI_UINT32		phy_led[PI_PHY_K_MAX];
 719	PI_UINT32		flush_time;
 720	} PI_CMD_STATUS_CHARS_GET_RSP;
 721
 722/* FDDI_MIB_Get Request */
 723
 724typedef struct
 725	{
 726	PI_UINT32  cmd_type;
 727	} PI_CMD_FDDI_MIB_GET_REQ;
 728
 729/* FDDI_MIB_Get Response */
 730
 731typedef struct
 732	{
 733	PI_RSP_HEADER   header;
 734
 735	/* SMT GROUP */
 736
 737	PI_STATION_ID   smt_station_id;
 738	PI_UINT32		smt_op_version_id;
 739	PI_UINT32		smt_hi_version_id;
 740	PI_UINT32		smt_lo_version_id;
 741	PI_UINT32		smt_mac_ct;
 742	PI_UINT32		smt_non_master_ct;
 743	PI_UINT32		smt_master_ct;
 744	PI_UINT32		smt_paths_available;
 745	PI_UINT32		smt_config_capabilities;
 746	PI_UINT32		smt_config_policy;
 747	PI_UINT32		smt_connection_policy;
 748	PI_UINT32		smt_t_notify;
 749	PI_UINT32		smt_status_reporting;
 750	PI_UINT32		smt_ecm_state;
 751	PI_UINT32		smt_cf_state;
 752	PI_UINT32		smt_hold_state;
 753	PI_UINT32		smt_remote_disconnect_flag;
 754	PI_UINT32		smt_station_action;
 755
 756	/* MAC GROUP */
 757
 758	PI_UINT32		mac_frame_status_capabilities;
 759	PI_UINT32		mac_t_max_greatest_lower_bound;
 760	PI_UINT32		mac_tvx_greatest_lower_bound;
 761	PI_UINT32		mac_paths_available;
 762	PI_UINT32		mac_current_path;
 763	PI_LAN_ADDR		mac_upstream_nbr;
 764	PI_LAN_ADDR		mac_old_upstream_nbr;
 765	PI_UINT32		mac_dup_addr_test;
 766	PI_UINT32		mac_paths_requested;
 767	PI_UINT32		mac_downstream_port_type;
 768	PI_LAN_ADDR		mac_smt_address;
 769	PI_UINT32		mac_t_req;
 770	PI_UINT32		mac_t_neg;
 771	PI_UINT32		mac_t_max;
 772	PI_UINT32		mac_tvx_value;
 773	PI_UINT32		mac_t_min;
 774	PI_UINT32		mac_current_frame_status;
 775	/*			  	mac_frame_cts 			*/
 776	/* 				mac_error_cts 			*/
 777	/* 		   		mac_lost_cts 			*/
 778	PI_UINT32		mac_frame_error_threshold;
 779	PI_UINT32		mac_frame_error_ratio;
 780	PI_UINT32		mac_rmt_state;
 781	PI_UINT32		mac_da_flag;
 782	PI_UINT32		mac_una_da_flag;
 783	PI_UINT32		mac_frame_condition;
 784	PI_UINT32		mac_chip_set;
 785	PI_UINT32		mac_action;
 786
 787	/* PATH GROUP => Does not need to be implemented */
 788
 789	/* PORT GROUP */
 790
 791	PI_UINT32		port_pc_type[PI_PHY_K_MAX];
 792	PI_UINT32		port_pc_neighbor[PI_PHY_K_MAX];
 793	PI_UINT32		port_connection_policies[PI_PHY_K_MAX];
 794	PI_UINT32		port_remote_mac_indicated[PI_PHY_K_MAX];
 795	PI_UINT32		port_ce_state[PI_PHY_K_MAX];
 796	PI_UINT32		port_paths_requested[PI_PHY_K_MAX];
 797	PI_UINT32		port_mac_placement[PI_PHY_K_MAX];
 798	PI_UINT32		port_available_paths[PI_PHY_K_MAX];
 799	PI_UINT32		port_mac_loop_time[PI_PHY_K_MAX];
 800	PI_UINT32		port_tb_max[PI_PHY_K_MAX];
 801	PI_UINT32		port_bs_flag[PI_PHY_K_MAX];
 802	/*				port_lct_fail_cts[PI_PHY_K_MAX];	*/
 803	PI_UINT32		port_ler_estimate[PI_PHY_K_MAX];
 804	/*				port_lem_reject_cts[PI_PHY_K_MAX];	*/
 805	/*				port_lem_cts[PI_PHY_K_MAX];		*/
 806	PI_UINT32		port_ler_cutoff[PI_PHY_K_MAX];
 807	PI_UINT32		port_ler_alarm[PI_PHY_K_MAX];
 808	PI_UINT32		port_connect_state[PI_PHY_K_MAX];
 809	PI_UINT32		port_pcm_state[PI_PHY_K_MAX];
 810	PI_UINT32		port_pc_withhold[PI_PHY_K_MAX];
 811	PI_UINT32		port_ler_condition[PI_PHY_K_MAX];
 812	PI_UINT32		port_chip_set[PI_PHY_K_MAX];
 813	PI_UINT32		port_action[PI_PHY_K_MAX];
 814
 815	/* ATTACHMENT GROUP */
 816
 817	PI_UINT32		attachment_class;
 818	PI_UINT32		attachment_ob_present;
 819	PI_UINT32		attachment_imax_expiration;
 820	PI_UINT32		attachment_inserted_status;
 821	PI_UINT32		attachment_insert_policy;
 822
 823	/* CHIP SET GROUP => Does not need to be implemented */
 824
 825	} PI_CMD_FDDI_MIB_GET_RSP;
 826
 827/* DEC_Ext_MIB_Get Request */
 828
 829typedef struct
 830	{
 831	PI_UINT32  cmd_type;
 832	} PI_CMD_DEC_EXT_MIB_GET_REQ;
 833
 834/* DEC_Ext_MIB_Get (efddi and efdx groups only) Response */
 835
 836typedef struct
 837	{
 838	PI_RSP_HEADER   header;
 839
 840	/* SMT GROUP */
 841
 842	PI_UINT32		esmt_station_type;
 843
 844	/* MAC GROUP */
 845
 846	PI_UINT32		emac_link_state;
 847	PI_UINT32		emac_ring_purger_state;
 848	PI_UINT32		emac_ring_purger_enable;
 849	PI_UINT32		emac_frame_strip_mode;
 850	PI_UINT32		emac_ring_error_reason;
 851	PI_UINT32		emac_up_nbr_dup_addr_flag;
 852	PI_UINT32		emac_restricted_token_timeout;
 853
 854	/* PORT GROUP */
 855
 856	PI_UINT32		eport_pmd_type[PI_PHY_K_MAX];
 857	PI_UINT32		eport_phy_state[PI_PHY_K_MAX];
 858	PI_UINT32		eport_reject_reason[PI_PHY_K_MAX];
 859
 860	/* FDX (Full-Duplex) GROUP */
 861
 862	PI_UINT32		efdx_enable;				/* Valid only in SMT 7.3 */
 863	PI_UINT32		efdx_op;					/* Valid only in SMT 7.3 */
 864	PI_UINT32		efdx_state;					/* Valid only in SMT 7.3 */
 865
 866	} PI_CMD_DEC_EXT_MIB_GET_RSP;
 867
 868typedef struct
 869	{
 870	PI_CNTR		traces_rcvd;					/* Station */
 871	PI_CNTR		frame_cnt;						/* Link */
 872	PI_CNTR		error_cnt;
 873	PI_CNTR		lost_cnt;
 874	PI_CNTR		octets_rcvd;
 875	PI_CNTR		octets_sent;
 876	PI_CNTR		pdus_rcvd;
 877	PI_CNTR		pdus_sent;
 878	PI_CNTR		mcast_octets_rcvd;
 879	PI_CNTR		mcast_octets_sent;
 880	PI_CNTR		mcast_pdus_rcvd;
 881	PI_CNTR		mcast_pdus_sent;
 882	PI_CNTR		xmt_underruns;
 883	PI_CNTR		xmt_failures;
 884	PI_CNTR		block_check_errors;
 885	PI_CNTR		frame_status_errors;
 886	PI_CNTR		pdu_length_errors;
 887	PI_CNTR		rcv_overruns;
 888	PI_CNTR		user_buff_unavailable;
 889	PI_CNTR		inits_initiated;
 890	PI_CNTR		inits_rcvd;
 891	PI_CNTR		beacons_initiated;
 892	PI_CNTR		dup_addrs;
 893	PI_CNTR		dup_tokens;
 894	PI_CNTR		purge_errors;
 895	PI_CNTR		fci_strip_errors;
 896	PI_CNTR		traces_initiated;
 897	PI_CNTR		directed_beacons_rcvd;
 898	PI_CNTR		emac_frame_alignment_errors;
 899	PI_CNTR		ebuff_errors[PI_PHY_K_MAX];		/* Phy */
 900	PI_CNTR		lct_rejects[PI_PHY_K_MAX];
 901	PI_CNTR		lem_rejects[PI_PHY_K_MAX];
 902	PI_CNTR		link_errors[PI_PHY_K_MAX];
 903	PI_CNTR		connections[PI_PHY_K_MAX];
 904	PI_CNTR		copied_cnt;			 			/* Valid only if using SMT 7.3 */
 905	PI_CNTR		transmit_cnt;					/* Valid only if using SMT 7.3 */
 906	PI_CNTR		tokens;
 907	} PI_CNTR_BLK;
 908
 909/* Counters_Get Request */
 910
 911typedef struct
 912	{
 913	PI_UINT32  cmd_type;
 914	} PI_CMD_CNTRS_GET_REQ;
 915
 916/* Counters_Get Response */
 917
 918typedef struct
 919	{
 920	PI_RSP_HEADER   header;
 921	PI_CNTR		time_since_reset;
 922	PI_CNTR_BLK		cntrs;
 923	} PI_CMD_CNTRS_GET_RSP;
 924
 925/* Counters_Set Request */
 926
 927typedef struct
 928	{
 929	PI_UINT32	cmd_type;
 930	PI_CNTR_BLK	cntrs;
 931	} PI_CMD_CNTRS_SET_REQ;
 932
 933/* Counters_Set Response */
 934
 935typedef struct
 936	{
 937	PI_RSP_HEADER   header;
 938	} PI_CMD_CNTRS_SET_RSP;
 939
 940/* Error_Log_Clear Request */
 941
 942typedef struct
 943	{
 944	PI_UINT32  cmd_type;
 945	} PI_CMD_ERROR_LOG_CLEAR_REQ;
 946
 947/* Error_Log_Clear Response */
 948
 949typedef struct
 950	{
 951	PI_RSP_HEADER   header;
 952	} PI_CMD_ERROR_LOG_CLEAR_RSP;
 953
 954/* Error_Log_Get Request */
 955
 956#define PI_LOG_ENTRY_K_INDEX_MIN	0		/* Minimum index for entry */
 957
 958typedef struct
 959	{
 960	PI_UINT32  cmd_type;
 961	PI_UINT32  entry_index;
 962	} PI_CMD_ERROR_LOG_GET_REQ;
 963
 964/* Error_Log_Get Response */
 965
 966#define PI_K_LOG_FW_SIZE			111		/* Max number of fw longwords */
 967#define PI_K_LOG_DIAG_SIZE	 		6		/* Max number of diag longwords */
 968
 969typedef struct
 970	{
 971	struct
 972		{
 973		PI_UINT32	fru_imp_mask;
 974		PI_UINT32	test_id;
 975		PI_UINT32	reserved[PI_K_LOG_DIAG_SIZE];
 976		} diag;
 977	PI_UINT32		fw[PI_K_LOG_FW_SIZE];
 978	} PI_LOG_ENTRY;
 979
 980typedef struct
 981	{
 982	PI_RSP_HEADER   header;
 983	PI_UINT32		event_status;
 984	PI_UINT32		caller_id;
 985	PI_UINT32		timestamp_l;
 986	PI_UINT32		timestamp_h;
 987	PI_UINT32		write_count;
 988	PI_LOG_ENTRY	entry_info;
 989	} PI_CMD_ERROR_LOG_GET_RSP;
 990
 991/* Define error log related constants and types.					*/
 992/*   Not all of the caller id's can occur.  The only ones currently */
 993/*   implemented are: none, selftest, mfg, fw, console				*/
 994
 995#define PI_LOG_EVENT_STATUS_K_VALID		0	/* Valid Event Status 		*/
 996#define PI_LOG_EVENT_STATUS_K_INVALID	1	/* Invalid Event Status 	*/
 997#define PI_LOG_CALLER_ID_K_NONE		 	0	/* No caller 				*/
 998#define PI_LOG_CALLER_ID_K_SELFTEST	 	1	/* Normal power-up selftest */
 999#define PI_LOG_CALLER_ID_K_MFG		 	2	/* Mfg power-up selftest 	*/
1000#define PI_LOG_CALLER_ID_K_ONLINE		3	/* On-line diagnostics 		*/
1001#define PI_LOG_CALLER_ID_K_HW			4	/* Hardware 				*/
1002#define PI_LOG_CALLER_ID_K_FW			5	/* Firmware 				*/
1003#define PI_LOG_CALLER_ID_K_CNS_HW		6	/* CNS firmware 			*/
1004#define PI_LOG_CALLER_ID_K_CNS_FW		7	/* CNS hardware 			*/
1005#define PI_LOG_CALLER_ID_K_CONSOLE	 	8   /* Console Caller Id 		*/
1006
1007/*
1008 *  Place all DMA commands in the following request and response structures
1009 *  to simplify code.
1010 */
1011
1012typedef union
1013	{
1014	PI_UINT32					cmd_type;
1015	PI_CMD_START_REQ			start;
1016	PI_CMD_FILTERS_SET_REQ		filter_set;
1017	PI_CMD_FILTERS_GET_REQ		filter_get;
1018	PI_CMD_CHARS_SET_REQ		char_set;
1019	PI_CMD_ADDR_FILTER_SET_REQ	addr_filter_set;
1020	PI_CMD_ADDR_FILTER_GET_REQ	addr_filter_get;
1021	PI_CMD_STATUS_CHARS_GET_REQ	stat_char_get;
1022	PI_CMD_CNTRS_GET_REQ		cntrs_get;
1023	PI_CMD_CNTRS_SET_REQ		cntrs_set;
1024	PI_CMD_ERROR_LOG_CLEAR_REQ	error_log_clear;
1025	PI_CMD_ERROR_LOG_GET_REQ	error_log_read;
1026	PI_CMD_SNMP_SET_REQ			snmp_set;
1027	PI_CMD_FDDI_MIB_GET_REQ		fddi_mib_get;
1028	PI_CMD_DEC_EXT_MIB_GET_REQ	dec_mib_get;
1029	PI_CMD_SMT_MIB_SET_REQ		smt_mib_set;
1030	PI_CMD_SMT_MIB_GET_REQ		smt_mib_get;
1031	char						pad[PI_CMD_REQ_K_SIZE_MAX];
1032	} PI_DMA_CMD_REQ;
1033
1034typedef union
1035	{
1036	PI_RSP_HEADER				header;
1037	PI_CMD_START_RSP			start;
1038	PI_CMD_FILTERS_SET_RSP		filter_set;
1039	PI_CMD_FILTERS_GET_RSP		filter_get;
1040	PI_CMD_CHARS_SET_RSP		char_set;
1041	PI_CMD_ADDR_FILTER_SET_RSP	addr_filter_set;
1042	PI_CMD_ADDR_FILTER_GET_RSP	addr_filter_get;
1043	PI_CMD_STATUS_CHARS_GET_RSP	stat_char_get;
1044	PI_CMD_CNTRS_GET_RSP		cntrs_get;
1045	PI_CMD_CNTRS_SET_RSP		cntrs_set;
1046	PI_CMD_ERROR_LOG_CLEAR_RSP	error_log_clear;
1047	PI_CMD_ERROR_LOG_GET_RSP	error_log_get;
1048	PI_CMD_SNMP_SET_RSP			snmp_set;
1049	PI_CMD_FDDI_MIB_GET_RSP		fddi_mib_get;
1050	PI_CMD_DEC_EXT_MIB_GET_RSP	dec_mib_get;
1051	PI_CMD_SMT_MIB_SET_RSP		smt_mib_set;
1052	PI_CMD_SMT_MIB_GET_RSP		smt_mib_get;
1053	char						pad[PI_CMD_RSP_K_SIZE_MAX];
1054	} PI_DMA_CMD_RSP;
1055
1056typedef union
1057	{
1058	PI_DMA_CMD_REQ	request;
1059	PI_DMA_CMD_RSP	response;
1060	} PI_DMA_CMD_BUFFER;
1061
1062
1063/* Define format of Consumer Block (resident in host memory) */
1064
1065typedef struct
1066	{
1067	volatile PI_UINT32	xmt_rcv_data;
1068	volatile PI_UINT32	reserved_1;
1069	volatile PI_UINT32	smt_host;
1070	volatile PI_UINT32	reserved_2;
1071	volatile PI_UINT32	unsol;
1072	volatile PI_UINT32	reserved_3;
1073	volatile PI_UINT32	cmd_rsp;
1074	volatile PI_UINT32	reserved_4;
1075	volatile PI_UINT32	cmd_req;
1076	volatile PI_UINT32	reserved_5;
1077	} PI_CONSUMER_BLOCK;
1078
1079#define PI_CONS_M_RCV_INDEX			0x000000FF
1080#define PI_CONS_M_XMT_INDEX			0x00FF0000
1081#define PI_CONS_V_RCV_INDEX			0
1082#define PI_CONS_V_XMT_INDEX			16
1083
1084/* Offsets into consumer block */
1085
1086#define PI_CONS_BLK_K_XMT_RCV		0x00
1087#define PI_CONS_BLK_K_SMT_HOST		0x08
1088#define PI_CONS_BLK_K_UNSOL			0x10
1089#define PI_CONS_BLK_K_CMD_RSP		0x18
1090#define PI_CONS_BLK_K_CMD_REQ		0x20
1091
1092/* Offsets into descriptor block */
1093
1094#define PI_DESCR_BLK_K_RCV_DATA		0x0000
1095#define PI_DESCR_BLK_K_XMT_DATA		0x0800
1096#define PI_DESCR_BLK_K_SMT_HOST 	0x1000
1097#define PI_DESCR_BLK_K_UNSOL		0x1200
1098#define PI_DESCR_BLK_K_CMD_RSP		0x1280
1099#define PI_DESCR_BLK_K_CMD_REQ		0x1300
1100
1101/* Define format of a rcv descr (Rcv Data, Cmd Rsp, Unsolicited, SMT Host)   */
1102/*   Note a field has been added for later versions of the PDQ to allow for  */
1103/*   finer granularity of the rcv buffer alignment.  For backwards		 	 */
1104/*   compatibility, the two bits (which allow the rcv buffer to be longword  */
1105/*   aligned) have been added at the MBZ bits.  To support previous drivers, */
1106/*   the MBZ definition is left intact.									  	 */
1107
1108typedef struct
1109	{
1110	PI_UINT32	long_0;
1111	PI_UINT32	long_1;
1112	} PI_RCV_DESCR;
1113
1114#define	PI_RCV_DESCR_M_SOP	  		0x80000000
1115#define PI_RCV_DESCR_M_SEG_LEN_LO 	0x60000000
1116#define PI_RCV_DESCR_M_MBZ	  		0x60000000
1117#define PI_RCV_DESCR_M_SEG_LEN		0x1F800000
1118#define PI_RCV_DESCR_M_SEG_LEN_HI	0x1FF00000
1119#define PI_RCV_DESCR_M_SEG_CNT	  	0x000F0000
1120#define PI_RCV_DESCR_M_BUFF_HI	  	0x0000FFFF
1121
1122#define	PI_RCV_DESCR_V_SOP	  		31
1123#define PI_RCV_DESCR_V_SEG_LEN_LO 	29
1124#define PI_RCV_DESCR_V_MBZ	  		29
1125#define PI_RCV_DESCR_V_SEG_LEN	  	23
1126#define PI_RCV_DESCR_V_SEG_LEN_HI 	20
1127#define PI_RCV_DESCR_V_SEG_CNT	  	16
1128#define PI_RCV_DESCR_V_BUFF_HI	 	0
1129
1130/* Define the format of a transmit descriptor (Xmt Data, Cmd Req) */
1131
1132typedef struct
1133	{
1134	PI_UINT32	long_0;
1135	PI_UINT32	long_1;
1136	} PI_XMT_DESCR;
1137
1138#define	PI_XMT_DESCR_M_SOP			0x80000000
1139#define PI_XMT_DESCR_M_EOP			0x40000000
1140#define PI_XMT_DESCR_M_MBZ			0x20000000
1141#define PI_XMT_DESCR_M_SEG_LEN		0x1FFF0000
1142#define PI_XMT_DESCR_M_BUFF_HI		0x0000FFFF
1143
1144#define	PI_XMT_DESCR_V_SOP			31
1145#define	PI_XMT_DESCR_V_EOP			30
1146#define PI_XMT_DESCR_V_MBZ			29
1147#define PI_XMT_DESCR_V_SEG_LEN		16
1148#define PI_XMT_DESCR_V_BUFF_HI		0
1149
1150/* Define format of the Descriptor Block (resident in host memory) */
1151
1152#define PI_RCV_DATA_K_NUM_ENTRIES			256
1153#define PI_XMT_DATA_K_NUM_ENTRIES			256
1154#define PI_SMT_HOST_K_NUM_ENTRIES			64
1155#define PI_UNSOL_K_NUM_ENTRIES				16
1156#define PI_CMD_RSP_K_NUM_ENTRIES			16
1157#define PI_CMD_REQ_K_NUM_ENTRIES			16
1158
1159typedef struct
1160	{
1161	PI_RCV_DESCR  rcv_data[PI_RCV_DATA_K_NUM_ENTRIES];
1162	PI_XMT_DESCR  xmt_data[PI_XMT_DATA_K_NUM_ENTRIES];
1163	PI_RCV_DESCR  smt_host[PI_SMT_HOST_K_NUM_ENTRIES];
1164	PI_RCV_DESCR  unsol[PI_UNSOL_K_NUM_ENTRIES];
1165	PI_RCV_DESCR  cmd_rsp[PI_CMD_RSP_K_NUM_ENTRIES];
1166	PI_XMT_DESCR  cmd_req[PI_CMD_REQ_K_NUM_ENTRIES];
1167	} PI_DESCR_BLOCK;
1168
1169/* Define Port Registers - offsets from PDQ Base address */
1170
1171#define PI_PDQ_K_REG_PORT_RESET			0x00000000
1172#define PI_PDQ_K_REG_HOST_DATA			0x00000004
1173#define PI_PDQ_K_REG_PORT_CTRL			0x00000008
1174#define PI_PDQ_K_REG_PORT_DATA_A		0x0000000C
1175#define PI_PDQ_K_REG_PORT_DATA_B		0x00000010
1176#define PI_PDQ_K_REG_PORT_STATUS		0x00000014
1177#define PI_PDQ_K_REG_TYPE_0_STATUS 		0x00000018
1178#define PI_PDQ_K_REG_HOST_INT_ENB	  	0x0000001C
1179#define PI_PDQ_K_REG_TYPE_2_PROD_NOINT 	0x00000020
1180#define PI_PDQ_K_REG_TYPE_2_PROD		0x00000024
1181#define PI_PDQ_K_REG_CMD_RSP_PROD		0x00000028
1182#define PI_PDQ_K_REG_CMD_REQ_PROD		0x0000002C
1183#define PI_PDQ_K_REG_SMT_HOST_PROD   	0x00000030
1184#define PI_PDQ_K_REG_UNSOL_PROD			0x00000034
1185
1186/* Port Control Register - Command codes for primary commands */
1187
1188#define PI_PCTRL_M_CMD_ERROR			0x8000
1189#define PI_PCTRL_M_BLAST_FLASH			0x4000
1190#define PI_PCTRL_M_HALT					0x2000
1191#define PI_PCTRL_M_COPY_DATA			0x1000
1192#define PI_PCTRL_M_ERROR_LOG_START		0x0800
1193#define PI_PCTRL_M_ERROR_LOG_READ		0x0400
1194#define PI_PCTRL_M_XMT_DATA_FLUSH_DONE	0x0200
1195#define PI_PCTRL_M_INIT					0x0100
1196#define PI_PCTRL_M_INIT_START		    0x0080
1197#define PI_PCTRL_M_CONS_BLOCK			0x0040
1198#define PI_PCTRL_M_UNINIT				0x0020
1199#define PI_PCTRL_M_RING_MEMBER			0x0010
1200#define PI_PCTRL_M_MLA					0x0008
1201#define PI_PCTRL_M_FW_REV_READ			0x0004
1202#define PI_PCTRL_M_DEV_SPECIFIC			0x0002
1203#define PI_PCTRL_M_SUB_CMD				0x0001
1204
1205/* Define sub-commands accessed via the PI_PCTRL_M_SUB_CMD command */
1206
1207#define PI_SUB_CMD_K_LINK_UNINIT		0x0001
1208#define PI_SUB_CMD_K_BURST_SIZE_SET		0x0002
1209#define PI_SUB_CMD_K_PDQ_REV_GET		0x0004
1210#define PI_SUB_CMD_K_HW_REV_GET			0x0008
1211
1212/* Define some Port Data B values */
1213
1214#define PI_PDATA_B_DMA_BURST_SIZE_4	 	0		/* valid values for command */
1215#define PI_PDATA_B_DMA_BURST_SIZE_8	 	1
1216#define PI_PDATA_B_DMA_BURST_SIZE_16	2
1217#define PI_PDATA_B_DMA_BURST_SIZE_32	3		/* not supported on PCI */
1218#define PI_PDATA_B_DMA_BURST_SIZE_DEF	PI_PDATA_B_DMA_BURST_SIZE_16
1219
1220/* Port Data A Reset state */
1221
1222#define PI_PDATA_A_RESET_M_UPGRADE		0x00000001
1223#define PI_PDATA_A_RESET_M_SOFT_RESET	0x00000002
1224#define PI_PDATA_A_RESET_M_SKIP_ST		0x00000004
1225
1226/* Read adapter MLA address port control command constants */
1227
1228#define PI_PDATA_A_MLA_K_LO				0
1229#define PI_PDATA_A_MLA_K_HI				1
1230
1231/* Byte Swap values for init command */
1232
1233#define PI_PDATA_A_INIT_M_DESC_BLK_ADDR			0x0FFFFE000
1234#define PI_PDATA_A_INIT_M_RESERVED				0x000001FFC
1235#define PI_PDATA_A_INIT_M_BSWAP_DATA			0x000000002
1236#define PI_PDATA_A_INIT_M_BSWAP_LITERAL			0x000000001
1237
1238#define PI_PDATA_A_INIT_V_DESC_BLK_ADDR			13
1239#define PI_PDATA_A_INIT_V_RESERVED				3
1240#define PI_PDATA_A_INIT_V_BSWAP_DATA			1
1241#define PI_PDATA_A_INIT_V_BSWAP_LITERAL			0
1242
1243/* Port Reset Register */
1244
1245#define PI_RESET_M_ASSERT_RESET			1
1246
1247/* Port Status register */
1248
1249#define PI_PSTATUS_V_RCV_DATA_PENDING	31
1250#define PI_PSTATUS_V_XMT_DATA_PENDING	30
1251#define PI_PSTATUS_V_SMT_HOST_PENDING	29
1252#define PI_PSTATUS_V_UNSOL_PENDING		28
1253#define PI_PSTATUS_V_CMD_RSP_PENDING	27
1254#define PI_PSTATUS_V_CMD_REQ_PENDING	26
1255#define PI_PSTATUS_V_TYPE_0_PENDING		25
1256#define PI_PSTATUS_V_RESERVED_1			16
1257#define PI_PSTATUS_V_RESERVED_2			11
1258#define PI_PSTATUS_V_STATE				8
1259#define PI_PSTATUS_V_HALT_ID			0
1260
1261#define PI_PSTATUS_M_RCV_DATA_PENDING	0x80000000
1262#define PI_PSTATUS_M_XMT_DATA_PENDING	0x40000000
1263#define PI_PSTATUS_M_SMT_HOST_PENDING	0x20000000
1264#define PI_PSTATUS_M_UNSOL_PENDING		0x10000000
1265#define PI_PSTATUS_M_CMD_RSP_PENDING	0x08000000
1266#define PI_PSTATUS_M_CMD_REQ_PENDING	0x04000000
1267#define PI_PSTATUS_M_TYPE_0_PENDING		0x02000000
1268#define PI_PSTATUS_M_RESERVED_1			0x01FF0000
1269#define PI_PSTATUS_M_RESERVED_2			0x0000F800
1270#define PI_PSTATUS_M_STATE				0x00000700
1271#define PI_PSTATUS_M_HALT_ID			0x000000FF
1272
1273/* Define Halt Id's			 					*/
1274/*   Do not insert into this list, only append. */
1275
1276#define PI_HALT_ID_K_SELFTEST_TIMEOUT	0
1277#define PI_HALT_ID_K_PARITY_ERROR		1
1278#define PI_HALT_ID_K_HOST_DIR_HALT		2
1279#define PI_HALT_ID_K_SW_FAULT			3
1280#define PI_HALT_ID_K_HW_FAULT			4
1281#define PI_HALT_ID_K_PC_TRACE			5
1282#define PI_HALT_ID_K_DMA_ERROR			6			/* Host Data has error reg */
1283#define PI_HALT_ID_K_IMAGE_CRC_ERROR	7   		/* Image is bad, update it */
1284#define PI_HALT_ID_K_BUS_EXCEPTION	 	8   		/* 68K bus exception	   */
1285
1286/* Host Interrupt Enable Register as seen by host */
1287
1288#define PI_HOST_INT_M_XMT_DATA_ENB		0x80000000	/* Type 2 Enables */
1289#define PI_HOST_INT_M_RCV_DATA_ENB		0x40000000
1290#define PI_HOST_INT_M_SMT_HOST_ENB		0x10000000	/* Type 1 Enables */
1291#define PI_HOST_INT_M_UNSOL_ENB			0x20000000
1292#define PI_HOST_INT_M_CMD_RSP_ENB		0x08000000
1293#define PI_HOST_INT_M_CMD_REQ_ENB		0x04000000
1294#define	PI_HOST_INT_M_TYPE_1_RESERVED	0x00FF0000
1295#define	PI_HOST_INT_M_TYPE_0_RESERVED	0x0000FF00	/* Type 0 Enables */
1296#define PI_HOST_INT_M_1MS				0x00000080
1297#define PI_HOST_INT_M_20MS				0x00000040
1298#define PI_HOST_INT_M_CSR_CMD_DONE		0x00000020
1299#define PI_HOST_INT_M_STATE_CHANGE		0x00000010
1300#define PI_HOST_INT_M_XMT_FLUSH			0x00000008
1301#define PI_HOST_INT_M_NXM				0x00000004
1302#define PI_HOST_INT_M_PM_PAR_ERR		0x00000002
1303#define PI_HOST_INT_M_BUS_PAR_ERR		0x00000001
1304
1305#define PI_HOST_INT_V_XMT_DATA_ENB		31			/* Type 2 Enables */
1306#define PI_HOST_INT_V_RCV_DATA_ENB		30
1307#define PI_HOST_INT_V_SMT_HOST_ENB		29			/* Type 1 Enables */
1308#define PI_HOST_INT_V_UNSOL_ENB			28
1309#define PI_HOST_INT_V_CMD_RSP_ENB		27
1310#define PI_HOST_INT_V_CMD_REQ_ENB		26
1311#define	PI_HOST_INT_V_TYPE_1_RESERVED	16
1312#define	PI_HOST_INT_V_TYPE_0_RESERVED   8			/* Type 0 Enables */
1313#define PI_HOST_INT_V_1MS_ENB			7
1314#define PI_HOST_INT_V_20MS_ENB			6
1315#define PI_HOST_INT_V_CSR_CMD_DONE_ENB	5
1316#define PI_HOST_INT_V_STATE_CHANGE_ENB	4
1317#define PI_HOST_INT_V_XMT_FLUSH_ENB 	3
1318#define PI_HOST_INT_V_NXM_ENB			2
1319#define PI_HOST_INT_V_PM_PAR_ERR_ENB	1
1320#define PI_HOST_INT_V_BUS_PAR_ERR_ENB	0
1321
1322#define PI_HOST_INT_K_ACK_ALL_TYPE_0	0x000000FF
1323#define PI_HOST_INT_K_DISABLE_ALL_INTS	0x00000000
1324#define PI_HOST_INT_K_ENABLE_ALL_INTS	0xFFFFFFFF
1325#define PI_HOST_INT_K_ENABLE_DEF_INTS	0xC000001F
1326
1327/* Type 0 Interrupt Status Register */
1328
1329#define PI_TYPE_0_STAT_M_1MS			0x00000080
1330#define PI_TYPE_0_STAT_M_20MS			0x00000040
1331#define PI_TYPE_0_STAT_M_CSR_CMD_DONE	0x00000020
1332#define PI_TYPE_0_STAT_M_STATE_CHANGE	0x00000010
1333#define PI_TYPE_0_STAT_M_XMT_FLUSH		0x00000008
1334#define PI_TYPE_0_STAT_M_NXM			0x00000004
1335#define PI_TYPE_0_STAT_M_PM_PAR_ERR		0x00000002
1336#define PI_TYPE_0_STAT_M_BUS_PAR_ERR	0x00000001
1337
1338#define PI_TYPE_0_STAT_V_1MS			7
1339#define PI_TYPE_0_STAT_V_20MS			6
1340#define PI_TYPE_0_STAT_V_CSR_CMD_DONE	5
1341#define PI_TYPE_0_STAT_V_STATE_CHANGE	4
1342#define PI_TYPE_0_STAT_V_XMT_FLUSH		3
1343#define PI_TYPE_0_STAT_V_NXM			2
1344#define PI_TYPE_0_STAT_V_PM_PAR_ERR		1
1345#define PI_TYPE_0_STAT_V_BUS_PAR_ERR	0
1346
1347/* Register definition structures are defined for both big and little endian systems */
1348
1349#ifndef __BIG_ENDIAN
1350
1351/* Little endian format of Type 1 Producer register */
1352
1353typedef union
1354	{
1355	PI_UINT32	lword;
1356	struct
1357		{
1358		PI_UINT8	prod;
1359		PI_UINT8	comp;
1360		PI_UINT8	mbz_1;
1361		PI_UINT8	mbz_2;
1362		} index;
1363	} PI_TYPE_1_PROD_REG;
1364
1365/* Little endian format of Type 2 Producer register */
1366
1367typedef union
1368	{
1369	PI_UINT32	lword;
1370	struct
1371		{
1372		PI_UINT8	rcv_prod;
1373		PI_UINT8	xmt_prod;
1374		PI_UINT8	rcv_comp;
1375		PI_UINT8	xmt_comp;
1376		} index;
1377	} PI_TYPE_2_PROD_REG;
1378
1379/* Little endian format of Type 1 Consumer Block longword */
1380
1381typedef union
1382	{
1383	PI_UINT32	lword;
1384	struct
1385		{
1386		PI_UINT8	cons;
1387		PI_UINT8	res0;
1388		PI_UINT8	res1;
1389		PI_UINT8	res2;
1390		} index;
1391	} PI_TYPE_1_CONSUMER;
1392
1393/* Little endian format of Type 2 Consumer Block longword */
1394
1395typedef union
1396	{
1397	PI_UINT32	lword;
1398	struct
1399		{
1400		PI_UINT8	rcv_cons;
1401		PI_UINT8	res0;
1402		PI_UINT8	xmt_cons;
1403		PI_UINT8	res1;
1404		} index;
1405	} PI_TYPE_2_CONSUMER;
1406
1407/* Define swapping required by DMA transfers.  */
1408#define PI_PDATA_A_INIT_M_BSWAP_INIT	\
1409	(PI_PDATA_A_INIT_M_BSWAP_DATA)
1410
1411#else /* __BIG_ENDIAN */
1412
1413/* Big endian format of Type 1 Producer register */
1414
1415typedef union
1416	{
1417	PI_UINT32	lword;
1418	struct
1419		{
1420		PI_UINT8	mbz_2;
1421		PI_UINT8	mbz_1;
1422		PI_UINT8	comp;
1423		PI_UINT8	prod;
1424		} index;
1425	} PI_TYPE_1_PROD_REG;
1426
1427/* Big endian format of Type 2 Producer register */
1428
1429typedef union
1430	{
1431	PI_UINT32	lword;
1432	struct
1433		{
1434		PI_UINT8	xmt_comp;
1435		PI_UINT8	rcv_comp;
1436		PI_UINT8	xmt_prod;
1437		PI_UINT8	rcv_prod;
1438		} index;
1439	} PI_TYPE_2_PROD_REG;
1440
1441/* Big endian format of Type 1 Consumer Block longword */
1442
1443typedef union
1444	{
1445	PI_UINT32	lword;
1446	struct
1447		{
1448		PI_UINT8	res2;
1449		PI_UINT8	res1;
1450		PI_UINT8	res0;
1451		PI_UINT8	cons;
1452		} index;
1453	} PI_TYPE_1_CONSUMER;
1454
1455/* Big endian format of Type 2 Consumer Block longword */
1456
1457typedef union
1458	{
1459	PI_UINT32	lword;
1460	struct
1461		{
1462		PI_UINT8	res1;
1463		PI_UINT8	xmt_cons;
1464		PI_UINT8	res0;
1465		PI_UINT8	rcv_cons;
1466		} index;
1467	} PI_TYPE_2_CONSUMER;
1468
1469/* Define swapping required by DMA transfers.  */
1470#define PI_PDATA_A_INIT_M_BSWAP_INIT	\
1471	(PI_PDATA_A_INIT_M_BSWAP_DATA | PI_PDATA_A_INIT_M_BSWAP_LITERAL)
1472
1473#endif /* __BIG_ENDIAN */
1474
1475/* Define TC PDQ CSR offset and length */
1476
1477#define PI_TC_K_CSR_OFFSET		0x100000
1478#define PI_TC_K_CSR_LEN			0x40		/* 64 bytes */
1479
1480/* Define EISA controller register offsets */
1481
1482#define PI_ESIC_K_CSR_IO_LEN		0x40		/* 64 bytes */
1483#define PI_ESIC_K_BURST_HOLDOFF_LEN	0x04		/* 4 bytes */
1484#define PI_ESIC_K_ESIC_CSR_LEN		0x40		/* 64 bytes */
1485
1486#define PI_DEFEA_K_CSR_IO		0x000
1487#define PI_DEFEA_K_BURST_HOLDOFF	0x040
1488#define PI_ESIC_K_ESIC_CSR		0xC80
1489
1490#define PI_ESIC_K_SLOT_ID            	0xC80
1491#define PI_ESIC_K_SLOT_CNTRL		0xC84
1492#define PI_ESIC_K_MEM_ADD_CMP_0     	0xC85
1493#define PI_ESIC_K_MEM_ADD_CMP_1     	0xC86
1494#define PI_ESIC_K_MEM_ADD_CMP_2     	0xC87
1495#define PI_ESIC_K_MEM_ADD_HI_CMP_0  	0xC88
1496#define PI_ESIC_K_MEM_ADD_HI_CMP_1  	0xC89
1497#define PI_ESIC_K_MEM_ADD_HI_CMP_2  	0xC8A
1498#define PI_ESIC_K_MEM_ADD_MASK_0     	0xC8B
1499#define PI_ESIC_K_MEM_ADD_MASK_1     	0xC8C
1500#define PI_ESIC_K_MEM_ADD_MASK_2     	0xC8D
1501#define PI_ESIC_K_MEM_ADD_LO_CMP_0  	0xC8E
1502#define PI_ESIC_K_MEM_ADD_LO_CMP_1  	0xC8F
1503#define PI_ESIC_K_MEM_ADD_LO_CMP_2  	0xC90
1504#define PI_ESIC_K_IO_ADD_CMP_0_0	0xC91
1505#define PI_ESIC_K_IO_ADD_CMP_0_1	0xC92
1506#define PI_ESIC_K_IO_ADD_CMP_1_0	0xC93
1507#define PI_ESIC_K_IO_ADD_CMP_1_1	0xC94
1508#define PI_ESIC_K_IO_ADD_CMP_2_0	0xC95
1509#define PI_ESIC_K_IO_ADD_CMP_2_1	0xC96
1510#define PI_ESIC_K_IO_ADD_CMP_3_0	0xC97
1511#define PI_ESIC_K_IO_ADD_CMP_3_1	0xC98
1512#define PI_ESIC_K_IO_ADD_MASK_0_0    	0xC99
1513#define PI_ESIC_K_IO_ADD_MASK_0_1    	0xC9A
1514#define PI_ESIC_K_IO_ADD_MASK_1_0    	0xC9B
1515#define PI_ESIC_K_IO_ADD_MASK_1_1    	0xC9C
1516#define PI_ESIC_K_IO_ADD_MASK_2_0    	0xC9D
1517#define PI_ESIC_K_IO_ADD_MASK_2_1    	0xC9E
1518#define PI_ESIC_K_IO_ADD_MASK_3_0    	0xC9F
1519#define PI_ESIC_K_IO_ADD_MASK_3_1    	0xCA0
1520#define PI_ESIC_K_MOD_CONFIG_1		0xCA1
1521#define PI_ESIC_K_MOD_CONFIG_2		0xCA2
1522#define PI_ESIC_K_MOD_CONFIG_3		0xCA3
1523#define PI_ESIC_K_MOD_CONFIG_4		0xCA4
1524#define PI_ESIC_K_MOD_CONFIG_5    	0xCA5
1525#define PI_ESIC_K_MOD_CONFIG_6		0xCA6
1526#define PI_ESIC_K_MOD_CONFIG_7		0xCA7
1527#define PI_ESIC_K_DIP_SWITCH         	0xCA8
1528#define PI_ESIC_K_IO_CONFIG_STAT_0   	0xCA9
1529#define PI_ESIC_K_IO_CONFIG_STAT_1   	0xCAA
1530#define PI_ESIC_K_DMA_CONFIG         	0xCAB
1531#define PI_ESIC_K_INPUT_PORT         	0xCAC
1532#define PI_ESIC_K_OUTPUT_PORT        	0xCAD
1533#define PI_ESIC_K_FUNCTION_CNTRL	0xCAE
1534
1535/* Define the bits in the function control register. */
1536
1537#define PI_FUNCTION_CNTRL_M_IOCS0	0x01
1538#define PI_FUNCTION_CNTRL_M_IOCS1	0x02
1539#define PI_FUNCTION_CNTRL_M_IOCS2	0x04
1540#define PI_FUNCTION_CNTRL_M_IOCS3	0x08
1541#define PI_FUNCTION_CNTRL_M_MEMCS0	0x10
1542#define PI_FUNCTION_CNTRL_M_MEMCS1	0x20
1543#define PI_FUNCTION_CNTRL_M_DMA		0x80
1544
1545/* Define the bits in the slot control register. */
1546
1547#define PI_SLOT_CNTRL_M_RESET		0x04	/* Don't use.       */
1548#define PI_SLOT_CNTRL_M_ERROR		0x02	/* Not implemented. */
1549#define PI_SLOT_CNTRL_M_ENB		0x01	/* Must be set.     */
1550
1551/* Define the bits in the burst holdoff register. */
1552
1553#define PI_BURST_HOLDOFF_M_HOLDOFF	0xFC
1554#define PI_BURST_HOLDOFF_M_RESERVED	0x02
1555#define PI_BURST_HOLDOFF_M_MEM_MAP	0x01
1556
1557#define PI_BURST_HOLDOFF_V_HOLDOFF	2
1558#define PI_BURST_HOLDOFF_V_RESERVED	1
1559#define PI_BURST_HOLDOFF_V_MEM_MAP	0
1560
1561/* Define the implicit mask of the Memory Address Compare registers.  */
1562
1563#define PI_MEM_ADD_MASK_M		0x3ff
1564
1565/* Define the fields in the I/O Address Compare and Mask registers.  */
1566
1567#define PI_IO_CMP_M_SLOT		0xf0
1568
1569#define PI_IO_CMP_V_SLOT		4
1570
1571/* Define the fields in the Interrupt Channel Configuration and Status reg */
1572
1573#define PI_CONFIG_STAT_0_M_PEND			0x80
1574#define PI_CONFIG_STAT_0_M_RES_1		0x40
1575#define PI_CONFIG_STAT_0_M_IREQ_OUT		0x20
1576#define PI_CONFIG_STAT_0_M_IREQ_IN		0x10
1577#define PI_CONFIG_STAT_0_M_INT_ENB		0x08
1578#define PI_CONFIG_STAT_0_M_RES_0		0x04
1579#define PI_CONFIG_STAT_0_M_IRQ			0x03
1580
1581#define PI_CONFIG_STAT_0_V_PEND			7
1582#define PI_CONFIG_STAT_0_V_RES_1		6
1583#define PI_CONFIG_STAT_0_V_IREQ_OUT		5
1584#define PI_CONFIG_STAT_0_V_IREQ_IN		4
1585#define PI_CONFIG_STAT_0_V_INT_ENB		3
1586#define PI_CONFIG_STAT_0_V_RES_0		2
1587#define PI_CONFIG_STAT_0_V_IRQ			0
1588
1589#define PI_CONFIG_STAT_0_IRQ_K_9		0
1590#define PI_CONFIG_STAT_0_IRQ_K_10		1
1591#define PI_CONFIG_STAT_0_IRQ_K_11		2
1592#define PI_CONFIG_STAT_0_IRQ_K_15		3
1593
1594/* Define DEC FDDIcontroller/EISA (DEFEA) EISA hardware ID's */
1595
1596#define DEFEA_PRODUCT_ID	0x0030A310		/* DEC product 300 (no rev)	*/
1597#define DEFEA_PROD_ID_1		0x0130A310		/* DEC product 300, rev 1	*/
1598#define DEFEA_PROD_ID_2		0x0230A310		/* DEC product 300, rev 2	*/
1599#define DEFEA_PROD_ID_3		0x0330A310		/* DEC product 300, rev 3	*/
1600#define DEFEA_PROD_ID_4		0x0430A310		/* DEC product 300, rev 4	*/
1601
1602/**********************************************/
1603/* Digital PFI Specification v1.0 Definitions */
1604/**********************************************/
1605
1606/* PCI Configuration Space Constants */
1607
1608#define PFI_K_LAT_TIMER_DEF			0x88	/* def max master latency timer */
1609#define PFI_K_LAT_TIMER_MIN			0x20	/* min max master latency timer */
1610#define PFI_K_CSR_MEM_LEN			0x80	/* 128 bytes */
1611#define PFI_K_CSR_IO_LEN			0x80	/* 128 bytes */
1612#define PFI_K_PKT_MEM_LEN			0x10000	/* 64K bytes */
1613
1614/* PFI Register Offsets (starting at PDQ Register Base Address) */
1615
1616#define PFI_K_REG_RESERVED_0		 0X00000038
1617#define PFI_K_REG_RESERVED_1		 0X0000003C
1618#define PFI_K_REG_MODE_CTRL		 0X00000040
1619#define PFI_K_REG_STATUS		 0X00000044
1620#define PFI_K_REG_FIFO_WRITE		 0X00000048
1621#define PFI_K_REG_FIFO_READ		 0X0000004C
1622
1623/* PFI Mode Control Register Constants */
1624
1625#define PFI_MODE_M_RESERVED		 0XFFFFFFF0
1626#define PFI_MODE_M_TGT_ABORT_ENB	 0X00000008
1627#define PFI_MODE_M_PDQ_INT_ENB		 0X00000004
1628#define PFI_MODE_M_PFI_INT_ENB		 0X00000002
1629#define PFI_MODE_M_DMA_ENB		 0X00000001
1630
1631#define PFI_MODE_V_RESERVED		 4
1632#define PFI_MODE_V_TGT_ABORT_ENB	 3
1633#define PFI_MODE_V_PDQ_INT_ENB		 2
1634#define PFI_MODE_V_PFI_INT_ENB		 1
1635#define PFI_MODE_V_DMA_ENB		 0
1636
1637#define PFI_MODE_K_ALL_DISABLE		 0X00000000
1638
1639/* PFI Status Register Constants */
1640
1641#define PFI_STATUS_M_RESERVED		 0XFFFFFFC0
1642#define PFI_STATUS_M_PFI_ERROR		 0X00000020		/* only valid in rev 1 or later PFI */
1643#define PFI_STATUS_M_PDQ_INT		 0X00000010
1644#define PFI_STATUS_M_PDQ_DMA_ABORT	 0X00000008
1645#define PFI_STATUS_M_FIFO_FULL		 0X00000004
1646#define PFI_STATUS_M_FIFO_EMPTY		 0X00000002
1647#define PFI_STATUS_M_DMA_IN_PROGRESS	 0X00000001
1648
1649#define PFI_STATUS_V_RESERVED		 6
1650#define PFI_STATUS_V_PFI_ERROR		 5			/* only valid in rev 1 or later PFI */
1651#define PFI_STATUS_V_PDQ_INT		 4
1652#define PFI_STATUS_V_PDQ_DMA_ABORT	 3
1653#define PFI_STATUS_V_FIFO_FULL		 2
1654#define PFI_STATUS_V_FIFO_EMPTY		 1
1655#define PFI_STATUS_V_DMA_IN_PROGRESS 0
1656
1657#define DFX_FC_PRH2_PRH1_PRH0		0x54003820	/* Packet Request Header bytes + FC */
1658#define DFX_PRH0_BYTE			0x20		/* Packet Request Header byte 0 */
1659#define DFX_PRH1_BYTE			0x38		/* Packet Request Header byte 1 */
1660#define DFX_PRH2_BYTE			0x00		/* Packet Request Header byte 2 */
1661
1662/* Driver routine status (return) codes */
1663
1664#define DFX_K_SUCCESS			0			/* routine succeeded */
1665#define DFX_K_FAILURE			1			/* routine failed */
1666#define DFX_K_OUTSTATE			2			/* bad state for command */
1667#define DFX_K_HW_TIMEOUT		3			/* command timed out */
1668
1669/* Define LLC host receive buffer min/max/default values */
1670
1671#define RCV_BUFS_MIN	2					/* minimum pre-allocated receive buffers */
1672#define RCV_BUFS_MAX	32					/* maximum pre-allocated receive buffers */
1673#define RCV_BUFS_DEF	8					/* default pre-allocated receive buffers */
1674
1675/* Define offsets into FDDI LLC or SMT receive frame buffers - used when indicating frameā€¦

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