/drivers/net/fddi/skfp/h/fplustm.h

http://github.com/mirrors/linux · C Header · 270 lines · 173 code · 33 blank · 64 comment · 0 complexity · fe714f249f33ee13b3240481ada12800 MD5 · raw file

  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /******************************************************************************
  3. *
  4. * (C)Copyright 1998,1999 SysKonnect,
  5. * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
  6. *
  7. * The information in this file is provided "AS IS" without warranty.
  8. *
  9. ******************************************************************************/
  10. /*
  11. * AMD Fplus in tag mode data structs
  12. * defs for fplustm.c
  13. */
  14. #ifndef _FPLUS_
  15. #define _FPLUS_
  16. #ifndef HW_PTR
  17. #define HW_PTR void __iomem *
  18. #endif
  19. /*
  20. * fplus error statistic structure
  21. */
  22. struct err_st {
  23. u_long err_valid ; /* memory status valid */
  24. u_long err_abort ; /* memory status receive abort */
  25. u_long err_e_indicator ; /* error indicator */
  26. u_long err_crc ; /* error detected (CRC or length) */
  27. u_long err_llc_frame ; /* LLC frame */
  28. u_long err_mac_frame ; /* MAC frame */
  29. u_long err_smt_frame ; /* SMT frame */
  30. u_long err_imp_frame ; /* implementer frame */
  31. u_long err_no_buf ; /* no buffer available */
  32. u_long err_too_long ; /* longer than max. buffer */
  33. u_long err_bec_stat ; /* beacon state entered */
  34. u_long err_clm_stat ; /* claim state entered */
  35. u_long err_sifg_det ; /* short interframe gap detect */
  36. u_long err_phinv ; /* PHY invalid */
  37. u_long err_tkiss ; /* token issued */
  38. u_long err_tkerr ; /* token error */
  39. } ;
  40. /*
  41. * Transmit Descriptor struct
  42. */
  43. struct s_smt_fp_txd {
  44. __le32 txd_tbctrl ; /* transmit buffer control */
  45. __le32 txd_txdscr ; /* transmit frame status word */
  46. __le32 txd_tbadr ; /* physical tx buffer address */
  47. __le32 txd_ntdadr ; /* physical pointer to the next TxD */
  48. #ifdef ENA_64BIT_SUP
  49. __le32 txd_tbadr_hi ; /* physical tx buffer addr (high dword)*/
  50. #endif
  51. char far *txd_virt ; /* virtual pointer to the data frag */
  52. /* virt pointer to the next TxD */
  53. struct s_smt_fp_txd volatile far *txd_next ;
  54. struct s_txd_os txd_os ; /* OS - specific struct */
  55. } ;
  56. /*
  57. * Receive Descriptor struct
  58. */
  59. struct s_smt_fp_rxd {
  60. __le32 rxd_rbctrl ; /* receive buffer control */
  61. __le32 rxd_rfsw ; /* receive frame status word */
  62. __le32 rxd_rbadr ; /* physical rx buffer address */
  63. __le32 rxd_nrdadr ; /* physical pointer to the next RxD */
  64. #ifdef ENA_64BIT_SUP
  65. __le32 rxd_rbadr_hi ; /* physical tx buffer addr (high dword)*/
  66. #endif
  67. char far *rxd_virt ; /* virtual pointer to the data frag */
  68. /* virt pointer to the next RxD */
  69. struct s_smt_fp_rxd volatile far *rxd_next ;
  70. struct s_rxd_os rxd_os ; /* OS - specific struct */
  71. } ;
  72. /*
  73. * Descriptor Union Definition
  74. */
  75. union s_fp_descr {
  76. struct s_smt_fp_txd t ; /* pointer to the TxD */
  77. struct s_smt_fp_rxd r ; /* pointer to the RxD */
  78. } ;
  79. /*
  80. * TxD Ring Control struct
  81. */
  82. struct s_smt_tx_queue {
  83. struct s_smt_fp_txd volatile *tx_curr_put ; /* next free TxD */
  84. struct s_smt_fp_txd volatile *tx_prev_put ; /* shadow put pointer */
  85. struct s_smt_fp_txd volatile *tx_curr_get ; /* next TxD to release*/
  86. u_short tx_free ; /* count of free TxD's */
  87. u_short tx_used ; /* count of used TxD's */
  88. HW_PTR tx_bmu_ctl ; /* BMU addr for tx start */
  89. HW_PTR tx_bmu_dsc ; /* BMU addr for curr dsc. */
  90. } ;
  91. /*
  92. * RxD Ring Control struct
  93. */
  94. struct s_smt_rx_queue {
  95. struct s_smt_fp_rxd volatile *rx_curr_put ; /* next RxD to queue into */
  96. struct s_smt_fp_rxd volatile *rx_prev_put ; /* shadow put pointer */
  97. struct s_smt_fp_rxd volatile *rx_curr_get ; /* next RxD to fill */
  98. u_short rx_free ; /* count of free RxD's */
  99. u_short rx_used ; /* count of used RxD's */
  100. HW_PTR rx_bmu_ctl ; /* BMU addr for rx start */
  101. HW_PTR rx_bmu_dsc ; /* BMU addr for curr dsc. */
  102. } ;
  103. #define VOID_FRAME_OFF 0x00
  104. #define CLAIM_FRAME_OFF 0x08
  105. #define BEACON_FRAME_OFF 0x10
  106. #define DBEACON_FRAME_OFF 0x18
  107. #define RX_FIFO_OFF 0x21 /* to get a prime number for */
  108. /* the RX_FIFO_SPACE */
  109. #define RBC_MEM_SIZE 0x8000
  110. #define SEND_ASYNC_AS_SYNC 0x1
  111. #define SYNC_TRAFFIC_ON 0x2
  112. /* big FIFO memory */
  113. #define RX_FIFO_SPACE 0x4000 - RX_FIFO_OFF
  114. #define TX_FIFO_SPACE 0x4000
  115. #define TX_SMALL_FIFO 0x0900
  116. #define TX_MEDIUM_FIFO TX_FIFO_SPACE / 2
  117. #define TX_LARGE_FIFO TX_FIFO_SPACE - TX_SMALL_FIFO
  118. #define RX_SMALL_FIFO 0x0900
  119. #define RX_LARGE_FIFO RX_FIFO_SPACE - RX_SMALL_FIFO
  120. struct s_smt_fifo_conf {
  121. u_short rbc_ram_start ; /* FIFO start address */
  122. u_short rbc_ram_end ; /* FIFO size */
  123. u_short rx1_fifo_start ; /* rx queue start address */
  124. u_short rx1_fifo_size ; /* rx queue size */
  125. u_short rx2_fifo_start ; /* rx queue start address */
  126. u_short rx2_fifo_size ; /* rx queue size */
  127. u_short tx_s_start ; /* sync queue start address */
  128. u_short tx_s_size ; /* sync queue size */
  129. u_short tx_a0_start ; /* async queue A0 start address */
  130. u_short tx_a0_size ; /* async queue A0 size */
  131. u_short fifo_config_mode ; /* FIFO configuration mode */
  132. } ;
  133. #define FM_ADDRX (FM_ADDET|FM_EXGPA0|FM_EXGPA1)
  134. struct s_smt_fp {
  135. u_short mdr2init ; /* mode register 2 init value */
  136. u_short mdr3init ; /* mode register 3 init value */
  137. u_short frselreg_init ; /* frame selection register init val */
  138. u_short rx_mode ; /* address mode broad/multi/promisc */
  139. u_short nsa_mode ;
  140. u_short rx_prom ;
  141. u_short exgpa ;
  142. struct err_st err_stats ; /* error statistics */
  143. /*
  144. * MAC buffers
  145. */
  146. struct fddi_mac_sf { /* special frame build buffer */
  147. u_char mac_fc ;
  148. struct fddi_addr mac_dest ;
  149. struct fddi_addr mac_source ;
  150. u_char mac_info[0x20] ;
  151. } mac_sfb ;
  152. /*
  153. * queues
  154. */
  155. #define QUEUE_S 0
  156. #define QUEUE_A0 1
  157. #define QUEUE_R1 0
  158. #define QUEUE_R2 1
  159. #define USED_QUEUES 2
  160. /*
  161. * queue pointers; points to the queue dependent variables
  162. */
  163. struct s_smt_tx_queue *tx[USED_QUEUES] ;
  164. struct s_smt_rx_queue *rx[USED_QUEUES] ;
  165. /*
  166. * queue dependent variables
  167. */
  168. struct s_smt_tx_queue tx_q[USED_QUEUES] ;
  169. struct s_smt_rx_queue rx_q[USED_QUEUES] ;
  170. /*
  171. * FIFO configuration struct
  172. */
  173. struct s_smt_fifo_conf fifo ;
  174. /* last formac status */
  175. u_short s2u ;
  176. u_short s2l ;
  177. /* calculated FORMAC+ reg.addr. */
  178. HW_PTR fm_st1u ;
  179. HW_PTR fm_st1l ;
  180. HW_PTR fm_st2u ;
  181. HW_PTR fm_st2l ;
  182. HW_PTR fm_st3u ;
  183. HW_PTR fm_st3l ;
  184. /*
  185. * multicast table
  186. */
  187. #define FPMAX_MULTICAST 32
  188. #define SMT_MAX_MULTI 4
  189. struct {
  190. struct s_fpmc {
  191. struct fddi_addr a ; /* mc address */
  192. u_char n ; /* usage counter */
  193. u_char perm ; /* flag: permanent */
  194. } table[FPMAX_MULTICAST] ;
  195. } mc ;
  196. struct fddi_addr group_addr ;
  197. u_long func_addr ; /* functional address */
  198. int smt_slots_used ; /* count of table entries for the SMT */
  199. int os_slots_used ; /* count of table entries */
  200. /* used by the os-specific module */
  201. } ;
  202. /*
  203. * modes for mac_set_rx_mode()
  204. */
  205. #define RX_ENABLE_ALLMULTI 1 /* enable all multicasts */
  206. #define RX_DISABLE_ALLMULTI 2 /* disable "enable all multicasts" */
  207. #define RX_ENABLE_PROMISC 3 /* enable promiscuous */
  208. #define RX_DISABLE_PROMISC 4 /* disable promiscuous */
  209. #define RX_ENABLE_NSA 5 /* enable reception of NSA frames */
  210. #define RX_DISABLE_NSA 6 /* disable reception of NSA frames */
  211. /*
  212. * support for byte reversal in AIX
  213. * (descriptors and pointers must be byte reversed in memory
  214. * CPU is big endian; M-Channel is little endian)
  215. */
  216. #ifdef AIX
  217. #define MDR_REV
  218. #define AIX_REVERSE(x) ((((x)<<24L)&0xff000000L) + \
  219. (((x)<< 8L)&0x00ff0000L) + \
  220. (((x)>> 8L)&0x0000ff00L) + \
  221. (((x)>>24L)&0x000000ffL))
  222. #else
  223. #ifndef AIX_REVERSE
  224. #define AIX_REVERSE(x) (x)
  225. #endif
  226. #endif
  227. #ifdef MDR_REV
  228. #define MDR_REVERSE(x) ((((x)<<24L)&0xff000000L) + \
  229. (((x)<< 8L)&0x00ff0000L) + \
  230. (((x)>> 8L)&0x0000ff00L) + \
  231. (((x)>>24L)&0x000000ffL))
  232. #else
  233. #ifndef MDR_REVERSE
  234. #define MDR_REVERSE(x) (x)
  235. #endif
  236. #endif
  237. #endif