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/drivers/net/hamradio/z8530.h

http://github.com/mirrors/linux
C Header | 246 lines | 169 code | 43 blank | 34 comment | 0 complexity | 9612667e1856c8f3ac07ebc5ec7727fb MD5 | raw file
  1/* SPDX-License-Identifier: GPL-2.0 */
  2
  3/* 8530 Serial Communications Controller Register definitions */
  4#define	FLAG	0x7e
  5
  6/* Write Register 0 */
  7#define	R0	0		/* Register selects */
  8#define	R1	1
  9#define	R2	2
 10#define	R3	3
 11#define	R4	4
 12#define	R5	5
 13#define	R6	6
 14#define	R7	7
 15#define	R8	8
 16#define	R9	9
 17#define	R10	10
 18#define	R11	11
 19#define	R12	12
 20#define	R13	13
 21#define	R14	14
 22#define	R15	15
 23
 24#define	NULLCODE	0	/* Null Code */
 25#define	POINT_HIGH	0x8	/* Select upper half of registers */
 26#define	RES_EXT_INT	0x10	/* Reset Ext. Status Interrupts */
 27#define	SEND_ABORT	0x18	/* HDLC Abort */
 28#define	RES_RxINT_FC	0x20	/* Reset RxINT on First Character */
 29#define	RES_Tx_P	0x28	/* Reset TxINT Pending */
 30#define	ERR_RES		0x30	/* Error Reset */
 31#define	RES_H_IUS	0x38	/* Reset highest IUS */
 32
 33#define	RES_Rx_CRC	0x40	/* Reset Rx CRC Checker */
 34#define	RES_Tx_CRC	0x80	/* Reset Tx CRC Checker */
 35#define	RES_EOM_L	0xC0	/* Reset EOM latch */
 36
 37/* Write Register 1 */
 38
 39#define	EXT_INT_ENAB	0x1	/* Ext Int Enable */
 40#define	TxINT_ENAB	0x2	/* Tx Int Enable */
 41#define	PAR_SPEC	0x4	/* Parity is special condition */
 42
 43#define	RxINT_DISAB	0	/* Rx Int Disable */
 44#define	RxINT_FCERR	0x8	/* Rx Int on First Character Only or Error */
 45#define	INT_ALL_Rx	0x10	/* Int on all Rx Characters or error */
 46#define	INT_ERR_Rx	0x18	/* Int on error only */
 47
 48#define	WT_RDY_RT	0x20	/* Wait/Ready on R/T */
 49#define	WT_FN_RDYFN	0x40	/* Wait/FN/Ready FN */
 50#define	WT_RDY_ENAB	0x80	/* Wait/Ready Enable */
 51
 52/* Write Register #2 (Interrupt Vector) */
 53
 54/* Write Register 3 */
 55
 56#define	RxENABLE	0x1	/* Rx Enable */
 57#define	SYNC_L_INH	0x2	/* Sync Character Load Inhibit */
 58#define	ADD_SM		0x4	/* Address Search Mode (SDLC) */
 59#define	RxCRC_ENAB	0x8	/* Rx CRC Enable */
 60#define	ENT_HM		0x10	/* Enter Hunt Mode */
 61#define	AUTO_ENAB	0x20	/* Auto Enables */
 62#define	Rx5		0x0	/* Rx 5 Bits/Character */
 63#define	Rx7		0x40	/* Rx 7 Bits/Character */
 64#define	Rx6		0x80	/* Rx 6 Bits/Character */
 65#define	Rx8		0xc0	/* Rx 8 Bits/Character */
 66
 67/* Write Register 4 */
 68
 69#define	PAR_ENA		0x1	/* Parity Enable */
 70#define	PAR_EVEN	0x2	/* Parity Even/Odd* */
 71
 72#define	SYNC_ENAB	0	/* Sync Modes Enable */
 73#define	SB1		0x4	/* 1 stop bit/char */
 74#define	SB15		0x8	/* 1.5 stop bits/char */
 75#define	SB2		0xc	/* 2 stop bits/char */
 76
 77#define	MONSYNC		0	/* 8 Bit Sync character */
 78#define	BISYNC		0x10	/* 16 bit sync character */
 79#define	SDLC		0x20	/* SDLC Mode (01111110 Sync Flag) */
 80#define	EXTSYNC		0x30	/* External Sync Mode */
 81
 82#define	X1CLK		0x0	/* x1 clock mode */
 83#define	X16CLK		0x40	/* x16 clock mode */
 84#define	X32CLK		0x80	/* x32 clock mode */
 85#define	X64CLK		0xC0	/* x64 clock mode */
 86
 87/* Write Register 5 */
 88
 89#define	TxCRC_ENAB	0x1	/* Tx CRC Enable */
 90#define	RTS		0x2	/* RTS */
 91#define	SDLC_CRC	0x4	/* SDLC/CRC-16 */
 92#define	TxENAB		0x8	/* Tx Enable */
 93#define	SND_BRK		0x10	/* Send Break */
 94#define	Tx5		0x0	/* Tx 5 bits (or less)/character */
 95#define	Tx7		0x20	/* Tx 7 bits/character */
 96#define	Tx6		0x40	/* Tx 6 bits/character */
 97#define	Tx8		0x60	/* Tx 8 bits/character */
 98#define	DTR		0x80	/* DTR */
 99
100/* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
101
102/* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
103
104/* Write Register 8 (transmit buffer) */
105
106/* Write Register 9 (Master interrupt control) */
107#define	VIS	1	/* Vector Includes Status */
108#define	NV	2	/* No Vector */
109#define	DLC	4	/* Disable Lower Chain */
110#define	MIE	8	/* Master Interrupt Enable */
111#define	STATHI	0x10	/* Status high */
112#define	NORESET	0	/* No reset on write to R9 */
113#define	CHRB	0x40	/* Reset channel B */
114#define	CHRA	0x80	/* Reset channel A */
115#define	FHWRES	0xc0	/* Force hardware reset */
116
117/* Write Register 10 (misc control bits) */
118#define	BIT6	1	/* 6 bit/8bit sync */
119#define	LOOPMODE 2	/* SDLC Loop mode */
120#define	ABUNDER	4	/* Abort/flag on SDLC xmit underrun */
121#define	MARKIDLE 8	/* Mark/flag on idle */
122#define	GAOP	0x10	/* Go active on poll */
123#define	NRZ	0	/* NRZ mode */
124#define	NRZI	0x20	/* NRZI mode */
125#define	FM1	0x40	/* FM1 (transition = 1) */
126#define	FM0	0x60	/* FM0 (transition = 0) */
127#define	CRCPS	0x80	/* CRC Preset I/O */
128
129/* Write Register 11 (Clock Mode control) */
130#define	TRxCXT	0	/* TRxC = Xtal output */
131#define	TRxCTC	1	/* TRxC = Transmit clock */
132#define	TRxCBR	2	/* TRxC = BR Generator Output */
133#define	TRxCDP	3	/* TRxC = DPLL output */
134#define	TRxCOI	4	/* TRxC O/I */
135#define	TCRTxCP	0	/* Transmit clock = RTxC pin */
136#define	TCTRxCP	8	/* Transmit clock = TRxC pin */
137#define	TCBR	0x10	/* Transmit clock = BR Generator output */
138#define	TCDPLL	0x18	/* Transmit clock = DPLL output */
139#define	RCRTxCP	0	/* Receive clock = RTxC pin */
140#define	RCTRxCP	0x20	/* Receive clock = TRxC pin */
141#define	RCBR	0x40	/* Receive clock = BR Generator output */
142#define	RCDPLL	0x60	/* Receive clock = DPLL output */
143#define	RTxCX	0x80	/* RTxC Xtal/No Xtal */
144
145/* Write Register 12 (lower byte of baud rate generator time constant) */
146
147/* Write Register 13 (upper byte of baud rate generator time constant) */
148
149/* Write Register 14 (Misc control bits) */
150#define	BRENABL	1	/* Baud rate generator enable */
151#define	BRSRC	2	/* Baud rate generator source */
152#define	DTRREQ	4	/* DTR/Request function */
153#define	AUTOECHO 8	/* Auto Echo */
154#define	LOOPBAK	0x10	/* Local loopback */
155#define	SEARCH	0x20	/* Enter search mode */
156#define	RMC	0x40	/* Reset missing clock */
157#define	DISDPLL	0x60	/* Disable DPLL */
158#define	SSBR	0x80	/* Set DPLL source = BR generator */
159#define	SSRTxC	0xa0	/* Set DPLL source = RTxC */
160#define	SFMM	0xc0	/* Set FM mode */
161#define	SNRZI	0xe0	/* Set NRZI mode */
162
163/* Write Register 15 (external/status interrupt control) */
164#define	ZCIE	2	/* Zero count IE */
165#define	DCDIE	8	/* DCD IE */
166#define	SYNCIE	0x10	/* Sync/hunt IE */
167#define	CTSIE	0x20	/* CTS IE */
168#define	TxUIE	0x40	/* Tx Underrun/EOM IE */
169#define	BRKIE	0x80	/* Break/Abort IE */
170
171
172/* Read Register 0 */
173#define	Rx_CH_AV	0x1	/* Rx Character Available */
174#define	ZCOUNT		0x2	/* Zero count */
175#define	Tx_BUF_EMP	0x4	/* Tx Buffer empty */
176#define	DCD		0x8	/* DCD */
177#define	SYNC_HUNT	0x10	/* Sync/hunt */
178#define	CTS		0x20	/* CTS */
179#define	TxEOM		0x40	/* Tx underrun */
180#define	BRK_ABRT	0x80	/* Break/Abort */
181
182/* Read Register 1 */
183#define	ALL_SNT		0x1	/* All sent */
184/* Residue Data for 8 Rx bits/char programmed */
185#define	RES3		0x8	/* 0/3 */
186#define	RES4		0x4	/* 0/4 */
187#define	RES5		0xc	/* 0/5 */
188#define	RES6		0x2	/* 0/6 */
189#define	RES7		0xa	/* 0/7 */
190#define	RES8		0x6	/* 0/8 */
191#define	RES18		0xe	/* 1/8 */
192#define	RES28		0x0	/* 2/8 */
193/* Special Rx Condition Interrupts */
194#define	PAR_ERR		0x10	/* Parity error */
195#define	Rx_OVR		0x20	/* Rx Overrun Error */
196#define	CRC_ERR		0x40	/* CRC/Framing Error */
197#define	END_FR		0x80	/* End of Frame (SDLC) */
198
199/* Read Register 2 (channel b only) - Interrupt vector */
200
201/* Read Register 3 (interrupt pending register) ch a only */
202#define	CHBEXT	0x1		/* Channel B Ext/Stat IP */
203#define	CHBTxIP	0x2		/* Channel B Tx IP */
204#define	CHBRxIP	0x4		/* Channel B Rx IP */
205#define	CHAEXT	0x8		/* Channel A Ext/Stat IP */
206#define	CHATxIP	0x10		/* Channel A Tx IP */
207#define	CHARxIP	0x20		/* Channel A Rx IP */
208
209/* Read Register 8 (receive data register) */
210
211/* Read Register 10  (misc status bits) */
212#define	ONLOOP	2		/* On loop */
213#define	LOOPSEND 0x10		/* Loop sending */
214#define	CLK2MIS	0x40		/* Two clocks missing */
215#define	CLK1MIS	0x80		/* One clock missing */
216
217/* Read Register 12 (lower byte of baud rate generator constant) */
218
219/* Read Register 13 (upper byte of baud rate generator constant) */
220
221/* Read Register 15 (value of WR 15) */
222
223/* Z85C30/Z85230 Enhanced SCC register definitions */
224
225/* Write Register 7' (SDLC/HDLC Programmable Enhancements) */
226#define AUTOTXF	0x01		/* Auto Tx Flag */
227#define AUTOEOM 0x02		/* Auto EOM Latch Reset */
228#define AUTORTS	0x04		/* Auto RTS */
229#define TXDNRZI 0x08		/* TxD Pulled High in SDLC NRZI mode */
230#define RXFIFOH 0x08		/* Z85230: Int on RX FIFO half full */
231#define FASTDTR 0x10		/* Fast DTR/REQ Mode */
232#define CRCCBCR	0x20		/* CRC Check Bytes Completely Received */
233#define TXFIFOE 0x20		/* Z85230: Int on TX FIFO completely empty */
234#define EXTRDEN	0x40		/* Extended Read Enabled */
235
236/* Write Register 15 (external/status interrupt control) */
237#define SHDLCE	1		/* SDLC/HDLC Enhancements Enable */
238#define FIFOE	4		/* FIFO Enable */
239
240/* Read Register 6 (frame status FIFO) */
241#define BCLSB	0xff		/* LSB of 14 bits count */
242
243/* Read Register 7 (frame status FIFO) */
244#define BCMSB	0x3f		/* MSB of 14 bits count */
245#define FDA	0x40		/* FIFO Data Available Status */
246#define FOS	0x80		/* FIFO Overflow Status */