/drivers/net/ethernet/jme.h

http://github.com/mirrors/linux · C Header · 1265 lines · 967 code · 152 blank · 146 comment · 7 complexity · 9406327da7221feb5b8806c52f32146e MD5 · raw file

  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
  4. *
  5. * Copyright 2008 JMicron Technology Corporation
  6. * http://www.jmicron.com/
  7. * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
  8. *
  9. * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
  10. */
  11. #ifndef __JME_H_INCLUDED__
  12. #define __JME_H_INCLUDED__
  13. #include <linux/interrupt.h>
  14. #define DRV_NAME "jme"
  15. #define DRV_VERSION "1.0.8"
  16. #define PCI_DEVICE_ID_JMICRON_JMC250 0x0250
  17. #define PCI_DEVICE_ID_JMICRON_JMC260 0x0260
  18. /*
  19. * Message related definitions
  20. */
  21. #define JME_DEF_MSG_ENABLE \
  22. (NETIF_MSG_PROBE | \
  23. NETIF_MSG_LINK | \
  24. NETIF_MSG_RX_ERR | \
  25. NETIF_MSG_TX_ERR | \
  26. NETIF_MSG_HW)
  27. #ifdef TX_DEBUG
  28. #define tx_dbg(priv, fmt, args...) \
  29. printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args)
  30. #else
  31. #define tx_dbg(priv, fmt, args...) \
  32. do { \
  33. if (0) \
  34. printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args); \
  35. } while (0)
  36. #endif
  37. /*
  38. * Extra PCI Configuration space interface
  39. */
  40. #define PCI_DCSR_MRRS 0x59
  41. #define PCI_DCSR_MRRS_MASK 0x70
  42. enum pci_dcsr_mrrs_vals {
  43. MRRS_128B = 0x00,
  44. MRRS_256B = 0x10,
  45. MRRS_512B = 0x20,
  46. MRRS_1024B = 0x30,
  47. MRRS_2048B = 0x40,
  48. MRRS_4096B = 0x50,
  49. };
  50. #define PCI_SPI 0xB0
  51. enum pci_spi_bits {
  52. SPI_EN = 0x10,
  53. SPI_MISO = 0x08,
  54. SPI_MOSI = 0x04,
  55. SPI_SCLK = 0x02,
  56. SPI_CS = 0x01,
  57. };
  58. struct jme_spi_op {
  59. void __user *uwbuf;
  60. void __user *urbuf;
  61. __u8 wn; /* Number of write actions */
  62. __u8 rn; /* Number of read actions */
  63. __u8 bitn; /* Number of bits per action */
  64. __u8 spd; /* The maxim acceptable speed of controller, in MHz.*/
  65. __u8 mode; /* CPOL, CPHA, and Duplex mode of SPI */
  66. /* Internal use only */
  67. u8 *kwbuf;
  68. u8 *krbuf;
  69. u8 sr;
  70. u16 halfclk; /* Half of clock cycle calculated from spd, in ns */
  71. };
  72. enum jme_spi_op_bits {
  73. SPI_MODE_CPHA = 0x01,
  74. SPI_MODE_CPOL = 0x02,
  75. SPI_MODE_DUP = 0x80,
  76. };
  77. #define HALF_US 500 /* 500 ns */
  78. #define PCI_PRIV_PE1 0xE4
  79. enum pci_priv_pe1_bit_masks {
  80. PE1_ASPMSUPRT = 0x00000003, /*
  81. * RW:
  82. * Aspm_support[1:0]
  83. * (R/W Port of 5C[11:10])
  84. */
  85. PE1_MULTIFUN = 0x00000004, /* RW: Multi_fun_bit */
  86. PE1_RDYDMA = 0x00000008, /* RO: ~link.rdy_for_dma */
  87. PE1_ASPMOPTL = 0x00000030, /* RW: link.rx10s_option[1:0] */
  88. PE1_ASPMOPTH = 0x000000C0, /* RW: 10_req=[3]?HW:[2] */
  89. PE1_GPREG0 = 0x0000FF00, /*
  90. * SRW:
  91. * Cfg_gp_reg0
  92. * [7:6] phy_giga BG control
  93. * [5] CREQ_N as CREQ_N1 (CPPE# as CREQ#)
  94. * [4:0] Reserved
  95. */
  96. PE1_GPREG0_PBG = 0x0000C000, /* phy_giga BG control */
  97. PE1_GPREG1 = 0x00FF0000, /* RW: Cfg_gp_reg1 */
  98. PE1_REVID = 0xFF000000, /* RO: Rev ID */
  99. };
  100. enum pci_priv_pe1_values {
  101. PE1_GPREG0_ENBG = 0x00000000, /* en BG */
  102. PE1_GPREG0_PDD3COLD = 0x00004000, /* giga_PD + d3cold */
  103. PE1_GPREG0_PDPCIESD = 0x00008000, /* giga_PD + pcie_shutdown */
  104. PE1_GPREG0_PDPCIEIDDQ = 0x0000C000, /* giga_PD + pcie_iddq */
  105. };
  106. /*
  107. * Dynamic(adaptive)/Static PCC values
  108. */
  109. enum dynamic_pcc_values {
  110. PCC_OFF = 0,
  111. PCC_P1 = 1,
  112. PCC_P2 = 2,
  113. PCC_P3 = 3,
  114. PCC_OFF_TO = 0,
  115. PCC_P1_TO = 1,
  116. PCC_P2_TO = 64,
  117. PCC_P3_TO = 128,
  118. PCC_OFF_CNT = 0,
  119. PCC_P1_CNT = 1,
  120. PCC_P2_CNT = 16,
  121. PCC_P3_CNT = 32,
  122. };
  123. struct dynpcc_info {
  124. unsigned long last_bytes;
  125. unsigned long last_pkts;
  126. unsigned long intr_cnt;
  127. unsigned char cur;
  128. unsigned char attempt;
  129. unsigned char cnt;
  130. };
  131. #define PCC_INTERVAL_US 100000
  132. #define PCC_INTERVAL (HZ / (1000000 / PCC_INTERVAL_US))
  133. #define PCC_P3_THRESHOLD (2 * 1024 * 1024)
  134. #define PCC_P2_THRESHOLD 800
  135. #define PCC_INTR_THRESHOLD 800
  136. #define PCC_TX_TO 1000
  137. #define PCC_TX_CNT 8
  138. /*
  139. * TX/RX Descriptors
  140. *
  141. * TX/RX Ring DESC Count Must be multiple of 16 and <= 1024
  142. */
  143. #define RING_DESC_ALIGN 16 /* Descriptor alignment */
  144. #define TX_DESC_SIZE 16
  145. #define TX_RING_NR 8
  146. #define TX_RING_ALLOC_SIZE(s) ((s * TX_DESC_SIZE) + RING_DESC_ALIGN)
  147. struct txdesc {
  148. union {
  149. __u8 all[16];
  150. __le32 dw[4];
  151. struct {
  152. /* DW0 */
  153. __le16 vlan;
  154. __u8 rsv1;
  155. __u8 flags;
  156. /* DW1 */
  157. __le16 datalen;
  158. __le16 mss;
  159. /* DW2 */
  160. __le16 pktsize;
  161. __le16 rsv2;
  162. /* DW3 */
  163. __le32 bufaddr;
  164. } desc1;
  165. struct {
  166. /* DW0 */
  167. __le16 rsv1;
  168. __u8 rsv2;
  169. __u8 flags;
  170. /* DW1 */
  171. __le16 datalen;
  172. __le16 rsv3;
  173. /* DW2 */
  174. __le32 bufaddrh;
  175. /* DW3 */
  176. __le32 bufaddrl;
  177. } desc2;
  178. struct {
  179. /* DW0 */
  180. __u8 ehdrsz;
  181. __u8 rsv1;
  182. __u8 rsv2;
  183. __u8 flags;
  184. /* DW1 */
  185. __le16 trycnt;
  186. __le16 segcnt;
  187. /* DW2 */
  188. __le16 pktsz;
  189. __le16 rsv3;
  190. /* DW3 */
  191. __le32 bufaddrl;
  192. } descwb;
  193. };
  194. };
  195. enum jme_txdesc_flags_bits {
  196. TXFLAG_OWN = 0x80,
  197. TXFLAG_INT = 0x40,
  198. TXFLAG_64BIT = 0x20,
  199. TXFLAG_TCPCS = 0x10,
  200. TXFLAG_UDPCS = 0x08,
  201. TXFLAG_IPCS = 0x04,
  202. TXFLAG_LSEN = 0x02,
  203. TXFLAG_TAGON = 0x01,
  204. };
  205. #define TXDESC_MSS_SHIFT 2
  206. enum jme_txwbdesc_flags_bits {
  207. TXWBFLAG_OWN = 0x80,
  208. TXWBFLAG_INT = 0x40,
  209. TXWBFLAG_TMOUT = 0x20,
  210. TXWBFLAG_TRYOUT = 0x10,
  211. TXWBFLAG_COL = 0x08,
  212. TXWBFLAG_ALLERR = TXWBFLAG_TMOUT |
  213. TXWBFLAG_TRYOUT |
  214. TXWBFLAG_COL,
  215. };
  216. #define RX_DESC_SIZE 16
  217. #define RX_RING_NR 4
  218. #define RX_RING_ALLOC_SIZE(s) ((s * RX_DESC_SIZE) + RING_DESC_ALIGN)
  219. #define RX_BUF_DMA_ALIGN 8
  220. #define RX_PREPAD_SIZE 10
  221. #define ETH_CRC_LEN 2
  222. #define RX_VLANHDR_LEN 2
  223. #define RX_EXTRA_LEN (RX_PREPAD_SIZE + \
  224. ETH_HLEN + \
  225. ETH_CRC_LEN + \
  226. RX_VLANHDR_LEN + \
  227. RX_BUF_DMA_ALIGN)
  228. struct rxdesc {
  229. union {
  230. __u8 all[16];
  231. __le32 dw[4];
  232. struct {
  233. /* DW0 */
  234. __le16 rsv2;
  235. __u8 rsv1;
  236. __u8 flags;
  237. /* DW1 */
  238. __le16 datalen;
  239. __le16 wbcpl;
  240. /* DW2 */
  241. __le32 bufaddrh;
  242. /* DW3 */
  243. __le32 bufaddrl;
  244. } desc1;
  245. struct {
  246. /* DW0 */
  247. __le16 vlan;
  248. __le16 flags;
  249. /* DW1 */
  250. __le16 framesize;
  251. __u8 errstat;
  252. __u8 desccnt;
  253. /* DW2 */
  254. __le32 rsshash;
  255. /* DW3 */
  256. __u8 hashfun;
  257. __u8 hashtype;
  258. __le16 resrv;
  259. } descwb;
  260. };
  261. };
  262. enum jme_rxdesc_flags_bits {
  263. RXFLAG_OWN = 0x80,
  264. RXFLAG_INT = 0x40,
  265. RXFLAG_64BIT = 0x20,
  266. };
  267. enum jme_rxwbdesc_flags_bits {
  268. RXWBFLAG_OWN = 0x8000,
  269. RXWBFLAG_INT = 0x4000,
  270. RXWBFLAG_MF = 0x2000,
  271. RXWBFLAG_64BIT = 0x2000,
  272. RXWBFLAG_TCPON = 0x1000,
  273. RXWBFLAG_UDPON = 0x0800,
  274. RXWBFLAG_IPCS = 0x0400,
  275. RXWBFLAG_TCPCS = 0x0200,
  276. RXWBFLAG_UDPCS = 0x0100,
  277. RXWBFLAG_TAGON = 0x0080,
  278. RXWBFLAG_IPV4 = 0x0040,
  279. RXWBFLAG_IPV6 = 0x0020,
  280. RXWBFLAG_PAUSE = 0x0010,
  281. RXWBFLAG_MAGIC = 0x0008,
  282. RXWBFLAG_WAKEUP = 0x0004,
  283. RXWBFLAG_DEST = 0x0003,
  284. RXWBFLAG_DEST_UNI = 0x0001,
  285. RXWBFLAG_DEST_MUL = 0x0002,
  286. RXWBFLAG_DEST_BRO = 0x0003,
  287. };
  288. enum jme_rxwbdesc_desccnt_mask {
  289. RXWBDCNT_WBCPL = 0x80,
  290. RXWBDCNT_DCNT = 0x7F,
  291. };
  292. enum jme_rxwbdesc_errstat_bits {
  293. RXWBERR_LIMIT = 0x80,
  294. RXWBERR_MIIER = 0x40,
  295. RXWBERR_NIBON = 0x20,
  296. RXWBERR_COLON = 0x10,
  297. RXWBERR_ABORT = 0x08,
  298. RXWBERR_SHORT = 0x04,
  299. RXWBERR_OVERUN = 0x02,
  300. RXWBERR_CRCERR = 0x01,
  301. RXWBERR_ALLERR = 0xFF,
  302. };
  303. /*
  304. * Buffer information corresponding to ring descriptors.
  305. */
  306. struct jme_buffer_info {
  307. struct sk_buff *skb;
  308. dma_addr_t mapping;
  309. int len;
  310. int nr_desc;
  311. unsigned long start_xmit;
  312. };
  313. /*
  314. * The structure holding buffer information and ring descriptors all together.
  315. */
  316. struct jme_ring {
  317. void *alloc; /* pointer to allocated memory */
  318. void *desc; /* pointer to ring memory */
  319. dma_addr_t dmaalloc; /* phys address of ring alloc */
  320. dma_addr_t dma; /* phys address for ring dma */
  321. /* Buffer information corresponding to each descriptor */
  322. struct jme_buffer_info *bufinf;
  323. int next_to_use;
  324. atomic_t next_to_clean;
  325. atomic_t nr_free;
  326. };
  327. #define NET_STAT(priv) (priv->dev->stats)
  328. #define NETDEV_GET_STATS(netdev, fun_ptr)
  329. #define DECLARE_NET_DEVICE_STATS
  330. #define DECLARE_NAPI_STRUCT struct napi_struct napi;
  331. #define NETIF_NAPI_SET(dev, napis, pollfn, q) \
  332. netif_napi_add(dev, napis, pollfn, q);
  333. #define JME_NAPI_HOLDER(holder) struct napi_struct *holder
  334. #define JME_NAPI_WEIGHT(w) int w
  335. #define JME_NAPI_WEIGHT_VAL(w) w
  336. #define JME_NAPI_WEIGHT_SET(w, r)
  337. #define JME_RX_COMPLETE(dev, napis) napi_complete(napis)
  338. #define JME_NAPI_ENABLE(priv) napi_enable(&priv->napi);
  339. #define JME_NAPI_DISABLE(priv) \
  340. if (!napi_disable_pending(&priv->napi)) \
  341. napi_disable(&priv->napi);
  342. #define JME_RX_SCHEDULE_PREP(priv) \
  343. napi_schedule_prep(&priv->napi)
  344. #define JME_RX_SCHEDULE(priv) \
  345. __napi_schedule(&priv->napi);
  346. /*
  347. * Jmac Adapter Private data
  348. */
  349. struct jme_adapter {
  350. struct pci_dev *pdev;
  351. struct net_device *dev;
  352. void __iomem *regs;
  353. struct mii_if_info mii_if;
  354. struct jme_ring rxring[RX_RING_NR];
  355. struct jme_ring txring[TX_RING_NR];
  356. spinlock_t phy_lock;
  357. spinlock_t macaddr_lock;
  358. spinlock_t rxmcs_lock;
  359. struct tasklet_struct rxempty_task;
  360. struct tasklet_struct rxclean_task;
  361. struct tasklet_struct txclean_task;
  362. struct tasklet_struct linkch_task;
  363. struct tasklet_struct pcc_task;
  364. unsigned long flags;
  365. u32 reg_txcs;
  366. u32 reg_txpfc;
  367. u32 reg_rxcs;
  368. u32 reg_rxmcs;
  369. u32 reg_ghc;
  370. u32 reg_pmcs;
  371. u32 reg_gpreg1;
  372. u32 phylink;
  373. u32 tx_ring_size;
  374. u32 tx_ring_mask;
  375. u32 tx_wake_threshold;
  376. u32 rx_ring_size;
  377. u32 rx_ring_mask;
  378. u8 mrrs;
  379. unsigned int fpgaver;
  380. u8 chiprev;
  381. u8 chip_main_rev;
  382. u8 chip_sub_rev;
  383. u8 pcirev;
  384. u32 msg_enable;
  385. struct ethtool_link_ksettings old_cmd;
  386. unsigned int old_mtu;
  387. struct dynpcc_info dpi;
  388. atomic_t intr_sem;
  389. atomic_t link_changing;
  390. atomic_t tx_cleaning;
  391. atomic_t rx_cleaning;
  392. atomic_t rx_empty;
  393. int (*jme_rx)(struct sk_buff *skb);
  394. DECLARE_NAPI_STRUCT
  395. DECLARE_NET_DEVICE_STATS
  396. };
  397. enum jme_flags_bits {
  398. JME_FLAG_MSI = 1,
  399. JME_FLAG_SSET = 2,
  400. JME_FLAG_POLL = 5,
  401. JME_FLAG_SHUTDOWN = 6,
  402. };
  403. #define TX_TIMEOUT (5 * HZ)
  404. #define JME_REG_LEN 0x500
  405. #define MAX_ETHERNET_JUMBO_PACKET_SIZE 9216
  406. static inline struct jme_adapter*
  407. jme_napi_priv(struct napi_struct *napi)
  408. {
  409. struct jme_adapter *jme;
  410. jme = container_of(napi, struct jme_adapter, napi);
  411. return jme;
  412. }
  413. /*
  414. * MMaped I/O Resters
  415. */
  416. enum jme_iomap_offsets {
  417. JME_MAC = 0x0000,
  418. JME_PHY = 0x0400,
  419. JME_MISC = 0x0800,
  420. JME_RSS = 0x0C00,
  421. };
  422. enum jme_iomap_lens {
  423. JME_MAC_LEN = 0x80,
  424. JME_PHY_LEN = 0x58,
  425. JME_MISC_LEN = 0x98,
  426. JME_RSS_LEN = 0xFF,
  427. };
  428. enum jme_iomap_regs {
  429. JME_TXCS = JME_MAC | 0x00, /* Transmit Control and Status */
  430. JME_TXDBA_LO = JME_MAC | 0x04, /* Transmit Queue Desc Base Addr */
  431. JME_TXDBA_HI = JME_MAC | 0x08, /* Transmit Queue Desc Base Addr */
  432. JME_TXQDC = JME_MAC | 0x0C, /* Transmit Queue Desc Count */
  433. JME_TXNDA = JME_MAC | 0x10, /* Transmit Queue Next Desc Addr */
  434. JME_TXMCS = JME_MAC | 0x14, /* Transmit MAC Control Status */
  435. JME_TXPFC = JME_MAC | 0x18, /* Transmit Pause Frame Control */
  436. JME_TXTRHD = JME_MAC | 0x1C, /* Transmit Timer/Retry@Half-Dup */
  437. JME_RXCS = JME_MAC | 0x20, /* Receive Control and Status */
  438. JME_RXDBA_LO = JME_MAC | 0x24, /* Receive Queue Desc Base Addr */
  439. JME_RXDBA_HI = JME_MAC | 0x28, /* Receive Queue Desc Base Addr */
  440. JME_RXQDC = JME_MAC | 0x2C, /* Receive Queue Desc Count */
  441. JME_RXNDA = JME_MAC | 0x30, /* Receive Queue Next Desc Addr */
  442. JME_RXMCS = JME_MAC | 0x34, /* Receive MAC Control Status */
  443. JME_RXUMA_LO = JME_MAC | 0x38, /* Receive Unicast MAC Address */
  444. JME_RXUMA_HI = JME_MAC | 0x3C, /* Receive Unicast MAC Address */
  445. JME_RXMCHT_LO = JME_MAC | 0x40, /* Recv Multicast Addr HashTable */
  446. JME_RXMCHT_HI = JME_MAC | 0x44, /* Recv Multicast Addr HashTable */
  447. JME_WFODP = JME_MAC | 0x48, /* Wakeup Frame Output Data Port */
  448. JME_WFOI = JME_MAC | 0x4C, /* Wakeup Frame Output Interface */
  449. JME_SMI = JME_MAC | 0x50, /* Station Management Interface */
  450. JME_GHC = JME_MAC | 0x54, /* Global Host Control */
  451. JME_PMCS = JME_MAC | 0x60, /* Power Management Control/Stat */
  452. JME_PHY_PWR = JME_PHY | 0x24, /* New PHY Power Ctrl Register */
  453. JME_PHY_CS = JME_PHY | 0x28, /* PHY Ctrl and Status Register */
  454. JME_PHY_LINK = JME_PHY | 0x30, /* PHY Link Status Register */
  455. JME_SMBCSR = JME_PHY | 0x40, /* SMB Control and Status */
  456. JME_SMBINTF = JME_PHY | 0x44, /* SMB Interface */
  457. JME_TMCSR = JME_MISC | 0x00, /* Timer Control/Status Register */
  458. JME_GPREG0 = JME_MISC | 0x08, /* General purpose REG-0 */
  459. JME_GPREG1 = JME_MISC | 0x0C, /* General purpose REG-1 */
  460. JME_IEVE = JME_MISC | 0x20, /* Interrupt Event Status */
  461. JME_IREQ = JME_MISC | 0x24, /* Intr Req Status(For Debug) */
  462. JME_IENS = JME_MISC | 0x28, /* Intr Enable - Setting Port */
  463. JME_IENC = JME_MISC | 0x2C, /* Interrupt Enable - Clear Port */
  464. JME_PCCRX0 = JME_MISC | 0x30, /* PCC Control for RX Queue 0 */
  465. JME_PCCTX = JME_MISC | 0x40, /* PCC Control for TX Queues */
  466. JME_CHIPMODE = JME_MISC | 0x44, /* Identify FPGA Version */
  467. JME_SHBA_HI = JME_MISC | 0x48, /* Shadow Register Base HI */
  468. JME_SHBA_LO = JME_MISC | 0x4C, /* Shadow Register Base LO */
  469. JME_TIMER1 = JME_MISC | 0x70, /* Timer1 */
  470. JME_TIMER2 = JME_MISC | 0x74, /* Timer2 */
  471. JME_APMC = JME_MISC | 0x7C, /* Aggressive Power Mode Control */
  472. JME_PCCSRX0 = JME_MISC | 0x80, /* PCC Status of RX0 */
  473. };
  474. /*
  475. * TX Control/Status Bits
  476. */
  477. enum jme_txcs_bits {
  478. TXCS_QUEUE7S = 0x00008000,
  479. TXCS_QUEUE6S = 0x00004000,
  480. TXCS_QUEUE5S = 0x00002000,
  481. TXCS_QUEUE4S = 0x00001000,
  482. TXCS_QUEUE3S = 0x00000800,
  483. TXCS_QUEUE2S = 0x00000400,
  484. TXCS_QUEUE1S = 0x00000200,
  485. TXCS_QUEUE0S = 0x00000100,
  486. TXCS_FIFOTH = 0x000000C0,
  487. TXCS_DMASIZE = 0x00000030,
  488. TXCS_BURST = 0x00000004,
  489. TXCS_ENABLE = 0x00000001,
  490. };
  491. enum jme_txcs_value {
  492. TXCS_FIFOTH_16QW = 0x000000C0,
  493. TXCS_FIFOTH_12QW = 0x00000080,
  494. TXCS_FIFOTH_8QW = 0x00000040,
  495. TXCS_FIFOTH_4QW = 0x00000000,
  496. TXCS_DMASIZE_64B = 0x00000000,
  497. TXCS_DMASIZE_128B = 0x00000010,
  498. TXCS_DMASIZE_256B = 0x00000020,
  499. TXCS_DMASIZE_512B = 0x00000030,
  500. TXCS_SELECT_QUEUE0 = 0x00000000,
  501. TXCS_SELECT_QUEUE1 = 0x00010000,
  502. TXCS_SELECT_QUEUE2 = 0x00020000,
  503. TXCS_SELECT_QUEUE3 = 0x00030000,
  504. TXCS_SELECT_QUEUE4 = 0x00040000,
  505. TXCS_SELECT_QUEUE5 = 0x00050000,
  506. TXCS_SELECT_QUEUE6 = 0x00060000,
  507. TXCS_SELECT_QUEUE7 = 0x00070000,
  508. TXCS_DEFAULT = TXCS_FIFOTH_4QW |
  509. TXCS_BURST,
  510. };
  511. #define JME_TX_DISABLE_TIMEOUT 10 /* 10 msec */
  512. /*
  513. * TX MAC Control/Status Bits
  514. */
  515. enum jme_txmcs_bit_masks {
  516. TXMCS_IFG2 = 0xC0000000,
  517. TXMCS_IFG1 = 0x30000000,
  518. TXMCS_TTHOLD = 0x00000300,
  519. TXMCS_FBURST = 0x00000080,
  520. TXMCS_CARRIEREXT = 0x00000040,
  521. TXMCS_DEFER = 0x00000020,
  522. TXMCS_BACKOFF = 0x00000010,
  523. TXMCS_CARRIERSENSE = 0x00000008,
  524. TXMCS_COLLISION = 0x00000004,
  525. TXMCS_CRC = 0x00000002,
  526. TXMCS_PADDING = 0x00000001,
  527. };
  528. enum jme_txmcs_values {
  529. TXMCS_IFG2_6_4 = 0x00000000,
  530. TXMCS_IFG2_8_5 = 0x40000000,
  531. TXMCS_IFG2_10_6 = 0x80000000,
  532. TXMCS_IFG2_12_7 = 0xC0000000,
  533. TXMCS_IFG1_8_4 = 0x00000000,
  534. TXMCS_IFG1_12_6 = 0x10000000,
  535. TXMCS_IFG1_16_8 = 0x20000000,
  536. TXMCS_IFG1_20_10 = 0x30000000,
  537. TXMCS_TTHOLD_1_8 = 0x00000000,
  538. TXMCS_TTHOLD_1_4 = 0x00000100,
  539. TXMCS_TTHOLD_1_2 = 0x00000200,
  540. TXMCS_TTHOLD_FULL = 0x00000300,
  541. TXMCS_DEFAULT = TXMCS_IFG2_8_5 |
  542. TXMCS_IFG1_16_8 |
  543. TXMCS_TTHOLD_FULL |
  544. TXMCS_DEFER |
  545. TXMCS_CRC |
  546. TXMCS_PADDING,
  547. };
  548. enum jme_txpfc_bits_masks {
  549. TXPFC_VLAN_TAG = 0xFFFF0000,
  550. TXPFC_VLAN_EN = 0x00008000,
  551. TXPFC_PF_EN = 0x00000001,
  552. };
  553. enum jme_txtrhd_bits_masks {
  554. TXTRHD_TXPEN = 0x80000000,
  555. TXTRHD_TXP = 0x7FFFFF00,
  556. TXTRHD_TXREN = 0x00000080,
  557. TXTRHD_TXRL = 0x0000007F,
  558. };
  559. enum jme_txtrhd_shifts {
  560. TXTRHD_TXP_SHIFT = 8,
  561. TXTRHD_TXRL_SHIFT = 0,
  562. };
  563. enum jme_txtrhd_values {
  564. TXTRHD_FULLDUPLEX = 0x00000000,
  565. TXTRHD_HALFDUPLEX = TXTRHD_TXPEN |
  566. ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
  567. TXTRHD_TXREN |
  568. ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL),
  569. };
  570. /*
  571. * RX Control/Status Bits
  572. */
  573. enum jme_rxcs_bit_masks {
  574. /* FIFO full threshold for transmitting Tx Pause Packet */
  575. RXCS_FIFOTHTP = 0x30000000,
  576. /* FIFO threshold for processing next packet */
  577. RXCS_FIFOTHNP = 0x0C000000,
  578. RXCS_DMAREQSZ = 0x03000000, /* DMA Request Size */
  579. RXCS_QUEUESEL = 0x00030000, /* Queue selection */
  580. RXCS_RETRYGAP = 0x0000F000, /* RX Desc full retry gap */
  581. RXCS_RETRYCNT = 0x00000F00, /* RX Desc full retry counter */
  582. RXCS_WAKEUP = 0x00000040, /* Enable receive wakeup packet */
  583. RXCS_MAGIC = 0x00000020, /* Enable receive magic packet */
  584. RXCS_SHORT = 0x00000010, /* Enable receive short packet */
  585. RXCS_ABORT = 0x00000008, /* Enable receive errorr packet */
  586. RXCS_QST = 0x00000004, /* Receive queue start */
  587. RXCS_SUSPEND = 0x00000002,
  588. RXCS_ENABLE = 0x00000001,
  589. };
  590. enum jme_rxcs_values {
  591. RXCS_FIFOTHTP_16T = 0x00000000,
  592. RXCS_FIFOTHTP_32T = 0x10000000,
  593. RXCS_FIFOTHTP_64T = 0x20000000,
  594. RXCS_FIFOTHTP_128T = 0x30000000,
  595. RXCS_FIFOTHNP_16QW = 0x00000000,
  596. RXCS_FIFOTHNP_32QW = 0x04000000,
  597. RXCS_FIFOTHNP_64QW = 0x08000000,
  598. RXCS_FIFOTHNP_128QW = 0x0C000000,
  599. RXCS_DMAREQSZ_16B = 0x00000000,
  600. RXCS_DMAREQSZ_32B = 0x01000000,
  601. RXCS_DMAREQSZ_64B = 0x02000000,
  602. RXCS_DMAREQSZ_128B = 0x03000000,
  603. RXCS_QUEUESEL_Q0 = 0x00000000,
  604. RXCS_QUEUESEL_Q1 = 0x00010000,
  605. RXCS_QUEUESEL_Q2 = 0x00020000,
  606. RXCS_QUEUESEL_Q3 = 0x00030000,
  607. RXCS_RETRYGAP_256ns = 0x00000000,
  608. RXCS_RETRYGAP_512ns = 0x00001000,
  609. RXCS_RETRYGAP_1024ns = 0x00002000,
  610. RXCS_RETRYGAP_2048ns = 0x00003000,
  611. RXCS_RETRYGAP_4096ns = 0x00004000,
  612. RXCS_RETRYGAP_8192ns = 0x00005000,
  613. RXCS_RETRYGAP_16384ns = 0x00006000,
  614. RXCS_RETRYGAP_32768ns = 0x00007000,
  615. RXCS_RETRYCNT_0 = 0x00000000,
  616. RXCS_RETRYCNT_4 = 0x00000100,
  617. RXCS_RETRYCNT_8 = 0x00000200,
  618. RXCS_RETRYCNT_12 = 0x00000300,
  619. RXCS_RETRYCNT_16 = 0x00000400,
  620. RXCS_RETRYCNT_20 = 0x00000500,
  621. RXCS_RETRYCNT_24 = 0x00000600,
  622. RXCS_RETRYCNT_28 = 0x00000700,
  623. RXCS_RETRYCNT_32 = 0x00000800,
  624. RXCS_RETRYCNT_36 = 0x00000900,
  625. RXCS_RETRYCNT_40 = 0x00000A00,
  626. RXCS_RETRYCNT_44 = 0x00000B00,
  627. RXCS_RETRYCNT_48 = 0x00000C00,
  628. RXCS_RETRYCNT_52 = 0x00000D00,
  629. RXCS_RETRYCNT_56 = 0x00000E00,
  630. RXCS_RETRYCNT_60 = 0x00000F00,
  631. RXCS_DEFAULT = RXCS_FIFOTHTP_128T |
  632. RXCS_FIFOTHNP_16QW |
  633. RXCS_DMAREQSZ_128B |
  634. RXCS_RETRYGAP_256ns |
  635. RXCS_RETRYCNT_32,
  636. };
  637. #define JME_RX_DISABLE_TIMEOUT 10 /* 10 msec */
  638. /*
  639. * RX MAC Control/Status Bits
  640. */
  641. enum jme_rxmcs_bits {
  642. RXMCS_ALLFRAME = 0x00000800,
  643. RXMCS_BRDFRAME = 0x00000400,
  644. RXMCS_MULFRAME = 0x00000200,
  645. RXMCS_UNIFRAME = 0x00000100,
  646. RXMCS_ALLMULFRAME = 0x00000080,
  647. RXMCS_MULFILTERED = 0x00000040,
  648. RXMCS_RXCOLLDEC = 0x00000020,
  649. RXMCS_FLOWCTRL = 0x00000008,
  650. RXMCS_VTAGRM = 0x00000004,
  651. RXMCS_PREPAD = 0x00000002,
  652. RXMCS_CHECKSUM = 0x00000001,
  653. RXMCS_DEFAULT = RXMCS_VTAGRM |
  654. RXMCS_PREPAD |
  655. RXMCS_FLOWCTRL |
  656. RXMCS_CHECKSUM,
  657. };
  658. /* Extern PHY common register 2 */
  659. #define PHY_GAD_TEST_MODE_1 0x00002000
  660. #define PHY_GAD_TEST_MODE_MSK 0x0000E000
  661. #define JM_PHY_SPEC_REG_READ 0x00004000
  662. #define JM_PHY_SPEC_REG_WRITE 0x00008000
  663. #define PHY_CALIBRATION_DELAY 20
  664. #define JM_PHY_SPEC_ADDR_REG 0x1E
  665. #define JM_PHY_SPEC_DATA_REG 0x1F
  666. #define JM_PHY_EXT_COMM_0_REG 0x30
  667. #define JM_PHY_EXT_COMM_1_REG 0x31
  668. #define JM_PHY_EXT_COMM_2_REG 0x32
  669. #define JM_PHY_EXT_COMM_2_CALI_ENABLE 0x01
  670. #define JM_PHY_EXT_COMM_2_CALI_MODE_0 0x02
  671. #define JM_PHY_EXT_COMM_2_CALI_LATCH 0x10
  672. #define PCI_PRIV_SHARE_NICCTRL 0xF5
  673. #define JME_FLAG_PHYEA_ENABLE 0x2
  674. /*
  675. * Wakeup Frame setup interface registers
  676. */
  677. #define WAKEUP_FRAME_NR 8
  678. #define WAKEUP_FRAME_MASK_DWNR 4
  679. enum jme_wfoi_bit_masks {
  680. WFOI_MASK_SEL = 0x00000070,
  681. WFOI_CRC_SEL = 0x00000008,
  682. WFOI_FRAME_SEL = 0x00000007,
  683. };
  684. enum jme_wfoi_shifts {
  685. WFOI_MASK_SHIFT = 4,
  686. };
  687. /*
  688. * SMI Related definitions
  689. */
  690. enum jme_smi_bit_mask {
  691. SMI_DATA_MASK = 0xFFFF0000,
  692. SMI_REG_ADDR_MASK = 0x0000F800,
  693. SMI_PHY_ADDR_MASK = 0x000007C0,
  694. SMI_OP_WRITE = 0x00000020,
  695. /* Set to 1, after req done it'll be cleared to 0 */
  696. SMI_OP_REQ = 0x00000010,
  697. SMI_OP_MDIO = 0x00000008, /* Software assess In/Out */
  698. SMI_OP_MDOE = 0x00000004, /* Software Output Enable */
  699. SMI_OP_MDC = 0x00000002, /* Software CLK Control */
  700. SMI_OP_MDEN = 0x00000001, /* Software access Enable */
  701. };
  702. enum jme_smi_bit_shift {
  703. SMI_DATA_SHIFT = 16,
  704. SMI_REG_ADDR_SHIFT = 11,
  705. SMI_PHY_ADDR_SHIFT = 6,
  706. };
  707. static inline u32 smi_reg_addr(int x)
  708. {
  709. return (x << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK;
  710. }
  711. static inline u32 smi_phy_addr(int x)
  712. {
  713. return (x << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK;
  714. }
  715. #define JME_PHY_TIMEOUT 100 /* 100 msec */
  716. #define JME_PHY_REG_NR 32
  717. /*
  718. * Global Host Control
  719. */
  720. enum jme_ghc_bit_mask {
  721. GHC_SWRST = 0x40000000,
  722. GHC_TO_CLK_SRC = 0x00C00000,
  723. GHC_TXMAC_CLK_SRC = 0x00300000,
  724. GHC_DPX = 0x00000040,
  725. GHC_SPEED = 0x00000030,
  726. GHC_LINK_POLL = 0x00000001,
  727. };
  728. enum jme_ghc_speed_val {
  729. GHC_SPEED_10M = 0x00000010,
  730. GHC_SPEED_100M = 0x00000020,
  731. GHC_SPEED_1000M = 0x00000030,
  732. };
  733. enum jme_ghc_to_clk {
  734. GHC_TO_CLK_OFF = 0x00000000,
  735. GHC_TO_CLK_GPHY = 0x00400000,
  736. GHC_TO_CLK_PCIE = 0x00800000,
  737. GHC_TO_CLK_INVALID = 0x00C00000,
  738. };
  739. enum jme_ghc_txmac_clk {
  740. GHC_TXMAC_CLK_OFF = 0x00000000,
  741. GHC_TXMAC_CLK_GPHY = 0x00100000,
  742. GHC_TXMAC_CLK_PCIE = 0x00200000,
  743. GHC_TXMAC_CLK_INVALID = 0x00300000,
  744. };
  745. /*
  746. * Power management control and status register
  747. */
  748. enum jme_pmcs_bit_masks {
  749. PMCS_STMASK = 0xFFFF0000,
  750. PMCS_WF7DET = 0x80000000,
  751. PMCS_WF6DET = 0x40000000,
  752. PMCS_WF5DET = 0x20000000,
  753. PMCS_WF4DET = 0x10000000,
  754. PMCS_WF3DET = 0x08000000,
  755. PMCS_WF2DET = 0x04000000,
  756. PMCS_WF1DET = 0x02000000,
  757. PMCS_WF0DET = 0x01000000,
  758. PMCS_LFDET = 0x00040000,
  759. PMCS_LRDET = 0x00020000,
  760. PMCS_MFDET = 0x00010000,
  761. PMCS_ENMASK = 0x0000FFFF,
  762. PMCS_WF7EN = 0x00008000,
  763. PMCS_WF6EN = 0x00004000,
  764. PMCS_WF5EN = 0x00002000,
  765. PMCS_WF4EN = 0x00001000,
  766. PMCS_WF3EN = 0x00000800,
  767. PMCS_WF2EN = 0x00000400,
  768. PMCS_WF1EN = 0x00000200,
  769. PMCS_WF0EN = 0x00000100,
  770. PMCS_LFEN = 0x00000004,
  771. PMCS_LREN = 0x00000002,
  772. PMCS_MFEN = 0x00000001,
  773. };
  774. /*
  775. * New PHY Power Control Register
  776. */
  777. enum jme_phy_pwr_bit_masks {
  778. PHY_PWR_DWN1SEL = 0x01000000, /* Phy_giga.p_PWR_DOWN1_SEL */
  779. PHY_PWR_DWN1SW = 0x02000000, /* Phy_giga.p_PWR_DOWN1_SW */
  780. PHY_PWR_DWN2 = 0x04000000, /* Phy_giga.p_PWR_DOWN2 */
  781. PHY_PWR_CLKSEL = 0x08000000, /*
  782. * XTL_OUT Clock select
  783. * (an internal free-running clock)
  784. * 0: xtl_out = phy_giga.A_XTL25_O
  785. * 1: xtl_out = phy_giga.PD_OSC
  786. */
  787. };
  788. /*
  789. * Giga PHY Status Registers
  790. */
  791. enum jme_phy_link_bit_mask {
  792. PHY_LINK_SPEED_MASK = 0x0000C000,
  793. PHY_LINK_DUPLEX = 0x00002000,
  794. PHY_LINK_SPEEDDPU_RESOLVED = 0x00000800,
  795. PHY_LINK_UP = 0x00000400,
  796. PHY_LINK_AUTONEG_COMPLETE = 0x00000200,
  797. PHY_LINK_MDI_STAT = 0x00000040,
  798. };
  799. enum jme_phy_link_speed_val {
  800. PHY_LINK_SPEED_10M = 0x00000000,
  801. PHY_LINK_SPEED_100M = 0x00004000,
  802. PHY_LINK_SPEED_1000M = 0x00008000,
  803. };
  804. #define JME_SPDRSV_TIMEOUT 500 /* 500 us */
  805. /*
  806. * SMB Control and Status
  807. */
  808. enum jme_smbcsr_bit_mask {
  809. SMBCSR_CNACK = 0x00020000,
  810. SMBCSR_RELOAD = 0x00010000,
  811. SMBCSR_EEPROMD = 0x00000020,
  812. SMBCSR_INITDONE = 0x00000010,
  813. SMBCSR_BUSY = 0x0000000F,
  814. };
  815. enum jme_smbintf_bit_mask {
  816. SMBINTF_HWDATR = 0xFF000000,
  817. SMBINTF_HWDATW = 0x00FF0000,
  818. SMBINTF_HWADDR = 0x0000FF00,
  819. SMBINTF_HWRWN = 0x00000020,
  820. SMBINTF_HWCMD = 0x00000010,
  821. SMBINTF_FASTM = 0x00000008,
  822. SMBINTF_GPIOSCL = 0x00000004,
  823. SMBINTF_GPIOSDA = 0x00000002,
  824. SMBINTF_GPIOEN = 0x00000001,
  825. };
  826. enum jme_smbintf_vals {
  827. SMBINTF_HWRWN_READ = 0x00000020,
  828. SMBINTF_HWRWN_WRITE = 0x00000000,
  829. };
  830. enum jme_smbintf_shifts {
  831. SMBINTF_HWDATR_SHIFT = 24,
  832. SMBINTF_HWDATW_SHIFT = 16,
  833. SMBINTF_HWADDR_SHIFT = 8,
  834. };
  835. #define JME_EEPROM_RELOAD_TIMEOUT 2000 /* 2000 msec */
  836. #define JME_SMB_BUSY_TIMEOUT 20 /* 20 msec */
  837. #define JME_SMB_LEN 256
  838. #define JME_EEPROM_MAGIC 0x250
  839. /*
  840. * Timer Control/Status Register
  841. */
  842. enum jme_tmcsr_bit_masks {
  843. TMCSR_SWIT = 0x80000000,
  844. TMCSR_EN = 0x01000000,
  845. TMCSR_CNT = 0x00FFFFFF,
  846. };
  847. /*
  848. * General Purpose REG-0
  849. */
  850. enum jme_gpreg0_masks {
  851. GPREG0_DISSH = 0xFF000000,
  852. GPREG0_PCIRLMT = 0x00300000,
  853. GPREG0_PCCNOMUTCLR = 0x00040000,
  854. GPREG0_LNKINTPOLL = 0x00001000,
  855. GPREG0_PCCTMR = 0x00000300,
  856. GPREG0_PHYADDR = 0x0000001F,
  857. };
  858. enum jme_gpreg0_vals {
  859. GPREG0_DISSH_DW7 = 0x80000000,
  860. GPREG0_DISSH_DW6 = 0x40000000,
  861. GPREG0_DISSH_DW5 = 0x20000000,
  862. GPREG0_DISSH_DW4 = 0x10000000,
  863. GPREG0_DISSH_DW3 = 0x08000000,
  864. GPREG0_DISSH_DW2 = 0x04000000,
  865. GPREG0_DISSH_DW1 = 0x02000000,
  866. GPREG0_DISSH_DW0 = 0x01000000,
  867. GPREG0_DISSH_ALL = 0xFF000000,
  868. GPREG0_PCIRLMT_8 = 0x00000000,
  869. GPREG0_PCIRLMT_6 = 0x00100000,
  870. GPREG0_PCIRLMT_5 = 0x00200000,
  871. GPREG0_PCIRLMT_4 = 0x00300000,
  872. GPREG0_PCCTMR_16ns = 0x00000000,
  873. GPREG0_PCCTMR_256ns = 0x00000100,
  874. GPREG0_PCCTMR_1us = 0x00000200,
  875. GPREG0_PCCTMR_1ms = 0x00000300,
  876. GPREG0_PHYADDR_1 = 0x00000001,
  877. GPREG0_DEFAULT = GPREG0_PCIRLMT_4 |
  878. GPREG0_PCCTMR_1us |
  879. GPREG0_PHYADDR_1,
  880. };
  881. /*
  882. * General Purpose REG-1
  883. */
  884. enum jme_gpreg1_bit_masks {
  885. GPREG1_RXCLKOFF = 0x04000000,
  886. GPREG1_PCREQN = 0x00020000,
  887. GPREG1_HALFMODEPATCH = 0x00000040, /* For Chip revision 0x11 only */
  888. GPREG1_RSSPATCH = 0x00000020, /* For Chip revision 0x11 only */
  889. GPREG1_INTRDELAYUNIT = 0x00000018,
  890. GPREG1_INTRDELAYENABLE = 0x00000007,
  891. };
  892. enum jme_gpreg1_vals {
  893. GPREG1_INTDLYUNIT_16NS = 0x00000000,
  894. GPREG1_INTDLYUNIT_256NS = 0x00000008,
  895. GPREG1_INTDLYUNIT_1US = 0x00000010,
  896. GPREG1_INTDLYUNIT_16US = 0x00000018,
  897. GPREG1_INTDLYEN_1U = 0x00000001,
  898. GPREG1_INTDLYEN_2U = 0x00000002,
  899. GPREG1_INTDLYEN_3U = 0x00000003,
  900. GPREG1_INTDLYEN_4U = 0x00000004,
  901. GPREG1_INTDLYEN_5U = 0x00000005,
  902. GPREG1_INTDLYEN_6U = 0x00000006,
  903. GPREG1_INTDLYEN_7U = 0x00000007,
  904. GPREG1_DEFAULT = GPREG1_PCREQN,
  905. };
  906. /*
  907. * Interrupt Status Bits
  908. */
  909. enum jme_interrupt_bits {
  910. INTR_SWINTR = 0x80000000,
  911. INTR_TMINTR = 0x40000000,
  912. INTR_LINKCH = 0x20000000,
  913. INTR_PAUSERCV = 0x10000000,
  914. INTR_MAGICRCV = 0x08000000,
  915. INTR_WAKERCV = 0x04000000,
  916. INTR_PCCRX0TO = 0x02000000,
  917. INTR_PCCRX1TO = 0x01000000,
  918. INTR_PCCRX2TO = 0x00800000,
  919. INTR_PCCRX3TO = 0x00400000,
  920. INTR_PCCTXTO = 0x00200000,
  921. INTR_PCCRX0 = 0x00100000,
  922. INTR_PCCRX1 = 0x00080000,
  923. INTR_PCCRX2 = 0x00040000,
  924. INTR_PCCRX3 = 0x00020000,
  925. INTR_PCCTX = 0x00010000,
  926. INTR_RX3EMP = 0x00008000,
  927. INTR_RX2EMP = 0x00004000,
  928. INTR_RX1EMP = 0x00002000,
  929. INTR_RX0EMP = 0x00001000,
  930. INTR_RX3 = 0x00000800,
  931. INTR_RX2 = 0x00000400,
  932. INTR_RX1 = 0x00000200,
  933. INTR_RX0 = 0x00000100,
  934. INTR_TX7 = 0x00000080,
  935. INTR_TX6 = 0x00000040,
  936. INTR_TX5 = 0x00000020,
  937. INTR_TX4 = 0x00000010,
  938. INTR_TX3 = 0x00000008,
  939. INTR_TX2 = 0x00000004,
  940. INTR_TX1 = 0x00000002,
  941. INTR_TX0 = 0x00000001,
  942. };
  943. static const u32 INTR_ENABLE = INTR_SWINTR |
  944. INTR_TMINTR |
  945. INTR_LINKCH |
  946. INTR_PCCRX0TO |
  947. INTR_PCCRX0 |
  948. INTR_PCCTXTO |
  949. INTR_PCCTX |
  950. INTR_RX0EMP;
  951. /*
  952. * PCC Control Registers
  953. */
  954. enum jme_pccrx_masks {
  955. PCCRXTO_MASK = 0xFFFF0000,
  956. PCCRX_MASK = 0x0000FF00,
  957. };
  958. enum jme_pcctx_masks {
  959. PCCTXTO_MASK = 0xFFFF0000,
  960. PCCTX_MASK = 0x0000FF00,
  961. PCCTX_QS_MASK = 0x000000FF,
  962. };
  963. enum jme_pccrx_shifts {
  964. PCCRXTO_SHIFT = 16,
  965. PCCRX_SHIFT = 8,
  966. };
  967. enum jme_pcctx_shifts {
  968. PCCTXTO_SHIFT = 16,
  969. PCCTX_SHIFT = 8,
  970. };
  971. enum jme_pcctx_bits {
  972. PCCTXQ0_EN = 0x00000001,
  973. PCCTXQ1_EN = 0x00000002,
  974. PCCTXQ2_EN = 0x00000004,
  975. PCCTXQ3_EN = 0x00000008,
  976. PCCTXQ4_EN = 0x00000010,
  977. PCCTXQ5_EN = 0x00000020,
  978. PCCTXQ6_EN = 0x00000040,
  979. PCCTXQ7_EN = 0x00000080,
  980. };
  981. /*
  982. * Chip Mode Register
  983. */
  984. enum jme_chipmode_bit_masks {
  985. CM_FPGAVER_MASK = 0xFFFF0000,
  986. CM_CHIPREV_MASK = 0x0000FF00,
  987. CM_CHIPMODE_MASK = 0x0000000F,
  988. };
  989. enum jme_chipmode_shifts {
  990. CM_FPGAVER_SHIFT = 16,
  991. CM_CHIPREV_SHIFT = 8,
  992. };
  993. /*
  994. * Aggressive Power Mode Control
  995. */
  996. enum jme_apmc_bits {
  997. JME_APMC_PCIE_SD_EN = 0x40000000,
  998. JME_APMC_PSEUDO_HP_EN = 0x20000000,
  999. JME_APMC_EPIEN = 0x04000000,
  1000. JME_APMC_EPIEN_CTRL = 0x03000000,
  1001. };
  1002. enum jme_apmc_values {
  1003. JME_APMC_EPIEN_CTRL_EN = 0x02000000,
  1004. JME_APMC_EPIEN_CTRL_DIS = 0x01000000,
  1005. };
  1006. #define APMC_PHP_SHUTDOWN_DELAY (10 * 1000 * 1000)
  1007. #ifdef REG_DEBUG
  1008. static char *MAC_REG_NAME[] = {
  1009. "JME_TXCS", "JME_TXDBA_LO", "JME_TXDBA_HI", "JME_TXQDC",
  1010. "JME_TXNDA", "JME_TXMCS", "JME_TXPFC", "JME_TXTRHD",
  1011. "JME_RXCS", "JME_RXDBA_LO", "JME_RXDBA_HI", "JME_RXQDC",
  1012. "JME_RXNDA", "JME_RXMCS", "JME_RXUMA_LO", "JME_RXUMA_HI",
  1013. "JME_RXMCHT_LO", "JME_RXMCHT_HI", "JME_WFODP", "JME_WFOI",
  1014. "JME_SMI", "JME_GHC", "UNKNOWN", "UNKNOWN",
  1015. "JME_PMCS"};
  1016. static char *PE_REG_NAME[] = {
  1017. "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
  1018. "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
  1019. "UNKNOWN", "UNKNOWN", "JME_PHY_CS", "UNKNOWN",
  1020. "JME_PHY_LINK", "UNKNOWN", "UNKNOWN", "UNKNOWN",
  1021. "JME_SMBCSR", "JME_SMBINTF"};
  1022. static char *MISC_REG_NAME[] = {
  1023. "JME_TMCSR", "JME_GPIO", "JME_GPREG0", "JME_GPREG1",
  1024. "JME_IEVE", "JME_IREQ", "JME_IENS", "JME_IENC",
  1025. "JME_PCCRX0", "JME_PCCRX1", "JME_PCCRX2", "JME_PCCRX3",
  1026. "JME_PCCTX0", "JME_CHIPMODE", "JME_SHBA_HI", "JME_SHBA_LO",
  1027. "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
  1028. "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
  1029. "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
  1030. "JME_TIMER1", "JME_TIMER2", "UNKNOWN", "JME_APMC",
  1031. "JME_PCCSRX0"};
  1032. static inline void reg_dbg(const struct jme_adapter *jme,
  1033. const char *msg, u32 val, u32 reg)
  1034. {
  1035. const char *regname;
  1036. switch (reg & 0xF00) {
  1037. case 0x000:
  1038. regname = MAC_REG_NAME[(reg & 0xFF) >> 2];
  1039. break;
  1040. case 0x400:
  1041. regname = PE_REG_NAME[(reg & 0xFF) >> 2];
  1042. break;
  1043. case 0x800:
  1044. regname = MISC_REG_NAME[(reg & 0xFF) >> 2];
  1045. break;
  1046. default:
  1047. regname = PE_REG_NAME[0];
  1048. }
  1049. printk(KERN_DEBUG "%s: %-20s %08x@%s\n", jme->dev->name,
  1050. msg, val, regname);
  1051. }
  1052. #else
  1053. static inline void reg_dbg(const struct jme_adapter *jme,
  1054. const char *msg, u32 val, u32 reg) {}
  1055. #endif
  1056. /*
  1057. * Read/Write MMaped I/O Registers
  1058. */
  1059. static inline u32 jread32(struct jme_adapter *jme, u32 reg)
  1060. {
  1061. return readl(jme->regs + reg);
  1062. }
  1063. static inline void jwrite32(struct jme_adapter *jme, u32 reg, u32 val)
  1064. {
  1065. reg_dbg(jme, "REG WRITE", val, reg);
  1066. writel(val, jme->regs + reg);
  1067. reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
  1068. }
  1069. static inline void jwrite32f(struct jme_adapter *jme, u32 reg, u32 val)
  1070. {
  1071. /*
  1072. * Read after write should cause flush
  1073. */
  1074. reg_dbg(jme, "REG WRITE FLUSH", val, reg);
  1075. writel(val, jme->regs + reg);
  1076. readl(jme->regs + reg);
  1077. reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
  1078. }
  1079. /*
  1080. * PHY Regs
  1081. */
  1082. enum jme_phy_reg17_bit_masks {
  1083. PREG17_SPEED = 0xC000,
  1084. PREG17_DUPLEX = 0x2000,
  1085. PREG17_SPDRSV = 0x0800,
  1086. PREG17_LNKUP = 0x0400,
  1087. PREG17_MDI = 0x0040,
  1088. };
  1089. enum jme_phy_reg17_vals {
  1090. PREG17_SPEED_10M = 0x0000,
  1091. PREG17_SPEED_100M = 0x4000,
  1092. PREG17_SPEED_1000M = 0x8000,
  1093. };
  1094. #define BMSR_ANCOMP 0x0020
  1095. /*
  1096. * Workaround
  1097. */
  1098. static inline int is_buggy250(unsigned short device, u8 chiprev)
  1099. {
  1100. return device == PCI_DEVICE_ID_JMICRON_JMC250 && chiprev == 0x11;
  1101. }
  1102. static inline int new_phy_power_ctrl(u8 chip_main_rev)
  1103. {
  1104. return chip_main_rev >= 5;
  1105. }
  1106. /*
  1107. * Function prototypes
  1108. */
  1109. static int jme_set_link_ksettings(struct net_device *netdev,
  1110. const struct ethtool_link_ksettings *cmd);
  1111. static void jme_set_unicastaddr(struct net_device *netdev);
  1112. static void jme_set_multi(struct net_device *netdev);
  1113. #endif