/drivers/net/ethernet/lantiq_etop.c

http://github.com/mirrors/linux · C · 735 lines · 606 code · 117 blank · 12 comment · 61 complexity · 6a654bb7c98dda451e6d167afcfb5a87 MD5 · raw file

  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. *
  4. * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
  5. */
  6. #include <linux/kernel.h>
  7. #include <linux/slab.h>
  8. #include <linux/errno.h>
  9. #include <linux/types.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/uaccess.h>
  12. #include <linux/in.h>
  13. #include <linux/netdevice.h>
  14. #include <linux/etherdevice.h>
  15. #include <linux/phy.h>
  16. #include <linux/ip.h>
  17. #include <linux/tcp.h>
  18. #include <linux/skbuff.h>
  19. #include <linux/mm.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/ethtool.h>
  22. #include <linux/init.h>
  23. #include <linux/delay.h>
  24. #include <linux/io.h>
  25. #include <linux/dma-mapping.h>
  26. #include <linux/module.h>
  27. #include <asm/checksum.h>
  28. #include <lantiq_soc.h>
  29. #include <xway_dma.h>
  30. #include <lantiq_platform.h>
  31. #define LTQ_ETOP_MDIO 0x11804
  32. #define MDIO_REQUEST 0x80000000
  33. #define MDIO_READ 0x40000000
  34. #define MDIO_ADDR_MASK 0x1f
  35. #define MDIO_ADDR_OFFSET 0x15
  36. #define MDIO_REG_MASK 0x1f
  37. #define MDIO_REG_OFFSET 0x10
  38. #define MDIO_VAL_MASK 0xffff
  39. #define PPE32_CGEN 0x800
  40. #define LQ_PPE32_ENET_MAC_CFG 0x1840
  41. #define LTQ_ETOP_ENETS0 0x11850
  42. #define LTQ_ETOP_MAC_DA0 0x1186C
  43. #define LTQ_ETOP_MAC_DA1 0x11870
  44. #define LTQ_ETOP_CFG 0x16020
  45. #define LTQ_ETOP_IGPLEN 0x16080
  46. #define MAX_DMA_CHAN 0x8
  47. #define MAX_DMA_CRC_LEN 0x4
  48. #define MAX_DMA_DATA_LEN 0x600
  49. #define ETOP_FTCU BIT(28)
  50. #define ETOP_MII_MASK 0xf
  51. #define ETOP_MII_NORMAL 0xd
  52. #define ETOP_MII_REVERSE 0xe
  53. #define ETOP_PLEN_UNDER 0x40
  54. #define ETOP_CGEN 0x800
  55. /* use 2 static channels for TX/RX */
  56. #define LTQ_ETOP_TX_CHANNEL 1
  57. #define LTQ_ETOP_RX_CHANNEL 6
  58. #define IS_TX(x) (x == LTQ_ETOP_TX_CHANNEL)
  59. #define IS_RX(x) (x == LTQ_ETOP_RX_CHANNEL)
  60. #define ltq_etop_r32(x) ltq_r32(ltq_etop_membase + (x))
  61. #define ltq_etop_w32(x, y) ltq_w32(x, ltq_etop_membase + (y))
  62. #define ltq_etop_w32_mask(x, y, z) \
  63. ltq_w32_mask(x, y, ltq_etop_membase + (z))
  64. #define DRV_VERSION "1.0"
  65. static void __iomem *ltq_etop_membase;
  66. struct ltq_etop_chan {
  67. int idx;
  68. int tx_free;
  69. struct net_device *netdev;
  70. struct napi_struct napi;
  71. struct ltq_dma_channel dma;
  72. struct sk_buff *skb[LTQ_DESC_NUM];
  73. };
  74. struct ltq_etop_priv {
  75. struct net_device *netdev;
  76. struct platform_device *pdev;
  77. struct ltq_eth_data *pldata;
  78. struct resource *res;
  79. struct mii_bus *mii_bus;
  80. struct ltq_etop_chan ch[MAX_DMA_CHAN];
  81. int tx_free[MAX_DMA_CHAN >> 1];
  82. spinlock_t lock;
  83. };
  84. static int
  85. ltq_etop_alloc_skb(struct ltq_etop_chan *ch)
  86. {
  87. struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
  88. ch->skb[ch->dma.desc] = netdev_alloc_skb(ch->netdev, MAX_DMA_DATA_LEN);
  89. if (!ch->skb[ch->dma.desc])
  90. return -ENOMEM;
  91. ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(&priv->pdev->dev,
  92. ch->skb[ch->dma.desc]->data, MAX_DMA_DATA_LEN,
  93. DMA_FROM_DEVICE);
  94. ch->dma.desc_base[ch->dma.desc].addr =
  95. CPHYSADDR(ch->skb[ch->dma.desc]->data);
  96. ch->dma.desc_base[ch->dma.desc].ctl =
  97. LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) |
  98. MAX_DMA_DATA_LEN;
  99. skb_reserve(ch->skb[ch->dma.desc], NET_IP_ALIGN);
  100. return 0;
  101. }
  102. static void
  103. ltq_etop_hw_receive(struct ltq_etop_chan *ch)
  104. {
  105. struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
  106. struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
  107. struct sk_buff *skb = ch->skb[ch->dma.desc];
  108. int len = (desc->ctl & LTQ_DMA_SIZE_MASK) - MAX_DMA_CRC_LEN;
  109. unsigned long flags;
  110. spin_lock_irqsave(&priv->lock, flags);
  111. if (ltq_etop_alloc_skb(ch)) {
  112. netdev_err(ch->netdev,
  113. "failed to allocate new rx buffer, stopping DMA\n");
  114. ltq_dma_close(&ch->dma);
  115. }
  116. ch->dma.desc++;
  117. ch->dma.desc %= LTQ_DESC_NUM;
  118. spin_unlock_irqrestore(&priv->lock, flags);
  119. skb_put(skb, len);
  120. skb->protocol = eth_type_trans(skb, ch->netdev);
  121. netif_receive_skb(skb);
  122. }
  123. static int
  124. ltq_etop_poll_rx(struct napi_struct *napi, int budget)
  125. {
  126. struct ltq_etop_chan *ch = container_of(napi,
  127. struct ltq_etop_chan, napi);
  128. int work_done = 0;
  129. while (work_done < budget) {
  130. struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
  131. if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) != LTQ_DMA_C)
  132. break;
  133. ltq_etop_hw_receive(ch);
  134. work_done++;
  135. }
  136. if (work_done < budget) {
  137. napi_complete_done(&ch->napi, work_done);
  138. ltq_dma_ack_irq(&ch->dma);
  139. }
  140. return work_done;
  141. }
  142. static int
  143. ltq_etop_poll_tx(struct napi_struct *napi, int budget)
  144. {
  145. struct ltq_etop_chan *ch =
  146. container_of(napi, struct ltq_etop_chan, napi);
  147. struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
  148. struct netdev_queue *txq =
  149. netdev_get_tx_queue(ch->netdev, ch->idx >> 1);
  150. unsigned long flags;
  151. spin_lock_irqsave(&priv->lock, flags);
  152. while ((ch->dma.desc_base[ch->tx_free].ctl &
  153. (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
  154. dev_kfree_skb_any(ch->skb[ch->tx_free]);
  155. ch->skb[ch->tx_free] = NULL;
  156. memset(&ch->dma.desc_base[ch->tx_free], 0,
  157. sizeof(struct ltq_dma_desc));
  158. ch->tx_free++;
  159. ch->tx_free %= LTQ_DESC_NUM;
  160. }
  161. spin_unlock_irqrestore(&priv->lock, flags);
  162. if (netif_tx_queue_stopped(txq))
  163. netif_tx_start_queue(txq);
  164. napi_complete(&ch->napi);
  165. ltq_dma_ack_irq(&ch->dma);
  166. return 1;
  167. }
  168. static irqreturn_t
  169. ltq_etop_dma_irq(int irq, void *_priv)
  170. {
  171. struct ltq_etop_priv *priv = _priv;
  172. int ch = irq - LTQ_DMA_CH0_INT;
  173. napi_schedule(&priv->ch[ch].napi);
  174. return IRQ_HANDLED;
  175. }
  176. static void
  177. ltq_etop_free_channel(struct net_device *dev, struct ltq_etop_chan *ch)
  178. {
  179. struct ltq_etop_priv *priv = netdev_priv(dev);
  180. ltq_dma_free(&ch->dma);
  181. if (ch->dma.irq)
  182. free_irq(ch->dma.irq, priv);
  183. if (IS_RX(ch->idx)) {
  184. int desc;
  185. for (desc = 0; desc < LTQ_DESC_NUM; desc++)
  186. dev_kfree_skb_any(ch->skb[ch->dma.desc]);
  187. }
  188. }
  189. static void
  190. ltq_etop_hw_exit(struct net_device *dev)
  191. {
  192. struct ltq_etop_priv *priv = netdev_priv(dev);
  193. int i;
  194. ltq_pmu_disable(PMU_PPE);
  195. for (i = 0; i < MAX_DMA_CHAN; i++)
  196. if (IS_TX(i) || IS_RX(i))
  197. ltq_etop_free_channel(dev, &priv->ch[i]);
  198. }
  199. static int
  200. ltq_etop_hw_init(struct net_device *dev)
  201. {
  202. struct ltq_etop_priv *priv = netdev_priv(dev);
  203. int i;
  204. ltq_pmu_enable(PMU_PPE);
  205. switch (priv->pldata->mii_mode) {
  206. case PHY_INTERFACE_MODE_RMII:
  207. ltq_etop_w32_mask(ETOP_MII_MASK,
  208. ETOP_MII_REVERSE, LTQ_ETOP_CFG);
  209. break;
  210. case PHY_INTERFACE_MODE_MII:
  211. ltq_etop_w32_mask(ETOP_MII_MASK,
  212. ETOP_MII_NORMAL, LTQ_ETOP_CFG);
  213. break;
  214. default:
  215. netdev_err(dev, "unknown mii mode %d\n",
  216. priv->pldata->mii_mode);
  217. return -ENOTSUPP;
  218. }
  219. /* enable crc generation */
  220. ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG);
  221. ltq_dma_init_port(DMA_PORT_ETOP);
  222. for (i = 0; i < MAX_DMA_CHAN; i++) {
  223. int irq = LTQ_DMA_CH0_INT + i;
  224. struct ltq_etop_chan *ch = &priv->ch[i];
  225. ch->idx = ch->dma.nr = i;
  226. ch->dma.dev = &priv->pdev->dev;
  227. if (IS_TX(i)) {
  228. ltq_dma_alloc_tx(&ch->dma);
  229. request_irq(irq, ltq_etop_dma_irq, 0, "etop_tx", priv);
  230. } else if (IS_RX(i)) {
  231. ltq_dma_alloc_rx(&ch->dma);
  232. for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM;
  233. ch->dma.desc++)
  234. if (ltq_etop_alloc_skb(ch))
  235. return -ENOMEM;
  236. ch->dma.desc = 0;
  237. request_irq(irq, ltq_etop_dma_irq, 0, "etop_rx", priv);
  238. }
  239. ch->dma.irq = irq;
  240. }
  241. return 0;
  242. }
  243. static void
  244. ltq_etop_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
  245. {
  246. strlcpy(info->driver, "Lantiq ETOP", sizeof(info->driver));
  247. strlcpy(info->bus_info, "internal", sizeof(info->bus_info));
  248. strlcpy(info->version, DRV_VERSION, sizeof(info->version));
  249. }
  250. static const struct ethtool_ops ltq_etop_ethtool_ops = {
  251. .get_drvinfo = ltq_etop_get_drvinfo,
  252. .nway_reset = phy_ethtool_nway_reset,
  253. .get_link_ksettings = phy_ethtool_get_link_ksettings,
  254. .set_link_ksettings = phy_ethtool_set_link_ksettings,
  255. };
  256. static int
  257. ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data)
  258. {
  259. u32 val = MDIO_REQUEST |
  260. ((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) |
  261. ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET) |
  262. phy_data;
  263. while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
  264. ;
  265. ltq_etop_w32(val, LTQ_ETOP_MDIO);
  266. return 0;
  267. }
  268. static int
  269. ltq_etop_mdio_rd(struct mii_bus *bus, int phy_addr, int phy_reg)
  270. {
  271. u32 val = MDIO_REQUEST | MDIO_READ |
  272. ((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) |
  273. ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET);
  274. while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
  275. ;
  276. ltq_etop_w32(val, LTQ_ETOP_MDIO);
  277. while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
  278. ;
  279. val = ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_VAL_MASK;
  280. return val;
  281. }
  282. static void
  283. ltq_etop_mdio_link(struct net_device *dev)
  284. {
  285. /* nothing to do */
  286. }
  287. static int
  288. ltq_etop_mdio_probe(struct net_device *dev)
  289. {
  290. struct ltq_etop_priv *priv = netdev_priv(dev);
  291. struct phy_device *phydev;
  292. phydev = phy_find_first(priv->mii_bus);
  293. if (!phydev) {
  294. netdev_err(dev, "no PHY found\n");
  295. return -ENODEV;
  296. }
  297. phydev = phy_connect(dev, phydev_name(phydev),
  298. &ltq_etop_mdio_link, priv->pldata->mii_mode);
  299. if (IS_ERR(phydev)) {
  300. netdev_err(dev, "Could not attach to PHY\n");
  301. return PTR_ERR(phydev);
  302. }
  303. phy_set_max_speed(phydev, SPEED_100);
  304. phy_attached_info(phydev);
  305. return 0;
  306. }
  307. static int
  308. ltq_etop_mdio_init(struct net_device *dev)
  309. {
  310. struct ltq_etop_priv *priv = netdev_priv(dev);
  311. int err;
  312. priv->mii_bus = mdiobus_alloc();
  313. if (!priv->mii_bus) {
  314. netdev_err(dev, "failed to allocate mii bus\n");
  315. err = -ENOMEM;
  316. goto err_out;
  317. }
  318. priv->mii_bus->priv = dev;
  319. priv->mii_bus->read = ltq_etop_mdio_rd;
  320. priv->mii_bus->write = ltq_etop_mdio_wr;
  321. priv->mii_bus->name = "ltq_mii";
  322. snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
  323. priv->pdev->name, priv->pdev->id);
  324. if (mdiobus_register(priv->mii_bus)) {
  325. err = -ENXIO;
  326. goto err_out_free_mdiobus;
  327. }
  328. if (ltq_etop_mdio_probe(dev)) {
  329. err = -ENXIO;
  330. goto err_out_unregister_bus;
  331. }
  332. return 0;
  333. err_out_unregister_bus:
  334. mdiobus_unregister(priv->mii_bus);
  335. err_out_free_mdiobus:
  336. mdiobus_free(priv->mii_bus);
  337. err_out:
  338. return err;
  339. }
  340. static void
  341. ltq_etop_mdio_cleanup(struct net_device *dev)
  342. {
  343. struct ltq_etop_priv *priv = netdev_priv(dev);
  344. phy_disconnect(dev->phydev);
  345. mdiobus_unregister(priv->mii_bus);
  346. mdiobus_free(priv->mii_bus);
  347. }
  348. static int
  349. ltq_etop_open(struct net_device *dev)
  350. {
  351. struct ltq_etop_priv *priv = netdev_priv(dev);
  352. int i;
  353. for (i = 0; i < MAX_DMA_CHAN; i++) {
  354. struct ltq_etop_chan *ch = &priv->ch[i];
  355. if (!IS_TX(i) && (!IS_RX(i)))
  356. continue;
  357. ltq_dma_open(&ch->dma);
  358. ltq_dma_enable_irq(&ch->dma);
  359. napi_enable(&ch->napi);
  360. }
  361. phy_start(dev->phydev);
  362. netif_tx_start_all_queues(dev);
  363. return 0;
  364. }
  365. static int
  366. ltq_etop_stop(struct net_device *dev)
  367. {
  368. struct ltq_etop_priv *priv = netdev_priv(dev);
  369. int i;
  370. netif_tx_stop_all_queues(dev);
  371. phy_stop(dev->phydev);
  372. for (i = 0; i < MAX_DMA_CHAN; i++) {
  373. struct ltq_etop_chan *ch = &priv->ch[i];
  374. if (!IS_RX(i) && !IS_TX(i))
  375. continue;
  376. napi_disable(&ch->napi);
  377. ltq_dma_close(&ch->dma);
  378. }
  379. return 0;
  380. }
  381. static int
  382. ltq_etop_tx(struct sk_buff *skb, struct net_device *dev)
  383. {
  384. int queue = skb_get_queue_mapping(skb);
  385. struct netdev_queue *txq = netdev_get_tx_queue(dev, queue);
  386. struct ltq_etop_priv *priv = netdev_priv(dev);
  387. struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1];
  388. struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
  389. int len;
  390. unsigned long flags;
  391. u32 byte_offset;
  392. len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
  393. if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) {
  394. dev_kfree_skb_any(skb);
  395. netdev_err(dev, "tx ring full\n");
  396. netif_tx_stop_queue(txq);
  397. return NETDEV_TX_BUSY;
  398. }
  399. /* dma needs to start on a 16 byte aligned address */
  400. byte_offset = CPHYSADDR(skb->data) % 16;
  401. ch->skb[ch->dma.desc] = skb;
  402. netif_trans_update(dev);
  403. spin_lock_irqsave(&priv->lock, flags);
  404. desc->addr = ((unsigned int) dma_map_single(&priv->pdev->dev, skb->data, len,
  405. DMA_TO_DEVICE)) - byte_offset;
  406. wmb();
  407. desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP |
  408. LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK);
  409. ch->dma.desc++;
  410. ch->dma.desc %= LTQ_DESC_NUM;
  411. spin_unlock_irqrestore(&priv->lock, flags);
  412. if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN)
  413. netif_tx_stop_queue(txq);
  414. return NETDEV_TX_OK;
  415. }
  416. static int
  417. ltq_etop_change_mtu(struct net_device *dev, int new_mtu)
  418. {
  419. struct ltq_etop_priv *priv = netdev_priv(dev);
  420. unsigned long flags;
  421. dev->mtu = new_mtu;
  422. spin_lock_irqsave(&priv->lock, flags);
  423. ltq_etop_w32((ETOP_PLEN_UNDER << 16) | new_mtu, LTQ_ETOP_IGPLEN);
  424. spin_unlock_irqrestore(&priv->lock, flags);
  425. return 0;
  426. }
  427. static int
  428. ltq_etop_set_mac_address(struct net_device *dev, void *p)
  429. {
  430. int ret = eth_mac_addr(dev, p);
  431. if (!ret) {
  432. struct ltq_etop_priv *priv = netdev_priv(dev);
  433. unsigned long flags;
  434. /* store the mac for the unicast filter */
  435. spin_lock_irqsave(&priv->lock, flags);
  436. ltq_etop_w32(*((u32 *)dev->dev_addr), LTQ_ETOP_MAC_DA0);
  437. ltq_etop_w32(*((u16 *)&dev->dev_addr[4]) << 16,
  438. LTQ_ETOP_MAC_DA1);
  439. spin_unlock_irqrestore(&priv->lock, flags);
  440. }
  441. return ret;
  442. }
  443. static void
  444. ltq_etop_set_multicast_list(struct net_device *dev)
  445. {
  446. struct ltq_etop_priv *priv = netdev_priv(dev);
  447. unsigned long flags;
  448. /* ensure that the unicast filter is not enabled in promiscious mode */
  449. spin_lock_irqsave(&priv->lock, flags);
  450. if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI))
  451. ltq_etop_w32_mask(ETOP_FTCU, 0, LTQ_ETOP_ENETS0);
  452. else
  453. ltq_etop_w32_mask(0, ETOP_FTCU, LTQ_ETOP_ENETS0);
  454. spin_unlock_irqrestore(&priv->lock, flags);
  455. }
  456. static int
  457. ltq_etop_init(struct net_device *dev)
  458. {
  459. struct ltq_etop_priv *priv = netdev_priv(dev);
  460. struct sockaddr mac;
  461. int err;
  462. bool random_mac = false;
  463. dev->watchdog_timeo = 10 * HZ;
  464. err = ltq_etop_hw_init(dev);
  465. if (err)
  466. goto err_hw;
  467. ltq_etop_change_mtu(dev, 1500);
  468. memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr));
  469. if (!is_valid_ether_addr(mac.sa_data)) {
  470. pr_warn("etop: invalid MAC, using random\n");
  471. eth_random_addr(mac.sa_data);
  472. random_mac = true;
  473. }
  474. err = ltq_etop_set_mac_address(dev, &mac);
  475. if (err)
  476. goto err_netdev;
  477. /* Set addr_assign_type here, ltq_etop_set_mac_address would reset it. */
  478. if (random_mac)
  479. dev->addr_assign_type = NET_ADDR_RANDOM;
  480. ltq_etop_set_multicast_list(dev);
  481. err = ltq_etop_mdio_init(dev);
  482. if (err)
  483. goto err_netdev;
  484. return 0;
  485. err_netdev:
  486. unregister_netdev(dev);
  487. free_netdev(dev);
  488. err_hw:
  489. ltq_etop_hw_exit(dev);
  490. return err;
  491. }
  492. static void
  493. ltq_etop_tx_timeout(struct net_device *dev, unsigned int txqueue)
  494. {
  495. int err;
  496. ltq_etop_hw_exit(dev);
  497. err = ltq_etop_hw_init(dev);
  498. if (err)
  499. goto err_hw;
  500. netif_trans_update(dev);
  501. netif_wake_queue(dev);
  502. return;
  503. err_hw:
  504. ltq_etop_hw_exit(dev);
  505. netdev_err(dev, "failed to restart etop after TX timeout\n");
  506. }
  507. static const struct net_device_ops ltq_eth_netdev_ops = {
  508. .ndo_open = ltq_etop_open,
  509. .ndo_stop = ltq_etop_stop,
  510. .ndo_start_xmit = ltq_etop_tx,
  511. .ndo_change_mtu = ltq_etop_change_mtu,
  512. .ndo_do_ioctl = phy_do_ioctl,
  513. .ndo_set_mac_address = ltq_etop_set_mac_address,
  514. .ndo_validate_addr = eth_validate_addr,
  515. .ndo_set_rx_mode = ltq_etop_set_multicast_list,
  516. .ndo_select_queue = dev_pick_tx_zero,
  517. .ndo_init = ltq_etop_init,
  518. .ndo_tx_timeout = ltq_etop_tx_timeout,
  519. };
  520. static int __init
  521. ltq_etop_probe(struct platform_device *pdev)
  522. {
  523. struct net_device *dev;
  524. struct ltq_etop_priv *priv;
  525. struct resource *res;
  526. int err;
  527. int i;
  528. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  529. if (!res) {
  530. dev_err(&pdev->dev, "failed to get etop resource\n");
  531. err = -ENOENT;
  532. goto err_out;
  533. }
  534. res = devm_request_mem_region(&pdev->dev, res->start,
  535. resource_size(res), dev_name(&pdev->dev));
  536. if (!res) {
  537. dev_err(&pdev->dev, "failed to request etop resource\n");
  538. err = -EBUSY;
  539. goto err_out;
  540. }
  541. ltq_etop_membase = devm_ioremap(&pdev->dev,
  542. res->start, resource_size(res));
  543. if (!ltq_etop_membase) {
  544. dev_err(&pdev->dev, "failed to remap etop engine %d\n",
  545. pdev->id);
  546. err = -ENOMEM;
  547. goto err_out;
  548. }
  549. dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
  550. if (!dev) {
  551. err = -ENOMEM;
  552. goto err_out;
  553. }
  554. strcpy(dev->name, "eth%d");
  555. dev->netdev_ops = &ltq_eth_netdev_ops;
  556. dev->ethtool_ops = &ltq_etop_ethtool_ops;
  557. priv = netdev_priv(dev);
  558. priv->res = res;
  559. priv->pdev = pdev;
  560. priv->pldata = dev_get_platdata(&pdev->dev);
  561. priv->netdev = dev;
  562. spin_lock_init(&priv->lock);
  563. SET_NETDEV_DEV(dev, &pdev->dev);
  564. for (i = 0; i < MAX_DMA_CHAN; i++) {
  565. if (IS_TX(i))
  566. netif_napi_add(dev, &priv->ch[i].napi,
  567. ltq_etop_poll_tx, 8);
  568. else if (IS_RX(i))
  569. netif_napi_add(dev, &priv->ch[i].napi,
  570. ltq_etop_poll_rx, 32);
  571. priv->ch[i].netdev = dev;
  572. }
  573. err = register_netdev(dev);
  574. if (err)
  575. goto err_free;
  576. platform_set_drvdata(pdev, dev);
  577. return 0;
  578. err_free:
  579. free_netdev(dev);
  580. err_out:
  581. return err;
  582. }
  583. static int
  584. ltq_etop_remove(struct platform_device *pdev)
  585. {
  586. struct net_device *dev = platform_get_drvdata(pdev);
  587. if (dev) {
  588. netif_tx_stop_all_queues(dev);
  589. ltq_etop_hw_exit(dev);
  590. ltq_etop_mdio_cleanup(dev);
  591. unregister_netdev(dev);
  592. }
  593. return 0;
  594. }
  595. static struct platform_driver ltq_mii_driver = {
  596. .remove = ltq_etop_remove,
  597. .driver = {
  598. .name = "ltq_etop",
  599. },
  600. };
  601. int __init
  602. init_ltq_etop(void)
  603. {
  604. int ret = platform_driver_probe(&ltq_mii_driver, ltq_etop_probe);
  605. if (ret)
  606. pr_err("ltq_etop: Error registering platform driver!");
  607. return ret;
  608. }
  609. static void __exit
  610. exit_ltq_etop(void)
  611. {
  612. platform_driver_unregister(&ltq_mii_driver);
  613. }
  614. module_init(init_ltq_etop);
  615. module_exit(exit_ltq_etop);
  616. MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
  617. MODULE_DESCRIPTION("Lantiq SoC ETOP");
  618. MODULE_LICENSE("GPL");