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/drivers/net/ethernet/chelsio/cxgb/subr.c

http://github.com/mirrors/linux
C | 1128 lines | 818 code | 141 blank | 169 comment | 109 complexity | 58eba96f19425428d84c948347fb7fd2 MD5 | raw file
   1/*****************************************************************************
   2 *                                                                           *
   3 * File: subr.c                                                              *
   4 * $Revision: 1.27 $                                                         *
   5 * $Date: 2005/06/22 01:08:36 $                                              *
   6 * Description:                                                              *
   7 *  Various subroutines (intr,pio,etc.) used by Chelsio 10G Ethernet driver. *
   8 *  part of the Chelsio 10Gb Ethernet Driver.                                *
   9 *                                                                           *
  10 * This program is free software; you can redistribute it and/or modify      *
  11 * it under the terms of the GNU General Public License, version 2, as       *
  12 * published by the Free Software Foundation.                                *
  13 *                                                                           *
  14 * You should have received a copy of the GNU General Public License along   *
  15 * with this program; if not, see <http://www.gnu.org/licenses/>.            *
  16 *                                                                           *
  17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED    *
  18 * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF      *
  19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.                     *
  20 *                                                                           *
  21 * http://www.chelsio.com                                                    *
  22 *                                                                           *
  23 * Copyright (c) 2003 - 2005 Chelsio Communications, Inc.                    *
  24 * All rights reserved.                                                      *
  25 *                                                                           *
  26 * Maintainers: maintainers@chelsio.com                                      *
  27 *                                                                           *
  28 * Authors: Dimitrios Michailidis   <dm@chelsio.com>                         *
  29 *          Tina Yang               <tainay@chelsio.com>                     *
  30 *          Felix Marti             <felix@chelsio.com>                      *
  31 *          Scott Bardone           <sbardone@chelsio.com>                   *
  32 *          Kurt Ottaway            <kottaway@chelsio.com>                   *
  33 *          Frank DiMambro          <frank@chelsio.com>                      *
  34 *                                                                           *
  35 * History:                                                                  *
  36 *                                                                           *
  37 ****************************************************************************/
  38
  39#include "common.h"
  40#include "elmer0.h"
  41#include "regs.h"
  42#include "gmac.h"
  43#include "cphy.h"
  44#include "sge.h"
  45#include "tp.h"
  46#include "espi.h"
  47
  48/**
  49 *	t1_wait_op_done - wait until an operation is completed
  50 *	@adapter: the adapter performing the operation
  51 *	@reg: the register to check for completion
  52 *	@mask: a single-bit field within @reg that indicates completion
  53 *	@polarity: the value of the field when the operation is completed
  54 *	@attempts: number of check iterations
  55 *      @delay: delay in usecs between iterations
  56 *
  57 *	Wait until an operation is completed by checking a bit in a register
  58 *	up to @attempts times.  Returns %0 if the operation completes and %1
  59 *	otherwise.
  60 */
  61static int t1_wait_op_done(adapter_t *adapter, int reg, u32 mask, int polarity,
  62			   int attempts, int delay)
  63{
  64	while (1) {
  65		u32 val = readl(adapter->regs + reg) & mask;
  66
  67		if (!!val == polarity)
  68			return 0;
  69		if (--attempts == 0)
  70			return 1;
  71		if (delay)
  72			udelay(delay);
  73	}
  74}
  75
  76#define TPI_ATTEMPTS 50
  77
  78/*
  79 * Write a register over the TPI interface (unlocked and locked versions).
  80 */
  81int __t1_tpi_write(adapter_t *adapter, u32 addr, u32 value)
  82{
  83	int tpi_busy;
  84
  85	writel(addr, adapter->regs + A_TPI_ADDR);
  86	writel(value, adapter->regs + A_TPI_WR_DATA);
  87	writel(F_TPIWR, adapter->regs + A_TPI_CSR);
  88
  89	tpi_busy = t1_wait_op_done(adapter, A_TPI_CSR, F_TPIRDY, 1,
  90				   TPI_ATTEMPTS, 3);
  91	if (tpi_busy)
  92		pr_alert("%s: TPI write to 0x%x failed\n",
  93			 adapter->name, addr);
  94	return tpi_busy;
  95}
  96
  97int t1_tpi_write(adapter_t *adapter, u32 addr, u32 value)
  98{
  99	int ret;
 100
 101	spin_lock(&adapter->tpi_lock);
 102	ret = __t1_tpi_write(adapter, addr, value);
 103	spin_unlock(&adapter->tpi_lock);
 104	return ret;
 105}
 106
 107/*
 108 * Read a register over the TPI interface (unlocked and locked versions).
 109 */
 110int __t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp)
 111{
 112	int tpi_busy;
 113
 114	writel(addr, adapter->regs + A_TPI_ADDR);
 115	writel(0, adapter->regs + A_TPI_CSR);
 116
 117	tpi_busy = t1_wait_op_done(adapter, A_TPI_CSR, F_TPIRDY, 1,
 118				   TPI_ATTEMPTS, 3);
 119	if (tpi_busy)
 120		pr_alert("%s: TPI read from 0x%x failed\n",
 121			 adapter->name, addr);
 122	else
 123		*valp = readl(adapter->regs + A_TPI_RD_DATA);
 124	return tpi_busy;
 125}
 126
 127int t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp)
 128{
 129	int ret;
 130
 131	spin_lock(&adapter->tpi_lock);
 132	ret = __t1_tpi_read(adapter, addr, valp);
 133	spin_unlock(&adapter->tpi_lock);
 134	return ret;
 135}
 136
 137/*
 138 * Set a TPI parameter.
 139 */
 140static void t1_tpi_par(adapter_t *adapter, u32 value)
 141{
 142	writel(V_TPIPAR(value), adapter->regs + A_TPI_PAR);
 143}
 144
 145/*
 146 * Called when a port's link settings change to propagate the new values to the
 147 * associated PHY and MAC.  After performing the common tasks it invokes an
 148 * OS-specific handler.
 149 */
 150void t1_link_changed(adapter_t *adapter, int port_id)
 151{
 152	int link_ok, speed, duplex, fc;
 153	struct cphy *phy = adapter->port[port_id].phy;
 154	struct link_config *lc = &adapter->port[port_id].link_config;
 155
 156	phy->ops->get_link_status(phy, &link_ok, &speed, &duplex, &fc);
 157
 158	lc->speed = speed < 0 ? SPEED_INVALID : speed;
 159	lc->duplex = duplex < 0 ? DUPLEX_INVALID : duplex;
 160	if (!(lc->requested_fc & PAUSE_AUTONEG))
 161		fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
 162
 163	if (link_ok && speed >= 0 && lc->autoneg == AUTONEG_ENABLE) {
 164		/* Set MAC speed, duplex, and flow control to match PHY. */
 165		struct cmac *mac = adapter->port[port_id].mac;
 166
 167		mac->ops->set_speed_duplex_fc(mac, speed, duplex, fc);
 168		lc->fc = (unsigned char)fc;
 169	}
 170	t1_link_negotiated(adapter, port_id, link_ok, speed, duplex, fc);
 171}
 172
 173static int t1_pci_intr_handler(adapter_t *adapter)
 174{
 175	u32 pcix_cause;
 176
 177	pci_read_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE, &pcix_cause);
 178
 179	if (pcix_cause) {
 180		pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE,
 181				       pcix_cause);
 182		t1_fatal_err(adapter);    /* PCI errors are fatal */
 183	}
 184	return 0;
 185}
 186
 187#ifdef CONFIG_CHELSIO_T1_1G
 188#include "fpga_defs.h"
 189
 190/*
 191 * PHY interrupt handler for FPGA boards.
 192 */
 193static int fpga_phy_intr_handler(adapter_t *adapter)
 194{
 195	int p;
 196	u32 cause = readl(adapter->regs + FPGA_GMAC_ADDR_INTERRUPT_CAUSE);
 197
 198	for_each_port(adapter, p)
 199		if (cause & (1 << p)) {
 200			struct cphy *phy = adapter->port[p].phy;
 201			int phy_cause = phy->ops->interrupt_handler(phy);
 202
 203			if (phy_cause & cphy_cause_link_change)
 204				t1_link_changed(adapter, p);
 205		}
 206	writel(cause, adapter->regs + FPGA_GMAC_ADDR_INTERRUPT_CAUSE);
 207	return 0;
 208}
 209
 210/*
 211 * Slow path interrupt handler for FPGAs.
 212 */
 213static int fpga_slow_intr(adapter_t *adapter)
 214{
 215	u32 cause = readl(adapter->regs + A_PL_CAUSE);
 216
 217	cause &= ~F_PL_INTR_SGE_DATA;
 218	if (cause & F_PL_INTR_SGE_ERR)
 219		t1_sge_intr_error_handler(adapter->sge);
 220
 221	if (cause & FPGA_PCIX_INTERRUPT_GMAC)
 222		fpga_phy_intr_handler(adapter);
 223
 224	if (cause & FPGA_PCIX_INTERRUPT_TP) {
 225		/*
 226		 * FPGA doesn't support MC4 interrupts and it requires
 227		 * this odd layer of indirection for MC5.
 228		 */
 229		u32 tp_cause = readl(adapter->regs + FPGA_TP_ADDR_INTERRUPT_CAUSE);
 230
 231		/* Clear TP interrupt */
 232		writel(tp_cause, adapter->regs + FPGA_TP_ADDR_INTERRUPT_CAUSE);
 233	}
 234	if (cause & FPGA_PCIX_INTERRUPT_PCIX)
 235		t1_pci_intr_handler(adapter);
 236
 237	/* Clear the interrupts just processed. */
 238	if (cause)
 239		writel(cause, adapter->regs + A_PL_CAUSE);
 240
 241	return cause != 0;
 242}
 243#endif
 244
 245/*
 246 * Wait until Elmer's MI1 interface is ready for new operations.
 247 */
 248static int mi1_wait_until_ready(adapter_t *adapter, int mi1_reg)
 249{
 250	int attempts = 100, busy;
 251
 252	do {
 253		u32 val;
 254
 255		__t1_tpi_read(adapter, mi1_reg, &val);
 256		busy = val & F_MI1_OP_BUSY;
 257		if (busy)
 258			udelay(10);
 259	} while (busy && --attempts);
 260	if (busy)
 261		pr_alert("%s: MDIO operation timed out\n", adapter->name);
 262	return busy;
 263}
 264
 265/*
 266 * MI1 MDIO initialization.
 267 */
 268static void mi1_mdio_init(adapter_t *adapter, const struct board_info *bi)
 269{
 270	u32 clkdiv = bi->clock_elmer0 / (2 * bi->mdio_mdc) - 1;
 271	u32 val = F_MI1_PREAMBLE_ENABLE | V_MI1_MDI_INVERT(bi->mdio_mdiinv) |
 272		V_MI1_MDI_ENABLE(bi->mdio_mdien) | V_MI1_CLK_DIV(clkdiv);
 273
 274	if (!(bi->caps & SUPPORTED_10000baseT_Full))
 275		val |= V_MI1_SOF(1);
 276	t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_CFG, val);
 277}
 278
 279#if defined(CONFIG_CHELSIO_T1_1G)
 280/*
 281 * Elmer MI1 MDIO read/write operations.
 282 */
 283static int mi1_mdio_read(struct net_device *dev, int phy_addr, int mmd_addr,
 284			 u16 reg_addr)
 285{
 286	struct adapter *adapter = dev->ml_priv;
 287	u32 addr = V_MI1_REG_ADDR(reg_addr) | V_MI1_PHY_ADDR(phy_addr);
 288	unsigned int val;
 289
 290	spin_lock(&adapter->tpi_lock);
 291	__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
 292	__t1_tpi_write(adapter,
 293			A_ELMER0_PORT0_MI1_OP, MI1_OP_DIRECT_READ);
 294	mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
 295	__t1_tpi_read(adapter, A_ELMER0_PORT0_MI1_DATA, &val);
 296	spin_unlock(&adapter->tpi_lock);
 297	return val;
 298}
 299
 300static int mi1_mdio_write(struct net_device *dev, int phy_addr, int mmd_addr,
 301			  u16 reg_addr, u16 val)
 302{
 303	struct adapter *adapter = dev->ml_priv;
 304	u32 addr = V_MI1_REG_ADDR(reg_addr) | V_MI1_PHY_ADDR(phy_addr);
 305
 306	spin_lock(&adapter->tpi_lock);
 307	__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
 308	__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, val);
 309	__t1_tpi_write(adapter,
 310			A_ELMER0_PORT0_MI1_OP, MI1_OP_DIRECT_WRITE);
 311	mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
 312	spin_unlock(&adapter->tpi_lock);
 313	return 0;
 314}
 315
 316static const struct mdio_ops mi1_mdio_ops = {
 317	.init = mi1_mdio_init,
 318	.read = mi1_mdio_read,
 319	.write = mi1_mdio_write,
 320	.mode_support = MDIO_SUPPORTS_C22
 321};
 322
 323#endif
 324
 325static int mi1_mdio_ext_read(struct net_device *dev, int phy_addr, int mmd_addr,
 326			     u16 reg_addr)
 327{
 328	struct adapter *adapter = dev->ml_priv;
 329	u32 addr = V_MI1_REG_ADDR(mmd_addr) | V_MI1_PHY_ADDR(phy_addr);
 330	unsigned int val;
 331
 332	spin_lock(&adapter->tpi_lock);
 333
 334	/* Write the address we want. */
 335	__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
 336	__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, reg_addr);
 337	__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP,
 338		       MI1_OP_INDIRECT_ADDRESS);
 339	mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
 340
 341	/* Write the operation we want. */
 342	__t1_tpi_write(adapter,
 343			A_ELMER0_PORT0_MI1_OP, MI1_OP_INDIRECT_READ);
 344	mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
 345
 346	/* Read the data. */
 347	__t1_tpi_read(adapter, A_ELMER0_PORT0_MI1_DATA, &val);
 348	spin_unlock(&adapter->tpi_lock);
 349	return val;
 350}
 351
 352static int mi1_mdio_ext_write(struct net_device *dev, int phy_addr,
 353			      int mmd_addr, u16 reg_addr, u16 val)
 354{
 355	struct adapter *adapter = dev->ml_priv;
 356	u32 addr = V_MI1_REG_ADDR(mmd_addr) | V_MI1_PHY_ADDR(phy_addr);
 357
 358	spin_lock(&adapter->tpi_lock);
 359
 360	/* Write the address we want. */
 361	__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
 362	__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, reg_addr);
 363	__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP,
 364		       MI1_OP_INDIRECT_ADDRESS);
 365	mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
 366
 367	/* Write the data. */
 368	__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, val);
 369	__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP, MI1_OP_INDIRECT_WRITE);
 370	mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
 371	spin_unlock(&adapter->tpi_lock);
 372	return 0;
 373}
 374
 375static const struct mdio_ops mi1_mdio_ext_ops = {
 376	.init = mi1_mdio_init,
 377	.read = mi1_mdio_ext_read,
 378	.write = mi1_mdio_ext_write,
 379	.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22
 380};
 381
 382enum {
 383	CH_BRD_T110_1CU,
 384	CH_BRD_N110_1F,
 385	CH_BRD_N210_1F,
 386	CH_BRD_T210_1F,
 387	CH_BRD_T210_1CU,
 388	CH_BRD_N204_4CU,
 389};
 390
 391static const struct board_info t1_board[] = {
 392	{
 393		.board		= CHBT_BOARD_CHT110,
 394		.port_number	= 1,
 395		.caps		= SUPPORTED_10000baseT_Full,
 396		.chip_term	= CHBT_TERM_T1,
 397		.chip_mac	= CHBT_MAC_PM3393,
 398		.chip_phy	= CHBT_PHY_MY3126,
 399		.clock_core	= 125000000,
 400		.clock_mc3	= 150000000,
 401		.clock_mc4	= 125000000,
 402		.espi_nports	= 1,
 403		.clock_elmer0	= 44,
 404		.mdio_mdien	= 1,
 405		.mdio_mdiinv	= 1,
 406		.mdio_mdc	= 1,
 407		.mdio_phybaseaddr = 1,
 408		.gmac		= &t1_pm3393_ops,
 409		.gphy		= &t1_my3126_ops,
 410		.mdio_ops	= &mi1_mdio_ext_ops,
 411		.desc		= "Chelsio T110 1x10GBase-CX4 TOE",
 412	},
 413
 414	{
 415		.board		= CHBT_BOARD_N110,
 416		.port_number	= 1,
 417		.caps		= SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE,
 418		.chip_term	= CHBT_TERM_T1,
 419		.chip_mac	= CHBT_MAC_PM3393,
 420		.chip_phy	= CHBT_PHY_88X2010,
 421		.clock_core	= 125000000,
 422		.espi_nports	= 1,
 423		.clock_elmer0	= 44,
 424		.mdio_mdien	= 0,
 425		.mdio_mdiinv	= 0,
 426		.mdio_mdc	= 1,
 427		.mdio_phybaseaddr = 0,
 428		.gmac		= &t1_pm3393_ops,
 429		.gphy		= &t1_mv88x201x_ops,
 430		.mdio_ops	= &mi1_mdio_ext_ops,
 431		.desc		= "Chelsio N110 1x10GBaseX NIC",
 432	},
 433
 434	{
 435		.board		= CHBT_BOARD_N210,
 436		.port_number	= 1,
 437		.caps		= SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE,
 438		.chip_term	= CHBT_TERM_T2,
 439		.chip_mac	= CHBT_MAC_PM3393,
 440		.chip_phy	= CHBT_PHY_88X2010,
 441		.clock_core	= 125000000,
 442		.espi_nports	= 1,
 443		.clock_elmer0	= 44,
 444		.mdio_mdien	= 0,
 445		.mdio_mdiinv	= 0,
 446		.mdio_mdc	= 1,
 447		.mdio_phybaseaddr = 0,
 448		.gmac		= &t1_pm3393_ops,
 449		.gphy		= &t1_mv88x201x_ops,
 450		.mdio_ops	= &mi1_mdio_ext_ops,
 451		.desc		= "Chelsio N210 1x10GBaseX NIC",
 452	},
 453
 454	{
 455		.board		= CHBT_BOARD_CHT210,
 456		.port_number	= 1,
 457		.caps		= SUPPORTED_10000baseT_Full,
 458		.chip_term	= CHBT_TERM_T2,
 459		.chip_mac	= CHBT_MAC_PM3393,
 460		.chip_phy	= CHBT_PHY_88X2010,
 461		.clock_core	= 125000000,
 462		.clock_mc3	= 133000000,
 463		.clock_mc4	= 125000000,
 464		.espi_nports	= 1,
 465		.clock_elmer0	= 44,
 466		.mdio_mdien	= 0,
 467		.mdio_mdiinv	= 0,
 468		.mdio_mdc	= 1,
 469		.mdio_phybaseaddr = 0,
 470		.gmac		= &t1_pm3393_ops,
 471		.gphy		= &t1_mv88x201x_ops,
 472		.mdio_ops	= &mi1_mdio_ext_ops,
 473		.desc		= "Chelsio T210 1x10GBaseX TOE",
 474	},
 475
 476	{
 477		.board		= CHBT_BOARD_CHT210,
 478		.port_number	= 1,
 479		.caps		= SUPPORTED_10000baseT_Full,
 480		.chip_term	= CHBT_TERM_T2,
 481		.chip_mac	= CHBT_MAC_PM3393,
 482		.chip_phy	= CHBT_PHY_MY3126,
 483		.clock_core	= 125000000,
 484		.clock_mc3	= 133000000,
 485		.clock_mc4	= 125000000,
 486		.espi_nports	= 1,
 487		.clock_elmer0	= 44,
 488		.mdio_mdien	= 1,
 489		.mdio_mdiinv	= 1,
 490		.mdio_mdc	= 1,
 491		.mdio_phybaseaddr = 1,
 492		.gmac		= &t1_pm3393_ops,
 493		.gphy		= &t1_my3126_ops,
 494		.mdio_ops	= &mi1_mdio_ext_ops,
 495		.desc		= "Chelsio T210 1x10GBase-CX4 TOE",
 496	},
 497
 498#ifdef CONFIG_CHELSIO_T1_1G
 499	{
 500		.board		= CHBT_BOARD_CHN204,
 501		.port_number	= 4,
 502		.caps		= SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full
 503				| SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full
 504				| SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg |
 505				  SUPPORTED_PAUSE | SUPPORTED_TP,
 506		.chip_term	= CHBT_TERM_T2,
 507		.chip_mac	= CHBT_MAC_VSC7321,
 508		.chip_phy	= CHBT_PHY_88E1111,
 509		.clock_core	= 100000000,
 510		.espi_nports	= 4,
 511		.clock_elmer0	= 44,
 512		.mdio_mdien	= 0,
 513		.mdio_mdiinv	= 0,
 514		.mdio_mdc	= 0,
 515		.mdio_phybaseaddr = 4,
 516		.gmac		= &t1_vsc7326_ops,
 517		.gphy		= &t1_mv88e1xxx_ops,
 518		.mdio_ops	= &mi1_mdio_ops,
 519		.desc		= "Chelsio N204 4x100/1000BaseT NIC",
 520	},
 521#endif
 522
 523};
 524
 525const struct pci_device_id t1_pci_tbl[] = {
 526	CH_DEVICE(8, 0, CH_BRD_T110_1CU),
 527	CH_DEVICE(8, 1, CH_BRD_T110_1CU),
 528	CH_DEVICE(7, 0, CH_BRD_N110_1F),
 529	CH_DEVICE(10, 1, CH_BRD_N210_1F),
 530	CH_DEVICE(11, 1, CH_BRD_T210_1F),
 531	CH_DEVICE(14, 1, CH_BRD_T210_1CU),
 532	CH_DEVICE(16, 1, CH_BRD_N204_4CU),
 533	{ 0 }
 534};
 535
 536MODULE_DEVICE_TABLE(pci, t1_pci_tbl);
 537
 538/*
 539 * Return the board_info structure with a given index.  Out-of-range indices
 540 * return NULL.
 541 */
 542const struct board_info *t1_get_board_info(unsigned int board_id)
 543{
 544	return board_id < ARRAY_SIZE(t1_board) ? &t1_board[board_id] : NULL;
 545}
 546
 547struct chelsio_vpd_t {
 548	u32 format_version;
 549	u8 serial_number[16];
 550	u8 mac_base_address[6];
 551	u8 pad[2];           /* make multiple-of-4 size requirement explicit */
 552};
 553
 554#define EEPROMSIZE        (8 * 1024)
 555#define EEPROM_MAX_POLL   4
 556
 557/*
 558 * Read SEEPROM. A zero is written to the flag register when the address is
 559 * written to the Control register. The hardware device will set the flag to a
 560 * one when 4B have been transferred to the Data register.
 561 */
 562int t1_seeprom_read(adapter_t *adapter, u32 addr, __le32 *data)
 563{
 564	int i = EEPROM_MAX_POLL;
 565	u16 val;
 566	u32 v;
 567
 568	if (addr >= EEPROMSIZE || (addr & 3))
 569		return -EINVAL;
 570
 571	pci_write_config_word(adapter->pdev, A_PCICFG_VPD_ADDR, (u16)addr);
 572	do {
 573		udelay(50);
 574		pci_read_config_word(adapter->pdev, A_PCICFG_VPD_ADDR, &val);
 575	} while (!(val & F_VPD_OP_FLAG) && --i);
 576
 577	if (!(val & F_VPD_OP_FLAG)) {
 578		pr_err("%s: reading EEPROM address 0x%x failed\n",
 579		       adapter->name, addr);
 580		return -EIO;
 581	}
 582	pci_read_config_dword(adapter->pdev, A_PCICFG_VPD_DATA, &v);
 583	*data = cpu_to_le32(v);
 584	return 0;
 585}
 586
 587static int t1_eeprom_vpd_get(adapter_t *adapter, struct chelsio_vpd_t *vpd)
 588{
 589	int addr, ret = 0;
 590
 591	for (addr = 0; !ret && addr < sizeof(*vpd); addr += sizeof(u32))
 592		ret = t1_seeprom_read(adapter, addr,
 593				      (__le32 *)((u8 *)vpd + addr));
 594
 595	return ret;
 596}
 597
 598/*
 599 * Read a port's MAC address from the VPD ROM.
 600 */
 601static int vpd_macaddress_get(adapter_t *adapter, int index, u8 mac_addr[])
 602{
 603	struct chelsio_vpd_t vpd;
 604
 605	if (t1_eeprom_vpd_get(adapter, &vpd))
 606		return 1;
 607	memcpy(mac_addr, vpd.mac_base_address, 5);
 608	mac_addr[5] = vpd.mac_base_address[5] + index;
 609	return 0;
 610}
 611
 612/*
 613 * Set up the MAC/PHY according to the requested link settings.
 614 *
 615 * If the PHY can auto-negotiate first decide what to advertise, then
 616 * enable/disable auto-negotiation as desired and reset.
 617 *
 618 * If the PHY does not auto-negotiate we just reset it.
 619 *
 620 * If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
 621 * otherwise do it later based on the outcome of auto-negotiation.
 622 */
 623int t1_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc)
 624{
 625	unsigned int fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
 626
 627	if (lc->supported & SUPPORTED_Autoneg) {
 628		lc->advertising &= ~(ADVERTISED_ASYM_PAUSE | ADVERTISED_PAUSE);
 629		if (fc) {
 630			if (fc == ((PAUSE_RX | PAUSE_TX) &
 631				   (mac->adapter->params.nports < 2)))
 632				lc->advertising |= ADVERTISED_PAUSE;
 633			else {
 634				lc->advertising |= ADVERTISED_ASYM_PAUSE;
 635				if (fc == PAUSE_RX)
 636					lc->advertising |= ADVERTISED_PAUSE;
 637			}
 638		}
 639		phy->ops->advertise(phy, lc->advertising);
 640
 641		if (lc->autoneg == AUTONEG_DISABLE) {
 642			lc->speed = lc->requested_speed;
 643			lc->duplex = lc->requested_duplex;
 644			lc->fc = (unsigned char)fc;
 645			mac->ops->set_speed_duplex_fc(mac, lc->speed,
 646						      lc->duplex, fc);
 647			/* Also disables autoneg */
 648			phy->state = PHY_AUTONEG_RDY;
 649			phy->ops->set_speed_duplex(phy, lc->speed, lc->duplex);
 650			phy->ops->reset(phy, 0);
 651		} else {
 652			phy->state = PHY_AUTONEG_EN;
 653			phy->ops->autoneg_enable(phy); /* also resets PHY */
 654		}
 655	} else {
 656		phy->state = PHY_AUTONEG_RDY;
 657		mac->ops->set_speed_duplex_fc(mac, -1, -1, fc);
 658		lc->fc = (unsigned char)fc;
 659		phy->ops->reset(phy, 0);
 660	}
 661	return 0;
 662}
 663
 664/*
 665 * External interrupt handler for boards using elmer0.
 666 */
 667int t1_elmer0_ext_intr_handler(adapter_t *adapter)
 668{
 669	struct cphy *phy;
 670	int phy_cause;
 671	u32 cause;
 672
 673	t1_tpi_read(adapter, A_ELMER0_INT_CAUSE, &cause);
 674
 675	switch (board_info(adapter)->board) {
 676#ifdef CONFIG_CHELSIO_T1_1G
 677	case CHBT_BOARD_CHT204:
 678	case CHBT_BOARD_CHT204E:
 679	case CHBT_BOARD_CHN204:
 680	case CHBT_BOARD_CHT204V: {
 681		int i, port_bit;
 682		for_each_port(adapter, i) {
 683			port_bit = i + 1;
 684			if (!(cause & (1 << port_bit)))
 685				continue;
 686
 687			phy = adapter->port[i].phy;
 688			phy_cause = phy->ops->interrupt_handler(phy);
 689			if (phy_cause & cphy_cause_link_change)
 690				t1_link_changed(adapter, i);
 691		}
 692		break;
 693	}
 694	case CHBT_BOARD_CHT101:
 695		if (cause & ELMER0_GP_BIT1) { /* Marvell 88E1111 interrupt */
 696			phy = adapter->port[0].phy;
 697			phy_cause = phy->ops->interrupt_handler(phy);
 698			if (phy_cause & cphy_cause_link_change)
 699				t1_link_changed(adapter, 0);
 700		}
 701		break;
 702	case CHBT_BOARD_7500: {
 703		int p;
 704		/*
 705		 * Elmer0's interrupt cause isn't useful here because there is
 706		 * only one bit that can be set for all 4 ports.  This means
 707		 * we are forced to check every PHY's interrupt status
 708		 * register to see who initiated the interrupt.
 709		 */
 710		for_each_port(adapter, p) {
 711			phy = adapter->port[p].phy;
 712			phy_cause = phy->ops->interrupt_handler(phy);
 713			if (phy_cause & cphy_cause_link_change)
 714			    t1_link_changed(adapter, p);
 715		}
 716		break;
 717	}
 718#endif
 719	case CHBT_BOARD_CHT210:
 720	case CHBT_BOARD_N210:
 721	case CHBT_BOARD_N110:
 722		if (cause & ELMER0_GP_BIT6) { /* Marvell 88x2010 interrupt */
 723			phy = adapter->port[0].phy;
 724			phy_cause = phy->ops->interrupt_handler(phy);
 725			if (phy_cause & cphy_cause_link_change)
 726				t1_link_changed(adapter, 0);
 727		}
 728		break;
 729	case CHBT_BOARD_8000:
 730	case CHBT_BOARD_CHT110:
 731		if (netif_msg_intr(adapter))
 732			dev_dbg(&adapter->pdev->dev,
 733				"External interrupt cause 0x%x\n", cause);
 734		if (cause & ELMER0_GP_BIT1) {        /* PMC3393 INTB */
 735			struct cmac *mac = adapter->port[0].mac;
 736
 737			mac->ops->interrupt_handler(mac);
 738		}
 739		if (cause & ELMER0_GP_BIT5) {        /* XPAK MOD_DETECT */
 740			u32 mod_detect;
 741
 742			t1_tpi_read(adapter,
 743					A_ELMER0_GPI_STAT, &mod_detect);
 744			if (netif_msg_link(adapter))
 745				dev_info(&adapter->pdev->dev, "XPAK %s\n",
 746					 mod_detect ? "removed" : "inserted");
 747		}
 748		break;
 749	}
 750	t1_tpi_write(adapter, A_ELMER0_INT_CAUSE, cause);
 751	return 0;
 752}
 753
 754/* Enables all interrupts. */
 755void t1_interrupts_enable(adapter_t *adapter)
 756{
 757	unsigned int i;
 758
 759	adapter->slow_intr_mask = F_PL_INTR_SGE_ERR | F_PL_INTR_TP;
 760
 761	t1_sge_intr_enable(adapter->sge);
 762	t1_tp_intr_enable(adapter->tp);
 763	if (adapter->espi) {
 764		adapter->slow_intr_mask |= F_PL_INTR_ESPI;
 765		t1_espi_intr_enable(adapter->espi);
 766	}
 767
 768	/* Enable MAC/PHY interrupts for each port. */
 769	for_each_port(adapter, i) {
 770		adapter->port[i].mac->ops->interrupt_enable(adapter->port[i].mac);
 771		adapter->port[i].phy->ops->interrupt_enable(adapter->port[i].phy);
 772	}
 773
 774	/* Enable PCIX & external chip interrupts on ASIC boards. */
 775	if (t1_is_asic(adapter)) {
 776		u32 pl_intr = readl(adapter->regs + A_PL_ENABLE);
 777
 778		/* PCI-X interrupts */
 779		pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_ENABLE,
 780				       0xffffffff);
 781
 782		adapter->slow_intr_mask |= F_PL_INTR_EXT | F_PL_INTR_PCIX;
 783		pl_intr |= F_PL_INTR_EXT | F_PL_INTR_PCIX;
 784		writel(pl_intr, adapter->regs + A_PL_ENABLE);
 785	}
 786}
 787
 788/* Disables all interrupts. */
 789void t1_interrupts_disable(adapter_t* adapter)
 790{
 791	unsigned int i;
 792
 793	t1_sge_intr_disable(adapter->sge);
 794	t1_tp_intr_disable(adapter->tp);
 795	if (adapter->espi)
 796		t1_espi_intr_disable(adapter->espi);
 797
 798	/* Disable MAC/PHY interrupts for each port. */
 799	for_each_port(adapter, i) {
 800		adapter->port[i].mac->ops->interrupt_disable(adapter->port[i].mac);
 801		adapter->port[i].phy->ops->interrupt_disable(adapter->port[i].phy);
 802	}
 803
 804	/* Disable PCIX & external chip interrupts. */
 805	if (t1_is_asic(adapter))
 806		writel(0, adapter->regs + A_PL_ENABLE);
 807
 808	/* PCI-X interrupts */
 809	pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_ENABLE, 0);
 810
 811	adapter->slow_intr_mask = 0;
 812}
 813
 814/* Clears all interrupts */
 815void t1_interrupts_clear(adapter_t* adapter)
 816{
 817	unsigned int i;
 818
 819	t1_sge_intr_clear(adapter->sge);
 820	t1_tp_intr_clear(adapter->tp);
 821	if (adapter->espi)
 822		t1_espi_intr_clear(adapter->espi);
 823
 824	/* Clear MAC/PHY interrupts for each port. */
 825	for_each_port(adapter, i) {
 826		adapter->port[i].mac->ops->interrupt_clear(adapter->port[i].mac);
 827		adapter->port[i].phy->ops->interrupt_clear(adapter->port[i].phy);
 828	}
 829
 830	/* Enable interrupts for external devices. */
 831	if (t1_is_asic(adapter)) {
 832		u32 pl_intr = readl(adapter->regs + A_PL_CAUSE);
 833
 834		writel(pl_intr | F_PL_INTR_EXT | F_PL_INTR_PCIX,
 835		       adapter->regs + A_PL_CAUSE);
 836	}
 837
 838	/* PCI-X interrupts */
 839	pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE, 0xffffffff);
 840}
 841
 842/*
 843 * Slow path interrupt handler for ASICs.
 844 */
 845static int asic_slow_intr(adapter_t *adapter)
 846{
 847	u32 cause = readl(adapter->regs + A_PL_CAUSE);
 848
 849	cause &= adapter->slow_intr_mask;
 850	if (!cause)
 851		return 0;
 852	if (cause & F_PL_INTR_SGE_ERR)
 853		t1_sge_intr_error_handler(adapter->sge);
 854	if (cause & F_PL_INTR_TP)
 855		t1_tp_intr_handler(adapter->tp);
 856	if (cause & F_PL_INTR_ESPI)
 857		t1_espi_intr_handler(adapter->espi);
 858	if (cause & F_PL_INTR_PCIX)
 859		t1_pci_intr_handler(adapter);
 860	if (cause & F_PL_INTR_EXT)
 861		t1_elmer0_ext_intr(adapter);
 862
 863	/* Clear the interrupts just processed. */
 864	writel(cause, adapter->regs + A_PL_CAUSE);
 865	readl(adapter->regs + A_PL_CAUSE); /* flush writes */
 866	return 1;
 867}
 868
 869int t1_slow_intr_handler(adapter_t *adapter)
 870{
 871#ifdef CONFIG_CHELSIO_T1_1G
 872	if (!t1_is_asic(adapter))
 873		return fpga_slow_intr(adapter);
 874#endif
 875	return asic_slow_intr(adapter);
 876}
 877
 878/* Power sequencing is a work-around for Intel's XPAKs. */
 879static void power_sequence_xpak(adapter_t* adapter)
 880{
 881	u32 mod_detect;
 882	u32 gpo;
 883
 884	/* Check for XPAK */
 885	t1_tpi_read(adapter, A_ELMER0_GPI_STAT, &mod_detect);
 886	if (!(ELMER0_GP_BIT5 & mod_detect)) {
 887		/* XPAK is present */
 888		t1_tpi_read(adapter, A_ELMER0_GPO, &gpo);
 889		gpo |= ELMER0_GP_BIT18;
 890		t1_tpi_write(adapter, A_ELMER0_GPO, gpo);
 891	}
 892}
 893
 894int t1_get_board_rev(adapter_t *adapter, const struct board_info *bi,
 895		     struct adapter_params *p)
 896{
 897	p->chip_version = bi->chip_term;
 898	p->is_asic = (p->chip_version != CHBT_TERM_FPGA);
 899	if (p->chip_version == CHBT_TERM_T1 ||
 900	    p->chip_version == CHBT_TERM_T2 ||
 901	    p->chip_version == CHBT_TERM_FPGA) {
 902		u32 val = readl(adapter->regs + A_TP_PC_CONFIG);
 903
 904		val = G_TP_PC_REV(val);
 905		if (val == 2)
 906			p->chip_revision = TERM_T1B;
 907		else if (val == 3)
 908			p->chip_revision = TERM_T2;
 909		else
 910			return -1;
 911	} else
 912		return -1;
 913	return 0;
 914}
 915
 916/*
 917 * Enable board components other than the Chelsio chip, such as external MAC
 918 * and PHY.
 919 */
 920static int board_init(adapter_t *adapter, const struct board_info *bi)
 921{
 922	switch (bi->board) {
 923	case CHBT_BOARD_8000:
 924	case CHBT_BOARD_N110:
 925	case CHBT_BOARD_N210:
 926	case CHBT_BOARD_CHT210:
 927		t1_tpi_par(adapter, 0xf);
 928		t1_tpi_write(adapter, A_ELMER0_GPO, 0x800);
 929		break;
 930	case CHBT_BOARD_CHT110:
 931		t1_tpi_par(adapter, 0xf);
 932		t1_tpi_write(adapter, A_ELMER0_GPO, 0x1800);
 933
 934		/* TBD XXX Might not need.  This fixes a problem
 935		 *         described in the Intel SR XPAK errata.
 936		 */
 937		power_sequence_xpak(adapter);
 938		break;
 939#ifdef CONFIG_CHELSIO_T1_1G
 940	case CHBT_BOARD_CHT204E:
 941		/* add config space write here */
 942	case CHBT_BOARD_CHT204:
 943	case CHBT_BOARD_CHT204V:
 944	case CHBT_BOARD_CHN204:
 945		t1_tpi_par(adapter, 0xf);
 946		t1_tpi_write(adapter, A_ELMER0_GPO, 0x804);
 947		break;
 948	case CHBT_BOARD_CHT101:
 949	case CHBT_BOARD_7500:
 950		t1_tpi_par(adapter, 0xf);
 951		t1_tpi_write(adapter, A_ELMER0_GPO, 0x1804);
 952		break;
 953#endif
 954	}
 955	return 0;
 956}
 957
 958/*
 959 * Initialize and configure the Terminator HW modules.  Note that external
 960 * MAC and PHYs are initialized separately.
 961 */
 962int t1_init_hw_modules(adapter_t *adapter)
 963{
 964	int err = -EIO;
 965	const struct board_info *bi = board_info(adapter);
 966
 967	if (!bi->clock_mc4) {
 968		u32 val = readl(adapter->regs + A_MC4_CFG);
 969
 970		writel(val | F_READY | F_MC4_SLOW, adapter->regs + A_MC4_CFG);
 971		writel(F_M_BUS_ENABLE | F_TCAM_RESET,
 972		       adapter->regs + A_MC5_CONFIG);
 973	}
 974
 975	if (adapter->espi && t1_espi_init(adapter->espi, bi->chip_mac,
 976					  bi->espi_nports))
 977		goto out_err;
 978
 979	if (t1_tp_reset(adapter->tp, &adapter->params.tp, bi->clock_core))
 980		goto out_err;
 981
 982	err = t1_sge_configure(adapter->sge, &adapter->params.sge);
 983	if (err)
 984		goto out_err;
 985
 986	err = 0;
 987out_err:
 988	return err;
 989}
 990
 991/*
 992 * Determine a card's PCI mode.
 993 */
 994static void get_pci_mode(adapter_t *adapter, struct chelsio_pci_params *p)
 995{
 996	static const unsigned short speed_map[] = { 33, 66, 100, 133 };
 997	u32 pci_mode;
 998
 999	pci_read_config_dword(adapter->pdev, A_PCICFG_MODE, &pci_mode);
1000	p->speed = speed_map[G_PCI_MODE_CLK(pci_mode)];
1001	p->width = (pci_mode & F_PCI_MODE_64BIT) ? 64 : 32;
1002	p->is_pcix = (pci_mode & F_PCI_MODE_PCIX) != 0;
1003}
1004
1005/*
1006 * Release the structures holding the SW per-Terminator-HW-module state.
1007 */
1008void t1_free_sw_modules(adapter_t *adapter)
1009{
1010	unsigned int i;
1011
1012	for_each_port(adapter, i) {
1013		struct cmac *mac = adapter->port[i].mac;
1014		struct cphy *phy = adapter->port[i].phy;
1015
1016		if (mac)
1017			mac->ops->destroy(mac);
1018		if (phy)
1019			phy->ops->destroy(phy);
1020	}
1021
1022	if (adapter->sge)
1023		t1_sge_destroy(adapter->sge);
1024	if (adapter->tp)
1025		t1_tp_destroy(adapter->tp);
1026	if (adapter->espi)
1027		t1_espi_destroy(adapter->espi);
1028}
1029
1030static void init_link_config(struct link_config *lc,
1031			     const struct board_info *bi)
1032{
1033	lc->supported = bi->caps;
1034	lc->requested_speed = lc->speed = SPEED_INVALID;
1035	lc->requested_duplex = lc->duplex = DUPLEX_INVALID;
1036	lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
1037	if (lc->supported & SUPPORTED_Autoneg) {
1038		lc->advertising = lc->supported;
1039		lc->autoneg = AUTONEG_ENABLE;
1040		lc->requested_fc |= PAUSE_AUTONEG;
1041	} else {
1042		lc->advertising = 0;
1043		lc->autoneg = AUTONEG_DISABLE;
1044	}
1045}
1046
1047/*
1048 * Allocate and initialize the data structures that hold the SW state of
1049 * the Terminator HW modules.
1050 */
1051int t1_init_sw_modules(adapter_t *adapter, const struct board_info *bi)
1052{
1053	unsigned int i;
1054
1055	adapter->params.brd_info = bi;
1056	adapter->params.nports = bi->port_number;
1057	adapter->params.stats_update_period = bi->gmac->stats_update_period;
1058
1059	adapter->sge = t1_sge_create(adapter, &adapter->params.sge);
1060	if (!adapter->sge) {
1061		pr_err("%s: SGE initialization failed\n",
1062		       adapter->name);
1063		goto error;
1064	}
1065
1066	if (bi->espi_nports && !(adapter->espi = t1_espi_create(adapter))) {
1067		pr_err("%s: ESPI initialization failed\n",
1068		       adapter->name);
1069		goto error;
1070	}
1071
1072	adapter->tp = t1_tp_create(adapter, &adapter->params.tp);
1073	if (!adapter->tp) {
1074		pr_err("%s: TP initialization failed\n",
1075		       adapter->name);
1076		goto error;
1077	}
1078
1079	board_init(adapter, bi);
1080	bi->mdio_ops->init(adapter, bi);
1081	if (bi->gphy->reset)
1082		bi->gphy->reset(adapter);
1083	if (bi->gmac->reset)
1084		bi->gmac->reset(adapter);
1085
1086	for_each_port(adapter, i) {
1087		u8 hw_addr[6];
1088		struct cmac *mac;
1089		int phy_addr = bi->mdio_phybaseaddr + i;
1090
1091		adapter->port[i].phy = bi->gphy->create(adapter->port[i].dev,
1092							phy_addr, bi->mdio_ops);
1093		if (!adapter->port[i].phy) {
1094			pr_err("%s: PHY %d initialization failed\n",
1095			       adapter->name, i);
1096			goto error;
1097		}
1098
1099		adapter->port[i].mac = mac = bi->gmac->create(adapter, i);
1100		if (!mac) {
1101			pr_err("%s: MAC %d initialization failed\n",
1102			       adapter->name, i);
1103			goto error;
1104		}
1105
1106		/*
1107		 * Get the port's MAC addresses either from the EEPROM if one
1108		 * exists or the one hardcoded in the MAC.
1109		 */
1110		if (!t1_is_asic(adapter) || bi->chip_mac == CHBT_MAC_DUMMY)
1111			mac->ops->macaddress_get(mac, hw_addr);
1112		else if (vpd_macaddress_get(adapter, i, hw_addr)) {
1113			pr_err("%s: could not read MAC address from VPD ROM\n",
1114			       adapter->port[i].dev->name);
1115			goto error;
1116		}
1117		memcpy(adapter->port[i].dev->dev_addr, hw_addr, ETH_ALEN);
1118		init_link_config(&adapter->port[i].link_config, bi);
1119	}
1120
1121	get_pci_mode(adapter, &adapter->params.pci);
1122	t1_interrupts_clear(adapter);
1123	return 0;
1124
1125error:
1126	t1_free_sw_modules(adapter);
1127	return -1;
1128}