/drivers/net/ethernet/intel/igb/e1000_phy.c

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /* Copyright(c) 2007 - 2018 Intel Corporation. */
  3. #include <linux/if_ether.h>
  4. #include <linux/delay.h>
  5. #include "e1000_mac.h"
  6. #include "e1000_phy.h"
  7. static s32 igb_phy_setup_autoneg(struct e1000_hw *hw);
  8. static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw,
  9. u16 *phy_ctrl);
  10. static s32 igb_wait_autoneg(struct e1000_hw *hw);
  11. static s32 igb_set_master_slave_mode(struct e1000_hw *hw);
  12. /* Cable length tables */
  13. static const u16 e1000_m88_cable_length_table[] = {
  14. 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
  15. static const u16 e1000_igp_2_cable_length_table[] = {
  16. 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
  17. 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
  18. 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
  19. 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
  20. 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
  21. 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
  22. 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
  23. 104, 109, 114, 118, 121, 124};
  24. /**
  25. * igb_check_reset_block - Check if PHY reset is blocked
  26. * @hw: pointer to the HW structure
  27. *
  28. * Read the PHY management control register and check whether a PHY reset
  29. * is blocked. If a reset is not blocked return 0, otherwise
  30. * return E1000_BLK_PHY_RESET (12).
  31. **/
  32. s32 igb_check_reset_block(struct e1000_hw *hw)
  33. {
  34. u32 manc;
  35. manc = rd32(E1000_MANC);
  36. return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? E1000_BLK_PHY_RESET : 0;
  37. }
  38. /**
  39. * igb_get_phy_id - Retrieve the PHY ID and revision
  40. * @hw: pointer to the HW structure
  41. *
  42. * Reads the PHY registers and stores the PHY ID and possibly the PHY
  43. * revision in the hardware structure.
  44. **/
  45. s32 igb_get_phy_id(struct e1000_hw *hw)
  46. {
  47. struct e1000_phy_info *phy = &hw->phy;
  48. s32 ret_val = 0;
  49. u16 phy_id;
  50. /* ensure PHY page selection to fix misconfigured i210 */
  51. if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
  52. phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0);
  53. ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
  54. if (ret_val)
  55. goto out;
  56. phy->id = (u32)(phy_id << 16);
  57. udelay(20);
  58. ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
  59. if (ret_val)
  60. goto out;
  61. phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
  62. phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
  63. out:
  64. return ret_val;
  65. }
  66. /**
  67. * igb_phy_reset_dsp - Reset PHY DSP
  68. * @hw: pointer to the HW structure
  69. *
  70. * Reset the digital signal processor.
  71. **/
  72. static s32 igb_phy_reset_dsp(struct e1000_hw *hw)
  73. {
  74. s32 ret_val = 0;
  75. if (!(hw->phy.ops.write_reg))
  76. goto out;
  77. ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
  78. if (ret_val)
  79. goto out;
  80. ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
  81. out:
  82. return ret_val;
  83. }
  84. /**
  85. * igb_read_phy_reg_mdic - Read MDI control register
  86. * @hw: pointer to the HW structure
  87. * @offset: register offset to be read
  88. * @data: pointer to the read data
  89. *
  90. * Reads the MDI control register in the PHY at offset and stores the
  91. * information read to data.
  92. **/
  93. s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
  94. {
  95. struct e1000_phy_info *phy = &hw->phy;
  96. u32 i, mdic = 0;
  97. s32 ret_val = 0;
  98. if (offset > MAX_PHY_REG_ADDRESS) {
  99. hw_dbg("PHY Address %d is out of range\n", offset);
  100. ret_val = -E1000_ERR_PARAM;
  101. goto out;
  102. }
  103. /* Set up Op-code, Phy Address, and register offset in the MDI
  104. * Control register. The MAC will take care of interfacing with the
  105. * PHY to retrieve the desired data.
  106. */
  107. mdic = ((offset << E1000_MDIC_REG_SHIFT) |
  108. (phy->addr << E1000_MDIC_PHY_SHIFT) |
  109. (E1000_MDIC_OP_READ));
  110. wr32(E1000_MDIC, mdic);
  111. /* Poll the ready bit to see if the MDI read completed
  112. * Increasing the time out as testing showed failures with
  113. * the lower time out
  114. */
  115. for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
  116. udelay(50);
  117. mdic = rd32(E1000_MDIC);
  118. if (mdic & E1000_MDIC_READY)
  119. break;
  120. }
  121. if (!(mdic & E1000_MDIC_READY)) {
  122. hw_dbg("MDI Read did not complete\n");
  123. ret_val = -E1000_ERR_PHY;
  124. goto out;
  125. }
  126. if (mdic & E1000_MDIC_ERROR) {
  127. hw_dbg("MDI Error\n");
  128. ret_val = -E1000_ERR_PHY;
  129. goto out;
  130. }
  131. *data = (u16) mdic;
  132. out:
  133. return ret_val;
  134. }
  135. /**
  136. * igb_write_phy_reg_mdic - Write MDI control register
  137. * @hw: pointer to the HW structure
  138. * @offset: register offset to write to
  139. * @data: data to write to register at offset
  140. *
  141. * Writes data to MDI control register in the PHY at offset.
  142. **/
  143. s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
  144. {
  145. struct e1000_phy_info *phy = &hw->phy;
  146. u32 i, mdic = 0;
  147. s32 ret_val = 0;
  148. if (offset > MAX_PHY_REG_ADDRESS) {
  149. hw_dbg("PHY Address %d is out of range\n", offset);
  150. ret_val = -E1000_ERR_PARAM;
  151. goto out;
  152. }
  153. /* Set up Op-code, Phy Address, and register offset in the MDI
  154. * Control register. The MAC will take care of interfacing with the
  155. * PHY to retrieve the desired data.
  156. */
  157. mdic = (((u32)data) |
  158. (offset << E1000_MDIC_REG_SHIFT) |
  159. (phy->addr << E1000_MDIC_PHY_SHIFT) |
  160. (E1000_MDIC_OP_WRITE));
  161. wr32(E1000_MDIC, mdic);
  162. /* Poll the ready bit to see if the MDI read completed
  163. * Increasing the time out as testing showed failures with
  164. * the lower time out
  165. */
  166. for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
  167. udelay(50);
  168. mdic = rd32(E1000_MDIC);
  169. if (mdic & E1000_MDIC_READY)
  170. break;
  171. }
  172. if (!(mdic & E1000_MDIC_READY)) {
  173. hw_dbg("MDI Write did not complete\n");
  174. ret_val = -E1000_ERR_PHY;
  175. goto out;
  176. }
  177. if (mdic & E1000_MDIC_ERROR) {
  178. hw_dbg("MDI Error\n");
  179. ret_val = -E1000_ERR_PHY;
  180. goto out;
  181. }
  182. out:
  183. return ret_val;
  184. }
  185. /**
  186. * igb_read_phy_reg_i2c - Read PHY register using i2c
  187. * @hw: pointer to the HW structure
  188. * @offset: register offset to be read
  189. * @data: pointer to the read data
  190. *
  191. * Reads the PHY register at offset using the i2c interface and stores the
  192. * retrieved information in data.
  193. **/
  194. s32 igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data)
  195. {
  196. struct e1000_phy_info *phy = &hw->phy;
  197. u32 i, i2ccmd = 0;
  198. /* Set up Op-code, Phy Address, and register address in the I2CCMD
  199. * register. The MAC will take care of interfacing with the
  200. * PHY to retrieve the desired data.
  201. */
  202. i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
  203. (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
  204. (E1000_I2CCMD_OPCODE_READ));
  205. wr32(E1000_I2CCMD, i2ccmd);
  206. /* Poll the ready bit to see if the I2C read completed */
  207. for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
  208. udelay(50);
  209. i2ccmd = rd32(E1000_I2CCMD);
  210. if (i2ccmd & E1000_I2CCMD_READY)
  211. break;
  212. }
  213. if (!(i2ccmd & E1000_I2CCMD_READY)) {
  214. hw_dbg("I2CCMD Read did not complete\n");
  215. return -E1000_ERR_PHY;
  216. }
  217. if (i2ccmd & E1000_I2CCMD_ERROR) {
  218. hw_dbg("I2CCMD Error bit set\n");
  219. return -E1000_ERR_PHY;
  220. }
  221. /* Need to byte-swap the 16-bit value. */
  222. *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);
  223. return 0;
  224. }
  225. /**
  226. * igb_write_phy_reg_i2c - Write PHY register using i2c
  227. * @hw: pointer to the HW structure
  228. * @offset: register offset to write to
  229. * @data: data to write at register offset
  230. *
  231. * Writes the data to PHY register at the offset using the i2c interface.
  232. **/
  233. s32 igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data)
  234. {
  235. struct e1000_phy_info *phy = &hw->phy;
  236. u32 i, i2ccmd = 0;
  237. u16 phy_data_swapped;
  238. /* Prevent overwriting SFP I2C EEPROM which is at A0 address.*/
  239. if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) {
  240. hw_dbg("PHY I2C Address %d is out of range.\n",
  241. hw->phy.addr);
  242. return -E1000_ERR_CONFIG;
  243. }
  244. /* Swap the data bytes for the I2C interface */
  245. phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
  246. /* Set up Op-code, Phy Address, and register address in the I2CCMD
  247. * register. The MAC will take care of interfacing with the
  248. * PHY to retrieve the desired data.
  249. */
  250. i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
  251. (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
  252. E1000_I2CCMD_OPCODE_WRITE |
  253. phy_data_swapped);
  254. wr32(E1000_I2CCMD, i2ccmd);
  255. /* Poll the ready bit to see if the I2C read completed */
  256. for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
  257. udelay(50);
  258. i2ccmd = rd32(E1000_I2CCMD);
  259. if (i2ccmd & E1000_I2CCMD_READY)
  260. break;
  261. }
  262. if (!(i2ccmd & E1000_I2CCMD_READY)) {
  263. hw_dbg("I2CCMD Write did not complete\n");
  264. return -E1000_ERR_PHY;
  265. }
  266. if (i2ccmd & E1000_I2CCMD_ERROR) {
  267. hw_dbg("I2CCMD Error bit set\n");
  268. return -E1000_ERR_PHY;
  269. }
  270. return 0;
  271. }
  272. /**
  273. * igb_read_sfp_data_byte - Reads SFP module data.
  274. * @hw: pointer to the HW structure
  275. * @offset: byte location offset to be read
  276. * @data: read data buffer pointer
  277. *
  278. * Reads one byte from SFP module data stored
  279. * in SFP resided EEPROM memory or SFP diagnostic area.
  280. * Function should be called with
  281. * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access
  282. * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters
  283. * access
  284. **/
  285. s32 igb_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data)
  286. {
  287. u32 i = 0;
  288. u32 i2ccmd = 0;
  289. u32 data_local = 0;
  290. if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) {
  291. hw_dbg("I2CCMD command address exceeds upper limit\n");
  292. return -E1000_ERR_PHY;
  293. }
  294. /* Set up Op-code, EEPROM Address,in the I2CCMD
  295. * register. The MAC will take care of interfacing with the
  296. * EEPROM to retrieve the desired data.
  297. */
  298. i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
  299. E1000_I2CCMD_OPCODE_READ);
  300. wr32(E1000_I2CCMD, i2ccmd);
  301. /* Poll the ready bit to see if the I2C read completed */
  302. for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
  303. udelay(50);
  304. data_local = rd32(E1000_I2CCMD);
  305. if (data_local & E1000_I2CCMD_READY)
  306. break;
  307. }
  308. if (!(data_local & E1000_I2CCMD_READY)) {
  309. hw_dbg("I2CCMD Read did not complete\n");
  310. return -E1000_ERR_PHY;
  311. }
  312. if (data_local & E1000_I2CCMD_ERROR) {
  313. hw_dbg("I2CCMD Error bit set\n");
  314. return -E1000_ERR_PHY;
  315. }
  316. *data = (u8) data_local & 0xFF;
  317. return 0;
  318. }
  319. /**
  320. * igb_read_phy_reg_igp - Read igp PHY register
  321. * @hw: pointer to the HW structure
  322. * @offset: register offset to be read
  323. * @data: pointer to the read data
  324. *
  325. * Acquires semaphore, if necessary, then reads the PHY register at offset
  326. * and storing the retrieved information in data. Release any acquired
  327. * semaphores before exiting.
  328. **/
  329. s32 igb_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
  330. {
  331. s32 ret_val = 0;
  332. if (!(hw->phy.ops.acquire))
  333. goto out;
  334. ret_val = hw->phy.ops.acquire(hw);
  335. if (ret_val)
  336. goto out;
  337. if (offset > MAX_PHY_MULTI_PAGE_REG) {
  338. ret_val = igb_write_phy_reg_mdic(hw,
  339. IGP01E1000_PHY_PAGE_SELECT,
  340. (u16)offset);
  341. if (ret_val) {
  342. hw->phy.ops.release(hw);
  343. goto out;
  344. }
  345. }
  346. ret_val = igb_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
  347. data);
  348. hw->phy.ops.release(hw);
  349. out:
  350. return ret_val;
  351. }
  352. /**
  353. * igb_write_phy_reg_igp - Write igp PHY register
  354. * @hw: pointer to the HW structure
  355. * @offset: register offset to write to
  356. * @data: data to write at register offset
  357. *
  358. * Acquires semaphore, if necessary, then writes the data to PHY register
  359. * at the offset. Release any acquired semaphores before exiting.
  360. **/
  361. s32 igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
  362. {
  363. s32 ret_val = 0;
  364. if (!(hw->phy.ops.acquire))
  365. goto out;
  366. ret_val = hw->phy.ops.acquire(hw);
  367. if (ret_val)
  368. goto out;
  369. if (offset > MAX_PHY_MULTI_PAGE_REG) {
  370. ret_val = igb_write_phy_reg_mdic(hw,
  371. IGP01E1000_PHY_PAGE_SELECT,
  372. (u16)offset);
  373. if (ret_val) {
  374. hw->phy.ops.release(hw);
  375. goto out;
  376. }
  377. }
  378. ret_val = igb_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
  379. data);
  380. hw->phy.ops.release(hw);
  381. out:
  382. return ret_val;
  383. }
  384. /**
  385. * igb_copper_link_setup_82580 - Setup 82580 PHY for copper link
  386. * @hw: pointer to the HW structure
  387. *
  388. * Sets up Carrier-sense on Transmit and downshift values.
  389. **/
  390. s32 igb_copper_link_setup_82580(struct e1000_hw *hw)
  391. {
  392. struct e1000_phy_info *phy = &hw->phy;
  393. s32 ret_val;
  394. u16 phy_data;
  395. if (phy->reset_disable) {
  396. ret_val = 0;
  397. goto out;
  398. }
  399. if (phy->type == e1000_phy_82580) {
  400. ret_val = hw->phy.ops.reset(hw);
  401. if (ret_val) {
  402. hw_dbg("Error resetting the PHY.\n");
  403. goto out;
  404. }
  405. }
  406. /* Enable CRS on TX. This must be set for half-duplex operation. */
  407. ret_val = phy->ops.read_reg(hw, I82580_CFG_REG, &phy_data);
  408. if (ret_val)
  409. goto out;
  410. phy_data |= I82580_CFG_ASSERT_CRS_ON_TX;
  411. /* Enable downshift */
  412. phy_data |= I82580_CFG_ENABLE_DOWNSHIFT;
  413. ret_val = phy->ops.write_reg(hw, I82580_CFG_REG, phy_data);
  414. if (ret_val)
  415. goto out;
  416. /* Set MDI/MDIX mode */
  417. ret_val = phy->ops.read_reg(hw, I82580_PHY_CTRL_2, &phy_data);
  418. if (ret_val)
  419. goto out;
  420. phy_data &= ~I82580_PHY_CTRL2_MDIX_CFG_MASK;
  421. /* Options:
  422. * 0 - Auto (default)
  423. * 1 - MDI mode
  424. * 2 - MDI-X mode
  425. */
  426. switch (hw->phy.mdix) {
  427. case 1:
  428. break;
  429. case 2:
  430. phy_data |= I82580_PHY_CTRL2_MANUAL_MDIX;
  431. break;
  432. case 0:
  433. default:
  434. phy_data |= I82580_PHY_CTRL2_AUTO_MDI_MDIX;
  435. break;
  436. }
  437. ret_val = hw->phy.ops.write_reg(hw, I82580_PHY_CTRL_2, phy_data);
  438. out:
  439. return ret_val;
  440. }
  441. /**
  442. * igb_copper_link_setup_m88 - Setup m88 PHY's for copper link
  443. * @hw: pointer to the HW structure
  444. *
  445. * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
  446. * and downshift values are set also.
  447. **/
  448. s32 igb_copper_link_setup_m88(struct e1000_hw *hw)
  449. {
  450. struct e1000_phy_info *phy = &hw->phy;
  451. s32 ret_val;
  452. u16 phy_data;
  453. if (phy->reset_disable) {
  454. ret_val = 0;
  455. goto out;
  456. }
  457. /* Enable CRS on TX. This must be set for half-duplex operation. */
  458. ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
  459. if (ret_val)
  460. goto out;
  461. phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
  462. /* Options:
  463. * MDI/MDI-X = 0 (default)
  464. * 0 - Auto for all speeds
  465. * 1 - MDI mode
  466. * 2 - MDI-X mode
  467. * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
  468. */
  469. phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
  470. switch (phy->mdix) {
  471. case 1:
  472. phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
  473. break;
  474. case 2:
  475. phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
  476. break;
  477. case 3:
  478. phy_data |= M88E1000_PSCR_AUTO_X_1000T;
  479. break;
  480. case 0:
  481. default:
  482. phy_data |= M88E1000_PSCR_AUTO_X_MODE;
  483. break;
  484. }
  485. /* Options:
  486. * disable_polarity_correction = 0 (default)
  487. * Automatic Correction for Reversed Cable Polarity
  488. * 0 - Disabled
  489. * 1 - Enabled
  490. */
  491. phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
  492. if (phy->disable_polarity_correction == 1)
  493. phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
  494. ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
  495. if (ret_val)
  496. goto out;
  497. if (phy->revision < E1000_REVISION_4) {
  498. /* Force TX_CLK in the Extended PHY Specific Control Register
  499. * to 25MHz clock.
  500. */
  501. ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
  502. &phy_data);
  503. if (ret_val)
  504. goto out;
  505. phy_data |= M88E1000_EPSCR_TX_CLK_25;
  506. if ((phy->revision == E1000_REVISION_2) &&
  507. (phy->id == M88E1111_I_PHY_ID)) {
  508. /* 82573L PHY - set the downshift counter to 5x. */
  509. phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
  510. phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
  511. } else {
  512. /* Configure Master and Slave downshift values */
  513. phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
  514. M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
  515. phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
  516. M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
  517. }
  518. ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
  519. phy_data);
  520. if (ret_val)
  521. goto out;
  522. }
  523. /* Commit the changes. */
  524. ret_val = igb_phy_sw_reset(hw);
  525. if (ret_val) {
  526. hw_dbg("Error committing the PHY changes\n");
  527. goto out;
  528. }
  529. out:
  530. return ret_val;
  531. }
  532. /**
  533. * igb_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link
  534. * @hw: pointer to the HW structure
  535. *
  536. * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's.
  537. * Also enables and sets the downshift parameters.
  538. **/
  539. s32 igb_copper_link_setup_m88_gen2(struct e1000_hw *hw)
  540. {
  541. struct e1000_phy_info *phy = &hw->phy;
  542. s32 ret_val;
  543. u16 phy_data;
  544. if (phy->reset_disable)
  545. return 0;
  546. /* Enable CRS on Tx. This must be set for half-duplex operation. */
  547. ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
  548. if (ret_val)
  549. return ret_val;
  550. /* Options:
  551. * MDI/MDI-X = 0 (default)
  552. * 0 - Auto for all speeds
  553. * 1 - MDI mode
  554. * 2 - MDI-X mode
  555. * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
  556. */
  557. phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
  558. switch (phy->mdix) {
  559. case 1:
  560. phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
  561. break;
  562. case 2:
  563. phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
  564. break;
  565. case 3:
  566. /* M88E1112 does not support this mode) */
  567. if (phy->id != M88E1112_E_PHY_ID) {
  568. phy_data |= M88E1000_PSCR_AUTO_X_1000T;
  569. break;
  570. }
  571. /* fall through */
  572. case 0:
  573. default:
  574. phy_data |= M88E1000_PSCR_AUTO_X_MODE;
  575. break;
  576. }
  577. /* Options:
  578. * disable_polarity_correction = 0 (default)
  579. * Automatic Correction for Reversed Cable Polarity
  580. * 0 - Disabled
  581. * 1 - Enabled
  582. */
  583. phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
  584. if (phy->disable_polarity_correction == 1)
  585. phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
  586. /* Enable downshift and setting it to X6 */
  587. if (phy->id == M88E1543_E_PHY_ID) {
  588. phy_data &= ~I347AT4_PSCR_DOWNSHIFT_ENABLE;
  589. ret_val =
  590. phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
  591. if (ret_val)
  592. return ret_val;
  593. ret_val = igb_phy_sw_reset(hw);
  594. if (ret_val) {
  595. hw_dbg("Error committing the PHY changes\n");
  596. return ret_val;
  597. }
  598. }
  599. phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK;
  600. phy_data |= I347AT4_PSCR_DOWNSHIFT_6X;
  601. phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE;
  602. ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
  603. if (ret_val)
  604. return ret_val;
  605. /* Commit the changes. */
  606. ret_val = igb_phy_sw_reset(hw);
  607. if (ret_val) {
  608. hw_dbg("Error committing the PHY changes\n");
  609. return ret_val;
  610. }
  611. ret_val = igb_set_master_slave_mode(hw);
  612. if (ret_val)
  613. return ret_val;
  614. return 0;
  615. }
  616. /**
  617. * igb_copper_link_setup_igp - Setup igp PHY's for copper link
  618. * @hw: pointer to the HW structure
  619. *
  620. * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
  621. * igp PHY's.
  622. **/
  623. s32 igb_copper_link_setup_igp(struct e1000_hw *hw)
  624. {
  625. struct e1000_phy_info *phy = &hw->phy;
  626. s32 ret_val;
  627. u16 data;
  628. if (phy->reset_disable) {
  629. ret_val = 0;
  630. goto out;
  631. }
  632. ret_val = phy->ops.reset(hw);
  633. if (ret_val) {
  634. hw_dbg("Error resetting the PHY.\n");
  635. goto out;
  636. }
  637. /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid
  638. * timeout issues when LFS is enabled.
  639. */
  640. msleep(100);
  641. /* The NVM settings will configure LPLU in D3 for
  642. * non-IGP1 PHYs.
  643. */
  644. if (phy->type == e1000_phy_igp) {
  645. /* disable lplu d3 during driver init */
  646. if (phy->ops.set_d3_lplu_state)
  647. ret_val = phy->ops.set_d3_lplu_state(hw, false);
  648. if (ret_val) {
  649. hw_dbg("Error Disabling LPLU D3\n");
  650. goto out;
  651. }
  652. }
  653. /* disable lplu d0 during driver init */
  654. ret_val = phy->ops.set_d0_lplu_state(hw, false);
  655. if (ret_val) {
  656. hw_dbg("Error Disabling LPLU D0\n");
  657. goto out;
  658. }
  659. /* Configure mdi-mdix settings */
  660. ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
  661. if (ret_val)
  662. goto out;
  663. data &= ~IGP01E1000_PSCR_AUTO_MDIX;
  664. switch (phy->mdix) {
  665. case 1:
  666. data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
  667. break;
  668. case 2:
  669. data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
  670. break;
  671. case 0:
  672. default:
  673. data |= IGP01E1000_PSCR_AUTO_MDIX;
  674. break;
  675. }
  676. ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
  677. if (ret_val)
  678. goto out;
  679. /* set auto-master slave resolution settings */
  680. if (hw->mac.autoneg) {
  681. /* when autonegotiation advertisement is only 1000Mbps then we
  682. * should disable SmartSpeed and enable Auto MasterSlave
  683. * resolution as hardware default.
  684. */
  685. if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
  686. /* Disable SmartSpeed */
  687. ret_val = phy->ops.read_reg(hw,
  688. IGP01E1000_PHY_PORT_CONFIG,
  689. &data);
  690. if (ret_val)
  691. goto out;
  692. data &= ~IGP01E1000_PSCFR_SMART_SPEED;
  693. ret_val = phy->ops.write_reg(hw,
  694. IGP01E1000_PHY_PORT_CONFIG,
  695. data);
  696. if (ret_val)
  697. goto out;
  698. /* Set auto Master/Slave resolution process */
  699. ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
  700. if (ret_val)
  701. goto out;
  702. data &= ~CR_1000T_MS_ENABLE;
  703. ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
  704. if (ret_val)
  705. goto out;
  706. }
  707. ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
  708. if (ret_val)
  709. goto out;
  710. /* load defaults for future use */
  711. phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ?
  712. ((data & CR_1000T_MS_VALUE) ?
  713. e1000_ms_force_master :
  714. e1000_ms_force_slave) :
  715. e1000_ms_auto;
  716. switch (phy->ms_type) {
  717. case e1000_ms_force_master:
  718. data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
  719. break;
  720. case e1000_ms_force_slave:
  721. data |= CR_1000T_MS_ENABLE;
  722. data &= ~(CR_1000T_MS_VALUE);
  723. break;
  724. case e1000_ms_auto:
  725. data &= ~CR_1000T_MS_ENABLE;
  726. default:
  727. break;
  728. }
  729. ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
  730. if (ret_val)
  731. goto out;
  732. }
  733. out:
  734. return ret_val;
  735. }
  736. /**
  737. * igb_copper_link_autoneg - Setup/Enable autoneg for copper link
  738. * @hw: pointer to the HW structure
  739. *
  740. * Performs initial bounds checking on autoneg advertisement parameter, then
  741. * configure to advertise the full capability. Setup the PHY to autoneg
  742. * and restart the negotiation process between the link partner. If
  743. * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
  744. **/
  745. static s32 igb_copper_link_autoneg(struct e1000_hw *hw)
  746. {
  747. struct e1000_phy_info *phy = &hw->phy;
  748. s32 ret_val;
  749. u16 phy_ctrl;
  750. /* Perform some bounds checking on the autoneg advertisement
  751. * parameter.
  752. */
  753. phy->autoneg_advertised &= phy->autoneg_mask;
  754. /* If autoneg_advertised is zero, we assume it was not defaulted
  755. * by the calling code so we set to advertise full capability.
  756. */
  757. if (phy->autoneg_advertised == 0)
  758. phy->autoneg_advertised = phy->autoneg_mask;
  759. hw_dbg("Reconfiguring auto-neg advertisement params\n");
  760. ret_val = igb_phy_setup_autoneg(hw);
  761. if (ret_val) {
  762. hw_dbg("Error Setting up Auto-Negotiation\n");
  763. goto out;
  764. }
  765. hw_dbg("Restarting Auto-Neg\n");
  766. /* Restart auto-negotiation by setting the Auto Neg Enable bit and
  767. * the Auto Neg Restart bit in the PHY control register.
  768. */
  769. ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
  770. if (ret_val)
  771. goto out;
  772. phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
  773. ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
  774. if (ret_val)
  775. goto out;
  776. /* Does the user want to wait for Auto-Neg to complete here, or
  777. * check at a later time (for example, callback routine).
  778. */
  779. if (phy->autoneg_wait_to_complete) {
  780. ret_val = igb_wait_autoneg(hw);
  781. if (ret_val) {
  782. hw_dbg("Error while waiting for autoneg to complete\n");
  783. goto out;
  784. }
  785. }
  786. hw->mac.get_link_status = true;
  787. out:
  788. return ret_val;
  789. }
  790. /**
  791. * igb_phy_setup_autoneg - Configure PHY for auto-negotiation
  792. * @hw: pointer to the HW structure
  793. *
  794. * Reads the MII auto-neg advertisement register and/or the 1000T control
  795. * register and if the PHY is already setup for auto-negotiation, then
  796. * return successful. Otherwise, setup advertisement and flow control to
  797. * the appropriate values for the wanted auto-negotiation.
  798. **/
  799. static s32 igb_phy_setup_autoneg(struct e1000_hw *hw)
  800. {
  801. struct e1000_phy_info *phy = &hw->phy;
  802. s32 ret_val;
  803. u16 mii_autoneg_adv_reg;
  804. u16 mii_1000t_ctrl_reg = 0;
  805. phy->autoneg_advertised &= phy->autoneg_mask;
  806. /* Read the MII Auto-Neg Advertisement Register (Address 4). */
  807. ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
  808. if (ret_val)
  809. goto out;
  810. if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
  811. /* Read the MII 1000Base-T Control Register (Address 9). */
  812. ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
  813. &mii_1000t_ctrl_reg);
  814. if (ret_val)
  815. goto out;
  816. }
  817. /* Need to parse both autoneg_advertised and fc and set up
  818. * the appropriate PHY registers. First we will parse for
  819. * autoneg_advertised software override. Since we can advertise
  820. * a plethora of combinations, we need to check each bit
  821. * individually.
  822. */
  823. /* First we clear all the 10/100 mb speed bits in the Auto-Neg
  824. * Advertisement Register (Address 4) and the 1000 mb speed bits in
  825. * the 1000Base-T Control Register (Address 9).
  826. */
  827. mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
  828. NWAY_AR_100TX_HD_CAPS |
  829. NWAY_AR_10T_FD_CAPS |
  830. NWAY_AR_10T_HD_CAPS);
  831. mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
  832. hw_dbg("autoneg_advertised %x\n", phy->autoneg_advertised);
  833. /* Do we want to advertise 10 Mb Half Duplex? */
  834. if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
  835. hw_dbg("Advertise 10mb Half duplex\n");
  836. mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
  837. }
  838. /* Do we want to advertise 10 Mb Full Duplex? */
  839. if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
  840. hw_dbg("Advertise 10mb Full duplex\n");
  841. mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
  842. }
  843. /* Do we want to advertise 100 Mb Half Duplex? */
  844. if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
  845. hw_dbg("Advertise 100mb Half duplex\n");
  846. mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
  847. }
  848. /* Do we want to advertise 100 Mb Full Duplex? */
  849. if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
  850. hw_dbg("Advertise 100mb Full duplex\n");
  851. mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
  852. }
  853. /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
  854. if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
  855. hw_dbg("Advertise 1000mb Half duplex request denied!\n");
  856. /* Do we want to advertise 1000 Mb Full Duplex? */
  857. if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
  858. hw_dbg("Advertise 1000mb Full duplex\n");
  859. mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
  860. }
  861. /* Check for a software override of the flow control settings, and
  862. * setup the PHY advertisement registers accordingly. If
  863. * auto-negotiation is enabled, then software will have to set the
  864. * "PAUSE" bits to the correct value in the Auto-Negotiation
  865. * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
  866. * negotiation.
  867. *
  868. * The possible values of the "fc" parameter are:
  869. * 0: Flow control is completely disabled
  870. * 1: Rx flow control is enabled (we can receive pause frames
  871. * but not send pause frames).
  872. * 2: Tx flow control is enabled (we can send pause frames
  873. * but we do not support receiving pause frames).
  874. * 3: Both Rx and TX flow control (symmetric) are enabled.
  875. * other: No software override. The flow control configuration
  876. * in the EEPROM is used.
  877. */
  878. switch (hw->fc.current_mode) {
  879. case e1000_fc_none:
  880. /* Flow control (RX & TX) is completely disabled by a
  881. * software over-ride.
  882. */
  883. mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
  884. break;
  885. case e1000_fc_rx_pause:
  886. /* RX Flow control is enabled, and TX Flow control is
  887. * disabled, by a software over-ride.
  888. *
  889. * Since there really isn't a way to advertise that we are
  890. * capable of RX Pause ONLY, we will advertise that we
  891. * support both symmetric and asymmetric RX PAUSE. Later
  892. * (in e1000_config_fc_after_link_up) we will disable the
  893. * hw's ability to send PAUSE frames.
  894. */
  895. mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
  896. break;
  897. case e1000_fc_tx_pause:
  898. /* TX Flow control is enabled, and RX Flow control is
  899. * disabled, by a software over-ride.
  900. */
  901. mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
  902. mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
  903. break;
  904. case e1000_fc_full:
  905. /* Flow control (both RX and TX) is enabled by a software
  906. * over-ride.
  907. */
  908. mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
  909. break;
  910. default:
  911. hw_dbg("Flow control param set incorrectly\n");
  912. ret_val = -E1000_ERR_CONFIG;
  913. goto out;
  914. }
  915. ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
  916. if (ret_val)
  917. goto out;
  918. hw_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
  919. if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
  920. ret_val = phy->ops.write_reg(hw,
  921. PHY_1000T_CTRL,
  922. mii_1000t_ctrl_reg);
  923. if (ret_val)
  924. goto out;
  925. }
  926. out:
  927. return ret_val;
  928. }
  929. /**
  930. * igb_setup_copper_link - Configure copper link settings
  931. * @hw: pointer to the HW structure
  932. *
  933. * Calls the appropriate function to configure the link for auto-neg or forced
  934. * speed and duplex. Then we check for link, once link is established calls
  935. * to configure collision distance and flow control are called. If link is
  936. * not established, we return -E1000_ERR_PHY (-2).
  937. **/
  938. s32 igb_setup_copper_link(struct e1000_hw *hw)
  939. {
  940. s32 ret_val;
  941. bool link;
  942. if (hw->mac.autoneg) {
  943. /* Setup autoneg and flow control advertisement and perform
  944. * autonegotiation.
  945. */
  946. ret_val = igb_copper_link_autoneg(hw);
  947. if (ret_val)
  948. goto out;
  949. } else {
  950. /* PHY will be set to 10H, 10F, 100H or 100F
  951. * depending on user settings.
  952. */
  953. hw_dbg("Forcing Speed and Duplex\n");
  954. ret_val = hw->phy.ops.force_speed_duplex(hw);
  955. if (ret_val) {
  956. hw_dbg("Error Forcing Speed and Duplex\n");
  957. goto out;
  958. }
  959. }
  960. /* Check link status. Wait up to 100 microseconds for link to become
  961. * valid.
  962. */
  963. ret_val = igb_phy_has_link(hw, COPPER_LINK_UP_LIMIT, 10, &link);
  964. if (ret_val)
  965. goto out;
  966. if (link) {
  967. hw_dbg("Valid link established!!!\n");
  968. igb_config_collision_dist(hw);
  969. ret_val = igb_config_fc_after_link_up(hw);
  970. } else {
  971. hw_dbg("Unable to establish link!!!\n");
  972. }
  973. out:
  974. return ret_val;
  975. }
  976. /**
  977. * igb_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
  978. * @hw: pointer to the HW structure
  979. *
  980. * Calls the PHY setup function to force speed and duplex. Clears the
  981. * auto-crossover to force MDI manually. Waits for link and returns
  982. * successful if link up is successful, else -E1000_ERR_PHY (-2).
  983. **/
  984. s32 igb_phy_force_speed_duplex_igp(struct e1000_hw *hw)
  985. {
  986. struct e1000_phy_info *phy = &hw->phy;
  987. s32 ret_val;
  988. u16 phy_data;
  989. bool link;
  990. ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
  991. if (ret_val)
  992. goto out;
  993. igb_phy_force_speed_duplex_setup(hw, &phy_data);
  994. ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
  995. if (ret_val)
  996. goto out;
  997. /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
  998. * forced whenever speed and duplex are forced.
  999. */
  1000. ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
  1001. if (ret_val)
  1002. goto out;
  1003. phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
  1004. phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
  1005. ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
  1006. if (ret_val)
  1007. goto out;
  1008. hw_dbg("IGP PSCR: %X\n", phy_data);
  1009. udelay(1);
  1010. if (phy->autoneg_wait_to_complete) {
  1011. hw_dbg("Waiting for forced speed/duplex link on IGP phy.\n");
  1012. ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 10000, &link);
  1013. if (ret_val)
  1014. goto out;
  1015. if (!link)
  1016. hw_dbg("Link taking longer than expected.\n");
  1017. /* Try once more */
  1018. ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 10000, &link);
  1019. if (ret_val)
  1020. goto out;
  1021. }
  1022. out:
  1023. return ret_val;
  1024. }
  1025. /**
  1026. * igb_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
  1027. * @hw: pointer to the HW structure
  1028. *
  1029. * Calls the PHY setup function to force speed and duplex. Clears the
  1030. * auto-crossover to force MDI manually. Resets the PHY to commit the
  1031. * changes. If time expires while waiting for link up, we reset the DSP.
  1032. * After reset, TX_CLK and CRS on TX must be set. Return successful upon
  1033. * successful completion, else return corresponding error code.
  1034. **/
  1035. s32 igb_phy_force_speed_duplex_m88(struct e1000_hw *hw)
  1036. {
  1037. struct e1000_phy_info *phy = &hw->phy;
  1038. s32 ret_val;
  1039. u16 phy_data;
  1040. bool link;
  1041. /* I210 and I211 devices support Auto-Crossover in forced operation. */
  1042. if (phy->type != e1000_phy_i210) {
  1043. /* Clear Auto-Crossover to force MDI manually. M88E1000
  1044. * requires MDI forced whenever speed and duplex are forced.
  1045. */
  1046. ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL,
  1047. &phy_data);
  1048. if (ret_val)
  1049. goto out;
  1050. phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
  1051. ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
  1052. phy_data);
  1053. if (ret_val)
  1054. goto out;
  1055. hw_dbg("M88E1000 PSCR: %X\n", phy_data);
  1056. }
  1057. ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
  1058. if (ret_val)
  1059. goto out;
  1060. igb_phy_force_speed_duplex_setup(hw, &phy_data);
  1061. ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
  1062. if (ret_val)
  1063. goto out;
  1064. /* Reset the phy to commit changes. */
  1065. ret_val = igb_phy_sw_reset(hw);
  1066. if (ret_val)
  1067. goto out;
  1068. if (phy->autoneg_wait_to_complete) {
  1069. hw_dbg("Waiting for forced speed/duplex link on M88 phy.\n");
  1070. ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link);
  1071. if (ret_val)
  1072. goto out;
  1073. if (!link) {
  1074. bool reset_dsp = true;
  1075. switch (hw->phy.id) {
  1076. case I347AT4_E_PHY_ID:
  1077. case M88E1112_E_PHY_ID:
  1078. case M88E1543_E_PHY_ID:
  1079. case M88E1512_E_PHY_ID:
  1080. case I210_I_PHY_ID:
  1081. reset_dsp = false;
  1082. break;
  1083. default:
  1084. if (hw->phy.type != e1000_phy_m88)
  1085. reset_dsp = false;
  1086. break;
  1087. }
  1088. if (!reset_dsp) {
  1089. hw_dbg("Link taking longer than expected.\n");
  1090. } else {
  1091. /* We didn't get link.
  1092. * Reset the DSP and cross our fingers.
  1093. */
  1094. ret_val = phy->ops.write_reg(hw,
  1095. M88E1000_PHY_PAGE_SELECT,
  1096. 0x001d);
  1097. if (ret_val)
  1098. goto out;
  1099. ret_val = igb_phy_reset_dsp(hw);
  1100. if (ret_val)
  1101. goto out;
  1102. }
  1103. }
  1104. /* Try once more */
  1105. ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT,
  1106. 100000, &link);
  1107. if (ret_val)
  1108. goto out;
  1109. }
  1110. if (hw->phy.type != e1000_phy_m88 ||
  1111. hw->phy.id == I347AT4_E_PHY_ID ||
  1112. hw->phy.id == M88E1112_E_PHY_ID ||
  1113. hw->phy.id == M88E1543_E_PHY_ID ||
  1114. hw->phy.id == M88E1512_E_PHY_ID ||
  1115. hw->phy.id == I210_I_PHY_ID)
  1116. goto out;
  1117. ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
  1118. if (ret_val)
  1119. goto out;
  1120. /* Resetting the phy means we need to re-force TX_CLK in the
  1121. * Extended PHY Specific Control Register to 25MHz clock from
  1122. * the reset value of 2.5MHz.
  1123. */
  1124. phy_data |= M88E1000_EPSCR_TX_CLK_25;
  1125. ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
  1126. if (ret_val)
  1127. goto out;
  1128. /* In addition, we must re-enable CRS on Tx for both half and full
  1129. * duplex.
  1130. */
  1131. ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
  1132. if (ret_val)
  1133. goto out;
  1134. phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
  1135. ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
  1136. out:
  1137. return ret_val;
  1138. }
  1139. /**
  1140. * igb_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
  1141. * @hw: pointer to the HW structure
  1142. * @phy_ctrl: pointer to current value of PHY_CONTROL
  1143. *
  1144. * Forces speed and duplex on the PHY by doing the following: disable flow
  1145. * control, force speed/duplex on the MAC, disable auto speed detection,
  1146. * disable auto-negotiation, configure duplex, configure speed, configure
  1147. * the collision distance, write configuration to CTRL register. The
  1148. * caller must write to the PHY_CONTROL register for these settings to
  1149. * take affect.
  1150. **/
  1151. static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw,
  1152. u16 *phy_ctrl)
  1153. {
  1154. struct e1000_mac_info *mac = &hw->mac;
  1155. u32 ctrl;
  1156. /* Turn off flow control when forcing speed/duplex */
  1157. hw->fc.current_mode = e1000_fc_none;
  1158. /* Force speed/duplex on the mac */
  1159. ctrl = rd32(E1000_CTRL);
  1160. ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
  1161. ctrl &= ~E1000_CTRL_SPD_SEL;
  1162. /* Disable Auto Speed Detection */
  1163. ctrl &= ~E1000_CTRL_ASDE;
  1164. /* Disable autoneg on the phy */
  1165. *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
  1166. /* Forcing Full or Half Duplex? */
  1167. if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
  1168. ctrl &= ~E1000_CTRL_FD;
  1169. *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
  1170. hw_dbg("Half Duplex\n");
  1171. } else {
  1172. ctrl |= E1000_CTRL_FD;
  1173. *phy_ctrl |= MII_CR_FULL_DUPLEX;
  1174. hw_dbg("Full Duplex\n");
  1175. }
  1176. /* Forcing 10mb or 100mb? */
  1177. if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
  1178. ctrl |= E1000_CTRL_SPD_100;
  1179. *phy_ctrl |= MII_CR_SPEED_100;
  1180. *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
  1181. hw_dbg("Forcing 100mb\n");
  1182. } else {
  1183. ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
  1184. *phy_ctrl |= MII_CR_SPEED_10;
  1185. *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
  1186. hw_dbg("Forcing 10mb\n");
  1187. }
  1188. igb_config_collision_dist(hw);
  1189. wr32(E1000_CTRL, ctrl);
  1190. }
  1191. /**
  1192. * igb_set_d3_lplu_state - Sets low power link up state for D3
  1193. * @hw: pointer to the HW structure
  1194. * @active: boolean used to enable/disable lplu
  1195. *
  1196. * Success returns 0, Failure returns 1
  1197. *
  1198. * The low power link up (lplu) state is set to the power management level D3
  1199. * and SmartSpeed is disabled when active is true, else clear lplu for D3
  1200. * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
  1201. * is used during Dx states where the power conservation is most important.
  1202. * During driver activity, SmartSpeed should be enabled so performance is
  1203. * maintained.
  1204. **/
  1205. s32 igb_set_d3_lplu_state(struct e1000_hw *hw, bool active)
  1206. {
  1207. struct e1000_phy_info *phy = &hw->phy;
  1208. s32 ret_val = 0;
  1209. u16 data;
  1210. if (!(hw->phy.ops.read_reg))
  1211. goto out;
  1212. ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
  1213. if (ret_val)
  1214. goto out;
  1215. if (!active) {
  1216. data &= ~IGP02E1000_PM_D3_LPLU;
  1217. ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
  1218. data);
  1219. if (ret_val)
  1220. goto out;
  1221. /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
  1222. * during Dx states where the power conservation is most
  1223. * important. During driver activity we should enable
  1224. * SmartSpeed, so performance is maintained.
  1225. */
  1226. if (phy->smart_speed == e1000_smart_speed_on) {
  1227. ret_val = phy->ops.read_reg(hw,
  1228. IGP01E1000_PHY_PORT_CONFIG,
  1229. &data);
  1230. if (ret_val)
  1231. goto out;
  1232. data |= IGP01E1000_PSCFR_SMART_SPEED;
  1233. ret_val = phy->ops.write_reg(hw,
  1234. IGP01E1000_PHY_PORT_CONFIG,
  1235. data);
  1236. if (ret_val)
  1237. goto out;
  1238. } else if (phy->smart_speed == e1000_smart_speed_off) {
  1239. ret_val = phy->ops.read_reg(hw,
  1240. IGP01E1000_PHY_PORT_CONFIG,
  1241. &data);
  1242. if (ret_val)
  1243. goto out;
  1244. data &= ~IGP01E1000_PSCFR_SMART_SPEED;
  1245. ret_val = phy->ops.write_reg(hw,
  1246. IGP01E1000_PHY_PORT_CONFIG,
  1247. data);
  1248. if (ret_val)
  1249. goto out;
  1250. }
  1251. } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
  1252. (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
  1253. (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
  1254. data |= IGP02E1000_PM_D3_LPLU;
  1255. ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
  1256. data);
  1257. if (ret_val)
  1258. goto out;
  1259. /* When LPLU is enabled, we should disable SmartSpeed */
  1260. ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
  1261. &data);
  1262. if (ret_val)
  1263. goto out;
  1264. data &= ~IGP01E1000_PSCFR_SMART_SPEED;
  1265. ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
  1266. data);
  1267. }
  1268. out:
  1269. return ret_val;
  1270. }
  1271. /**
  1272. * igb_check_downshift - Checks whether a downshift in speed occurred
  1273. * @hw: pointer to the HW structure
  1274. *
  1275. * Success returns 0, Failure returns 1
  1276. *
  1277. * A downshift is detected by querying the PHY link health.
  1278. **/
  1279. s32 igb_check_downshift(struct e1000_hw *hw)
  1280. {
  1281. struct e1000_phy_info *phy = &hw->phy;
  1282. s32 ret_val;
  1283. u16 phy_data, offset, mask;
  1284. switch (phy->type) {
  1285. case e1000_phy_i210:
  1286. case e1000_phy_m88:
  1287. case e1000_phy_gg82563:
  1288. offset = M88E1000_PHY_SPEC_STATUS;
  1289. mask = M88E1000_PSSR_DOWNSHIFT;
  1290. break;
  1291. case e1000_phy_igp_2:
  1292. case e1000_phy_igp:
  1293. case e1000_phy_igp_3:
  1294. offset = IGP01E1000_PHY_LINK_HEALTH;
  1295. mask = IGP01E1000_PLHR_SS_DOWNGRADE;
  1296. break;
  1297. default:
  1298. /* speed downshift not supported */
  1299. phy->speed_downgraded = false;
  1300. ret_val = 0;
  1301. goto out;
  1302. }
  1303. ret_val = phy->ops.read_reg(hw, offset, &phy_data);
  1304. if (!ret_val)
  1305. phy->speed_downgraded = (phy_data & mask) ? true : false;
  1306. out:
  1307. return ret_val;
  1308. }
  1309. /**
  1310. * igb_check_polarity_m88 - Checks the polarity.
  1311. * @hw: pointer to the HW structure
  1312. *
  1313. * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
  1314. *
  1315. * Polarity is determined based on the PHY specific status register.
  1316. **/
  1317. s32 igb_check_polarity_m88(struct e1000_hw *hw)
  1318. {
  1319. struct e1000_phy_info *phy = &hw->phy;
  1320. s32 ret_val;
  1321. u16 data;
  1322. ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);
  1323. if (!ret_val)
  1324. phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
  1325. ? e1000_rev_polarity_reversed
  1326. : e1000_rev_polarity_normal;
  1327. return ret_val;
  1328. }
  1329. /**
  1330. * igb_check_polarity_igp - Checks the polarity.
  1331. * @hw: pointer to the HW structure
  1332. *
  1333. * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
  1334. *
  1335. * Polarity is determined based on the PHY port status register, and the
  1336. * current speed (since there is no polarity at 100Mbps).
  1337. **/
  1338. static s32 igb_check_polarity_igp(struct e1000_hw *hw)
  1339. {
  1340. struct e1000_phy_info *phy = &hw->phy;
  1341. s32 ret_val;
  1342. u16 data, offset, mask;
  1343. /* Polarity is determined based on the speed of
  1344. * our connection.
  1345. */
  1346. ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
  1347. if (ret_val)
  1348. goto out;
  1349. if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
  1350. IGP01E1000_PSSR_SPEED_1000MBPS) {
  1351. offset = IGP01E1000_PHY_PCS_INIT_REG;
  1352. mask = IGP01E1000_PHY_POLARITY_MASK;
  1353. } else {
  1354. /* This really only applies to 10Mbps since
  1355. * there is no polarity for 100Mbps (always 0).
  1356. */
  1357. offset = IGP01E1000_PHY_PORT_STATUS;
  1358. mask = IGP01E1000_PSSR_POLARITY_REVERSED;
  1359. }
  1360. ret_val = phy->ops.read_reg(hw, offset, &data);
  1361. if (!ret_val)
  1362. phy->cable_polarity = (data & mask)
  1363. ? e1000_rev_polarity_reversed
  1364. : e1000_rev_polarity_normal;
  1365. out:
  1366. return ret_val;
  1367. }
  1368. /**
  1369. * igb_wait_autoneg - Wait for auto-neg completion
  1370. * @hw: pointer to the HW structure
  1371. *
  1372. * Waits for auto-negotiation to complete or for the auto-negotiation time
  1373. * limit to expire, which ever happens first.
  1374. **/
  1375. static s32 igb_wait_autoneg(struct e1000_hw *hw)
  1376. {
  1377. s32 ret_val = 0;
  1378. u16 i, phy_status;
  1379. /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
  1380. for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
  1381. ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
  1382. if (ret_val)
  1383. break;
  1384. ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
  1385. if (ret_val)
  1386. break;
  1387. if (phy_status & MII_SR_AUTONEG_COMPLETE)
  1388. break;
  1389. msleep(100);
  1390. }
  1391. /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
  1392. * has completed.
  1393. */
  1394. return ret_val;
  1395. }
  1396. /**
  1397. * igb_phy_has_link - Polls PHY for link
  1398. * @hw: pointer to the HW structure
  1399. * @iterations: number of times to poll for link
  1400. * @usec_interval: delay between polling attempts
  1401. * @success: pointer to whether polling was successful or not
  1402. *
  1403. * Polls the PHY status register for link, 'iterations' number of times.
  1404. **/
  1405. s32 igb_phy_has_link(struct e1000_hw *hw, u32 iterations,
  1406. u32 usec_interval, bool *success)
  1407. {
  1408. s32 ret_val = 0;
  1409. u16 i, phy_status;
  1410. for (i = 0; i < iterations; i++) {
  1411. /* Some PHYs require the PHY_STATUS register to be read
  1412. * twice due to the link bit being sticky. No harm doing
  1413. * it across the board.
  1414. */
  1415. ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
  1416. if (ret_val && usec_interval > 0) {
  1417. /* If the first read fails, another entity may have
  1418. * ownership of the resources, wait and try again to
  1419. * see if they have relinquished the resources yet.
  1420. */
  1421. if (usec_interval >= 1000)
  1422. mdelay(usec_interval/1000);
  1423. else
  1424. udelay(usec_interval);
  1425. }
  1426. ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
  1427. if (ret_val)
  1428. break;
  1429. if (phy_status & MII_SR_LINK_STATUS)
  1430. break;
  1431. if (usec_interval >= 1000)
  1432. mdelay(usec_interval/1000);
  1433. else
  1434. udelay(usec_interval);
  1435. }
  1436. *success = (i < iterations) ? true : false;
  1437. return ret_val;
  1438. }
  1439. /**
  1440. * igb_get_cable_length_m88 - Determine cable length for m88 PHY
  1441. * @hw: pointer to the HW structure
  1442. *
  1443. * Reads the PHY specific status register to retrieve the cable length
  1444. * information. The cable length is determined by averaging the minimum and
  1445. * maximum values to get the "average" cable length. The m88 PHY has four
  1446. * possible cable length values, which are:
  1447. * Register Value Cable Length
  1448. * 0 < 50 meters
  1449. * 1 50 - 80 meters
  1450. * 2 80 - 110 meters
  1451. * 3 110 - 140 meters
  1452. * 4 > 140 meters
  1453. **/
  1454. s32 igb_get_cable_length_m88(struct e1000_hw *hw)
  1455. {
  1456. struct e1000_phy_info *phy = &hw->phy;
  1457. s32 ret_val;
  1458. u16 phy_data, index;
  1459. ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
  1460. if (ret_val)
  1461. goto out;
  1462. index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
  1463. M88E1000_PSSR_CABLE_LENGTH_SHIFT;
  1464. if (index >= ARRAY_SIZE(e1000_m88_cable_length_table) - 1) {
  1465. ret_val = -E1000_ERR_PHY;
  1466. goto out;
  1467. }
  1468. phy->min_cable_length = e1000_m88_cable_length_table[index];
  1469. phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
  1470. phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
  1471. out:
  1472. return ret_val;
  1473. }
  1474. s32 igb_get_cable_length_m88_gen2(struct e1000_hw *hw)
  1475. {
  1476. struct e1000_phy_info *phy = &hw->phy;
  1477. s32 ret_val;
  1478. u16 phy_data, phy_data2, index, default_page, is_cm;
  1479. int len_tot = 0;
  1480. u16 len_min;
  1481. u16 len_max;
  1482. switch (hw->phy.id) {
  1483. case M88E1543_E_PHY_ID:
  1484. case M88E1512_E_PHY_ID:
  1485. case I347AT4_E_PHY_ID:
  1486. case I210_I_PHY_ID:
  1487. /* Remember the original page select and set it to 7 */
  1488. ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
  1489. &default_page);
  1490. if (ret_val)
  1491. goto out;
  1492. ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07);
  1493. if (ret_val)
  1494. goto out;
  1495. /* Check if the unit of cable length is meters or cm */
  1496. ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2);
  1497. if (ret_val)
  1498. goto out;
  1499. is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
  1500. /* Get cable length from Pair 0 length Regs */
  1501. ret_val = phy->ops.read_reg(hw, I347AT4_PCDL0, &phy_data);
  1502. if (ret_val)
  1503. goto out;
  1504. phy->pair_length[0] = phy_data / (is_cm ? 100 : 1);
  1505. len_tot = phy->pair_length[0];
  1506. len_min = phy->pair_length[0];
  1507. len_max = phy->pair_length[0];
  1508. /* Get cable length from Pair 1 length Regs */
  1509. ret_val = phy->ops.read_reg(hw, I347AT4_PCDL1, &phy_data);
  1510. if (ret_val)
  1511. goto out;
  1512. phy->pair_length[1] = phy_data / (is_cm ? 100 : 1);
  1513. len_tot += phy->pair_length[1];
  1514. len_min = min(len_min, phy->pair_length[1]);
  1515. len_max = max(len_max, phy->pair_length[1]);
  1516. /* Get cable length from Pair 2 length Regs */
  1517. ret_val = phy->ops.read_reg(hw, I347AT4_PCDL2, &phy_data);
  1518. if (ret_val)
  1519. goto out;
  1520. phy->pair_length[2] = phy_data / (is_cm ? 100 : 1);
  1521. len_tot += phy->pair_length[2];
  1522. len_min = min(len_min, phy->pair_length[2]);
  1523. len_max = max(len_max, phy->pair_length[2]);
  1524. /* Get cable length from Pair 3 length Regs */
  1525. ret_val = phy->ops.read_reg(hw, I347AT4_PCDL3, &phy_data);
  1526. if (ret_val)
  1527. goto out;
  1528. phy->pair_length[3] = phy_data / (is_cm ? 100 : 1);
  1529. len_tot += phy->pair_length[3];
  1530. len_min = min(len_min, phy->pair_length[3]);
  1531. len_max = max(len_max, phy->pair_length[3]);
  1532. /* Populate the phy structure with cable length in meters */
  1533. phy->min_cable_length = len_min;
  1534. phy->max_cable_length = len_max;
  1535. phy->cable_length = len_tot / 4;
  1536. /* Reset the page selec to its original value */
  1537. ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
  1538. default_page);
  1539. if (ret_val)
  1540. goto out;
  1541. break;
  1542. case M88E1112_E_PHY_ID:
  1543. /* Remember the original page select and set it to 5 */
  1544. ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
  1545. &default_page);
  1546. if (ret_val)
  1547. goto out;
  1548. ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05);
  1549. if (ret_val)
  1550. goto out;
  1551. ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE,
  1552. &phy_data);
  1553. if (ret_val)
  1554. goto out;
  1555. index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
  1556. M88E1000_PSSR_CABLE_LENGTH_SHIFT;
  1557. if (index >= ARRAY_SIZE(e1000_m88_cable_length_table) - 1) {
  1558. ret_val = -E1000_ERR_PHY;
  1559. goto out;
  1560. }
  1561. phy->min_cable_length = e1000_m88_cable_length_table[index];
  1562. phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
  1563. phy->cable_length = (phy->min_cable_length +
  1564. phy->max_cable_length) / 2;
  1565. /* Reset the page select to its original value */
  1566. ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
  1567. default_page);
  1568. if (ret_val)
  1569. goto out;
  1570. break;
  1571. default:
  1572. ret_val = -E1000_ERR_PHY;
  1573. goto out;
  1574. }
  1575. out:
  1576. return ret_val;
  1577. }
  1578. /**
  1579. * igb_get_cable_length_igp_2 - Determine cable length for igp2 PHY
  1580. * @hw: pointer to the HW structure
  1581. *
  1582. * The automatic gain control (agc) normalizes the amplitude of the
  1583. * received signal, adjusting for the attenuation produced by the
  1584. * cable. By reading the AGC registers, which represent the
  1585. * combination of coarse and fine gain value, the value can be put
  1586. * into a lookup table to obtain the approximate cable length
  1587. * for each channel.
  1588. **/
  1589. s32 igb_get_cable_length_igp_2(struct e1000_hw *hw)
  1590. {
  1591. struct e1000_phy_info *phy = &hw->phy;
  1592. s32 ret_val = 0;
  1593. u16 phy_data, i, agc_value = 0;
  1594. u16 cur_agc_index, max_agc_index = 0;
  1595. u16 min_agc_index = ARRAY_SIZE(e1000_igp_2_cable_length_table) - 1;
  1596. static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
  1597. IGP02E1000_PHY_AGC_A,
  1598. IGP02E1000_PHY_AGC_B,
  1599. IGP02E1000_PHY_AGC_C,
  1600. IGP02E1000_PHY_AGC_D
  1601. };
  1602. /* Read the AGC registers for all channels */
  1603. for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
  1604. ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);
  1605. if (ret_val)
  1606. goto out;
  1607. /* Getting bits 15:9, which represent the combination of
  1608. * coarse and fine gain values. The result is a number
  1609. * that can be put into the lookup table to obtain the
  1610. * approximate cable length.
  1611. */
  1612. cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
  1613. IGP02E1000_AGC_LENGTH_MASK;
  1614. /* Array index bound check. */
  1615. if ((cur_agc_index >= ARRAY_SIZE(e1000_igp_2_cable_length_table)) ||
  1616. (cur_agc_index ==