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/drivers/net/ethernet/intel/igb/igb.h

http://github.com/mirrors/linux
C Header | 736 lines | 552 code | 116 blank | 68 comment | 15 complexity | 763bea733a9b63fe234fc618ac25a4c4 MD5 | raw file
  1/* SPDX-License-Identifier: GPL-2.0 */
  2/* Copyright(c) 2007 - 2018 Intel Corporation. */
  3
  4/* Linux PRO/1000 Ethernet Driver main header file */
  5
  6#ifndef _IGB_H_
  7#define _IGB_H_
  8
  9#include "e1000_mac.h"
 10#include "e1000_82575.h"
 11
 12#include <linux/timecounter.h>
 13#include <linux/net_tstamp.h>
 14#include <linux/ptp_clock_kernel.h>
 15#include <linux/bitops.h>
 16#include <linux/if_vlan.h>
 17#include <linux/i2c.h>
 18#include <linux/i2c-algo-bit.h>
 19#include <linux/pci.h>
 20#include <linux/mdio.h>
 21
 22struct igb_adapter;
 23
 24#define E1000_PCS_CFG_IGN_SD	1
 25
 26/* Interrupt defines */
 27#define IGB_START_ITR		648 /* ~6000 ints/sec */
 28#define IGB_4K_ITR		980
 29#define IGB_20K_ITR		196
 30#define IGB_70K_ITR		56
 31
 32/* TX/RX descriptor defines */
 33#define IGB_DEFAULT_TXD		256
 34#define IGB_DEFAULT_TX_WORK	128
 35#define IGB_MIN_TXD		80
 36#define IGB_MAX_TXD		4096
 37
 38#define IGB_DEFAULT_RXD		256
 39#define IGB_MIN_RXD		80
 40#define IGB_MAX_RXD		4096
 41
 42#define IGB_DEFAULT_ITR		3 /* dynamic */
 43#define IGB_MAX_ITR_USECS	10000
 44#define IGB_MIN_ITR_USECS	10
 45#define NON_Q_VECTORS		1
 46#define MAX_Q_VECTORS		8
 47#define MAX_MSIX_ENTRIES	10
 48
 49/* Transmit and receive queues */
 50#define IGB_MAX_RX_QUEUES	8
 51#define IGB_MAX_RX_QUEUES_82575	4
 52#define IGB_MAX_RX_QUEUES_I211	2
 53#define IGB_MAX_TX_QUEUES	8
 54#define IGB_MAX_VF_MC_ENTRIES	30
 55#define IGB_MAX_VF_FUNCTIONS	8
 56#define IGB_MAX_VFTA_ENTRIES	128
 57#define IGB_82576_VF_DEV_ID	0x10CA
 58#define IGB_I350_VF_DEV_ID	0x1520
 59
 60/* NVM version defines */
 61#define IGB_MAJOR_MASK		0xF000
 62#define IGB_MINOR_MASK		0x0FF0
 63#define IGB_BUILD_MASK		0x000F
 64#define IGB_COMB_VER_MASK	0x00FF
 65#define IGB_MAJOR_SHIFT		12
 66#define IGB_MINOR_SHIFT		4
 67#define IGB_COMB_VER_SHFT	8
 68#define IGB_NVM_VER_INVALID	0xFFFF
 69#define IGB_ETRACK_SHIFT	16
 70#define NVM_ETRACK_WORD		0x0042
 71#define NVM_COMB_VER_OFF	0x0083
 72#define NVM_COMB_VER_PTR	0x003d
 73
 74/* Transmit and receive latency (for PTP timestamps) */
 75#define IGB_I210_TX_LATENCY_10		9542
 76#define IGB_I210_TX_LATENCY_100		1024
 77#define IGB_I210_TX_LATENCY_1000	178
 78#define IGB_I210_RX_LATENCY_10		20662
 79#define IGB_I210_RX_LATENCY_100		2213
 80#define IGB_I210_RX_LATENCY_1000	448
 81
 82struct vf_data_storage {
 83	unsigned char vf_mac_addresses[ETH_ALEN];
 84	u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];
 85	u16 num_vf_mc_hashes;
 86	u32 flags;
 87	unsigned long last_nack;
 88	u16 pf_vlan; /* When set, guest VLAN config not allowed. */
 89	u16 pf_qos;
 90	u16 tx_rate;
 91	bool spoofchk_enabled;
 92	bool trusted;
 93};
 94
 95/* Number of unicast MAC filters reserved for the PF in the RAR registers */
 96#define IGB_PF_MAC_FILTERS_RESERVED	3
 97
 98struct vf_mac_filter {
 99	struct list_head l;
100	int vf;
101	bool free;
102	u8 vf_mac[ETH_ALEN];
103};
104
105#define IGB_VF_FLAG_CTS            0x00000001 /* VF is clear to send data */
106#define IGB_VF_FLAG_UNI_PROMISC    0x00000002 /* VF has unicast promisc */
107#define IGB_VF_FLAG_MULTI_PROMISC  0x00000004 /* VF has multicast promisc */
108#define IGB_VF_FLAG_PF_SET_MAC     0x00000008 /* PF has set MAC address */
109
110/* RX descriptor control thresholds.
111 * PTHRESH - MAC will consider prefetch if it has fewer than this number of
112 *           descriptors available in its onboard memory.
113 *           Setting this to 0 disables RX descriptor prefetch.
114 * HTHRESH - MAC will only prefetch if there are at least this many descriptors
115 *           available in host memory.
116 *           If PTHRESH is 0, this should also be 0.
117 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
118 *           descriptors until either it has this many to write back, or the
119 *           ITR timer expires.
120 */
121#define IGB_RX_PTHRESH	((hw->mac.type == e1000_i354) ? 12 : 8)
122#define IGB_RX_HTHRESH	8
123#define IGB_TX_PTHRESH	((hw->mac.type == e1000_i354) ? 20 : 8)
124#define IGB_TX_HTHRESH	1
125#define IGB_RX_WTHRESH	((hw->mac.type == e1000_82576 && \
126			  (adapter->flags & IGB_FLAG_HAS_MSIX)) ? 1 : 4)
127#define IGB_TX_WTHRESH	((hw->mac.type == e1000_82576 && \
128			  (adapter->flags & IGB_FLAG_HAS_MSIX)) ? 1 : 16)
129
130/* this is the size past which hardware will drop packets when setting LPE=0 */
131#define MAXIMUM_ETHERNET_VLAN_SIZE 1522
132
133/* Supported Rx Buffer Sizes */
134#define IGB_RXBUFFER_256	256
135#define IGB_RXBUFFER_2048	2048
136#define IGB_RXBUFFER_3072	3072
137#define IGB_RX_HDR_LEN		IGB_RXBUFFER_256
138#define IGB_TS_HDR_LEN		16
139
140#define IGB_SKB_PAD		(NET_SKB_PAD + NET_IP_ALIGN)
141#if (PAGE_SIZE < 8192)
142#define IGB_MAX_FRAME_BUILD_SKB \
143	(SKB_WITH_OVERHEAD(IGB_RXBUFFER_2048) - IGB_SKB_PAD - IGB_TS_HDR_LEN)
144#else
145#define IGB_MAX_FRAME_BUILD_SKB (IGB_RXBUFFER_2048 - IGB_TS_HDR_LEN)
146#endif
147
148/* How many Rx Buffers do we bundle into one write to the hardware ? */
149#define IGB_RX_BUFFER_WRITE	16 /* Must be power of 2 */
150
151#define IGB_RX_DMA_ATTR \
152	(DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
153
154#define AUTO_ALL_MODES		0
155#define IGB_EEPROM_APME		0x0400
156
157#ifndef IGB_MASTER_SLAVE
158/* Switch to override PHY master/slave setting */
159#define IGB_MASTER_SLAVE	e1000_ms_hw_default
160#endif
161
162#define IGB_MNG_VLAN_NONE	-1
163
164enum igb_tx_flags {
165	/* cmd_type flags */
166	IGB_TX_FLAGS_VLAN	= 0x01,
167	IGB_TX_FLAGS_TSO	= 0x02,
168	IGB_TX_FLAGS_TSTAMP	= 0x04,
169
170	/* olinfo flags */
171	IGB_TX_FLAGS_IPV4	= 0x10,
172	IGB_TX_FLAGS_CSUM	= 0x20,
173};
174
175/* VLAN info */
176#define IGB_TX_FLAGS_VLAN_MASK	0xffff0000
177#define IGB_TX_FLAGS_VLAN_SHIFT	16
178
179/* The largest size we can write to the descriptor is 65535.  In order to
180 * maintain a power of two alignment we have to limit ourselves to 32K.
181 */
182#define IGB_MAX_TXD_PWR	15
183#define IGB_MAX_DATA_PER_TXD	(1u << IGB_MAX_TXD_PWR)
184
185/* Tx Descriptors needed, worst case */
186#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGB_MAX_DATA_PER_TXD)
187#define DESC_NEEDED (MAX_SKB_FRAGS + 4)
188
189/* EEPROM byte offsets */
190#define IGB_SFF_8472_SWAP		0x5C
191#define IGB_SFF_8472_COMP		0x5E
192
193/* Bitmasks */
194#define IGB_SFF_ADDRESSING_MODE		0x4
195#define IGB_SFF_8472_UNSUP		0x00
196
197/* wrapper around a pointer to a socket buffer,
198 * so a DMA handle can be stored along with the buffer
199 */
200struct igb_tx_buffer {
201	union e1000_adv_tx_desc *next_to_watch;
202	unsigned long time_stamp;
203	struct sk_buff *skb;
204	unsigned int bytecount;
205	u16 gso_segs;
206	__be16 protocol;
207
208	DEFINE_DMA_UNMAP_ADDR(dma);
209	DEFINE_DMA_UNMAP_LEN(len);
210	u32 tx_flags;
211};
212
213struct igb_rx_buffer {
214	dma_addr_t dma;
215	struct page *page;
216#if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536)
217	__u32 page_offset;
218#else
219	__u16 page_offset;
220#endif
221	__u16 pagecnt_bias;
222};
223
224struct igb_tx_queue_stats {
225	u64 packets;
226	u64 bytes;
227	u64 restart_queue;
228	u64 restart_queue2;
229};
230
231struct igb_rx_queue_stats {
232	u64 packets;
233	u64 bytes;
234	u64 drops;
235	u64 csum_err;
236	u64 alloc_failed;
237};
238
239struct igb_ring_container {
240	struct igb_ring *ring;		/* pointer to linked list of rings */
241	unsigned int total_bytes;	/* total bytes processed this int */
242	unsigned int total_packets;	/* total packets processed this int */
243	u16 work_limit;			/* total work allowed per interrupt */
244	u8 count;			/* total number of rings in vector */
245	u8 itr;				/* current ITR setting for ring */
246};
247
248struct igb_ring {
249	struct igb_q_vector *q_vector;	/* backlink to q_vector */
250	struct net_device *netdev;	/* back pointer to net_device */
251	struct device *dev;		/* device pointer for dma mapping */
252	union {				/* array of buffer info structs */
253		struct igb_tx_buffer *tx_buffer_info;
254		struct igb_rx_buffer *rx_buffer_info;
255	};
256	void *desc;			/* descriptor ring memory */
257	unsigned long flags;		/* ring specific flags */
258	void __iomem *tail;		/* pointer to ring tail register */
259	dma_addr_t dma;			/* phys address of the ring */
260	unsigned int  size;		/* length of desc. ring in bytes */
261
262	u16 count;			/* number of desc. in the ring */
263	u8 queue_index;			/* logical index of the ring*/
264	u8 reg_idx;			/* physical index of the ring */
265	bool launchtime_enable;		/* true if LaunchTime is enabled */
266	bool cbs_enable;		/* indicates if CBS is enabled */
267	s32 idleslope;			/* idleSlope in kbps */
268	s32 sendslope;			/* sendSlope in kbps */
269	s32 hicredit;			/* hiCredit in bytes */
270	s32 locredit;			/* loCredit in bytes */
271
272	/* everything past this point are written often */
273	u16 next_to_clean;
274	u16 next_to_use;
275	u16 next_to_alloc;
276
277	union {
278		/* TX */
279		struct {
280			struct igb_tx_queue_stats tx_stats;
281			struct u64_stats_sync tx_syncp;
282			struct u64_stats_sync tx_syncp2;
283		};
284		/* RX */
285		struct {
286			struct sk_buff *skb;
287			struct igb_rx_queue_stats rx_stats;
288			struct u64_stats_sync rx_syncp;
289		};
290	};
291} ____cacheline_internodealigned_in_smp;
292
293struct igb_q_vector {
294	struct igb_adapter *adapter;	/* backlink */
295	int cpu;			/* CPU for DCA */
296	u32 eims_value;			/* EIMS mask value */
297
298	u16 itr_val;
299	u8 set_itr;
300	void __iomem *itr_register;
301
302	struct igb_ring_container rx, tx;
303
304	struct napi_struct napi;
305	struct rcu_head rcu;	/* to avoid race with update stats on free */
306	char name[IFNAMSIZ + 9];
307
308	/* for dynamic allocation of rings associated with this q_vector */
309	struct igb_ring ring[] ____cacheline_internodealigned_in_smp;
310};
311
312enum e1000_ring_flags_t {
313	IGB_RING_FLAG_RX_3K_BUFFER,
314	IGB_RING_FLAG_RX_BUILD_SKB_ENABLED,
315	IGB_RING_FLAG_RX_SCTP_CSUM,
316	IGB_RING_FLAG_RX_LB_VLAN_BSWAP,
317	IGB_RING_FLAG_TX_CTX_IDX,
318	IGB_RING_FLAG_TX_DETECT_HANG
319};
320
321#define ring_uses_large_buffer(ring) \
322	test_bit(IGB_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
323#define set_ring_uses_large_buffer(ring) \
324	set_bit(IGB_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
325#define clear_ring_uses_large_buffer(ring) \
326	clear_bit(IGB_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
327
328#define ring_uses_build_skb(ring) \
329	test_bit(IGB_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags)
330#define set_ring_build_skb_enabled(ring) \
331	set_bit(IGB_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags)
332#define clear_ring_build_skb_enabled(ring) \
333	clear_bit(IGB_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags)
334
335static inline unsigned int igb_rx_bufsz(struct igb_ring *ring)
336{
337#if (PAGE_SIZE < 8192)
338	if (ring_uses_large_buffer(ring))
339		return IGB_RXBUFFER_3072;
340
341	if (ring_uses_build_skb(ring))
342		return IGB_MAX_FRAME_BUILD_SKB + IGB_TS_HDR_LEN;
343#endif
344	return IGB_RXBUFFER_2048;
345}
346
347static inline unsigned int igb_rx_pg_order(struct igb_ring *ring)
348{
349#if (PAGE_SIZE < 8192)
350	if (ring_uses_large_buffer(ring))
351		return 1;
352#endif
353	return 0;
354}
355
356#define igb_rx_pg_size(_ring) (PAGE_SIZE << igb_rx_pg_order(_ring))
357
358#define IGB_TXD_DCMD (E1000_ADVTXD_DCMD_EOP | E1000_ADVTXD_DCMD_RS)
359
360#define IGB_RX_DESC(R, i)	\
361	(&(((union e1000_adv_rx_desc *)((R)->desc))[i]))
362#define IGB_TX_DESC(R, i)	\
363	(&(((union e1000_adv_tx_desc *)((R)->desc))[i]))
364#define IGB_TX_CTXTDESC(R, i)	\
365	(&(((struct e1000_adv_tx_context_desc *)((R)->desc))[i]))
366
367/* igb_test_staterr - tests bits within Rx descriptor status and error fields */
368static inline __le32 igb_test_staterr(union e1000_adv_rx_desc *rx_desc,
369				      const u32 stat_err_bits)
370{
371	return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
372}
373
374/* igb_desc_unused - calculate if we have unused descriptors */
375static inline int igb_desc_unused(struct igb_ring *ring)
376{
377	if (ring->next_to_clean > ring->next_to_use)
378		return ring->next_to_clean - ring->next_to_use - 1;
379
380	return ring->count + ring->next_to_clean - ring->next_to_use - 1;
381}
382
383#ifdef CONFIG_IGB_HWMON
384
385#define IGB_HWMON_TYPE_LOC	0
386#define IGB_HWMON_TYPE_TEMP	1
387#define IGB_HWMON_TYPE_CAUTION	2
388#define IGB_HWMON_TYPE_MAX	3
389
390struct hwmon_attr {
391	struct device_attribute dev_attr;
392	struct e1000_hw *hw;
393	struct e1000_thermal_diode_data *sensor;
394	char name[12];
395	};
396
397struct hwmon_buff {
398	struct attribute_group group;
399	const struct attribute_group *groups[2];
400	struct attribute *attrs[E1000_MAX_SENSORS * 4 + 1];
401	struct hwmon_attr hwmon_list[E1000_MAX_SENSORS * 4];
402	unsigned int n_hwmon;
403	};
404#endif
405
406/* The number of L2 ether-type filter registers, Index 3 is reserved
407 * for PTP 1588 timestamp
408 */
409#define MAX_ETYPE_FILTER	(4 - 1)
410/* ETQF filter list: one static filter per filter consumer. This is
411 * to avoid filter collisions later. Add new filters here!!
412 *
413 * Current filters:		Filter 3
414 */
415#define IGB_ETQF_FILTER_1588	3
416
417#define IGB_N_EXTTS	2
418#define IGB_N_PEROUT	2
419#define IGB_N_SDP	4
420#define IGB_RETA_SIZE	128
421
422enum igb_filter_match_flags {
423	IGB_FILTER_FLAG_ETHER_TYPE = 0x1,
424	IGB_FILTER_FLAG_VLAN_TCI   = 0x2,
425	IGB_FILTER_FLAG_SRC_MAC_ADDR   = 0x4,
426	IGB_FILTER_FLAG_DST_MAC_ADDR   = 0x8,
427};
428
429#define IGB_MAX_RXNFC_FILTERS 16
430
431/* RX network flow classification data structure */
432struct igb_nfc_input {
433	/* Byte layout in order, all values with MSB first:
434	 * match_flags - 1 byte
435	 * etype - 2 bytes
436	 * vlan_tci - 2 bytes
437	 */
438	u8 match_flags;
439	__be16 etype;
440	__be16 vlan_tci;
441	u8 src_addr[ETH_ALEN];
442	u8 dst_addr[ETH_ALEN];
443};
444
445struct igb_nfc_filter {
446	struct hlist_node nfc_node;
447	struct igb_nfc_input filter;
448	unsigned long cookie;
449	u16 etype_reg_index;
450	u16 sw_idx;
451	u16 action;
452};
453
454struct igb_mac_addr {
455	u8 addr[ETH_ALEN];
456	u8 queue;
457	u8 state; /* bitmask */
458};
459
460#define IGB_MAC_STATE_DEFAULT	0x1
461#define IGB_MAC_STATE_IN_USE	0x2
462#define IGB_MAC_STATE_SRC_ADDR	0x4
463#define IGB_MAC_STATE_QUEUE_STEERING 0x8
464
465/* board specific private data structure */
466struct igb_adapter {
467	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
468
469	struct net_device *netdev;
470
471	unsigned long state;
472	unsigned int flags;
473
474	unsigned int num_q_vectors;
475	struct msix_entry msix_entries[MAX_MSIX_ENTRIES];
476
477	/* Interrupt Throttle Rate */
478	u32 rx_itr_setting;
479	u32 tx_itr_setting;
480	u16 tx_itr;
481	u16 rx_itr;
482
483	/* TX */
484	u16 tx_work_limit;
485	u32 tx_timeout_count;
486	int num_tx_queues;
487	struct igb_ring *tx_ring[16];
488
489	/* RX */
490	int num_rx_queues;
491	struct igb_ring *rx_ring[16];
492
493	u32 max_frame_size;
494	u32 min_frame_size;
495
496	struct timer_list watchdog_timer;
497	struct timer_list phy_info_timer;
498
499	u16 mng_vlan_id;
500	u32 bd_number;
501	u32 wol;
502	u32 en_mng_pt;
503	u16 link_speed;
504	u16 link_duplex;
505
506	u8 __iomem *io_addr; /* Mainly for iounmap use */
507
508	struct work_struct reset_task;
509	struct work_struct watchdog_task;
510	bool fc_autoneg;
511	u8  tx_timeout_factor;
512	struct timer_list blink_timer;
513	unsigned long led_status;
514
515	/* OS defined structs */
516	struct pci_dev *pdev;
517
518	spinlock_t stats64_lock;
519	struct rtnl_link_stats64 stats64;
520
521	/* structs defined in e1000_hw.h */
522	struct e1000_hw hw;
523	struct e1000_hw_stats stats;
524	struct e1000_phy_info phy_info;
525
526	u32 test_icr;
527	struct igb_ring test_tx_ring;
528	struct igb_ring test_rx_ring;
529
530	int msg_enable;
531
532	struct igb_q_vector *q_vector[MAX_Q_VECTORS];
533	u32 eims_enable_mask;
534	u32 eims_other;
535
536	/* to not mess up cache alignment, always add to the bottom */
537	u16 tx_ring_count;
538	u16 rx_ring_count;
539	unsigned int vfs_allocated_count;
540	struct vf_data_storage *vf_data;
541	int vf_rate_link_speed;
542	u32 rss_queues;
543	u32 wvbr;
544	u32 *shadow_vfta;
545
546	struct ptp_clock *ptp_clock;
547	struct ptp_clock_info ptp_caps;
548	struct delayed_work ptp_overflow_work;
549	struct work_struct ptp_tx_work;
550	struct sk_buff *ptp_tx_skb;
551	struct hwtstamp_config tstamp_config;
552	unsigned long ptp_tx_start;
553	unsigned long last_rx_ptp_check;
554	unsigned long last_rx_timestamp;
555	unsigned int ptp_flags;
556	spinlock_t tmreg_lock;
557	struct cyclecounter cc;
558	struct timecounter tc;
559	u32 tx_hwtstamp_timeouts;
560	u32 tx_hwtstamp_skipped;
561	u32 rx_hwtstamp_cleared;
562	bool pps_sys_wrap_on;
563
564	struct ptp_pin_desc sdp_config[IGB_N_SDP];
565	struct {
566		struct timespec64 start;
567		struct timespec64 period;
568	} perout[IGB_N_PEROUT];
569
570	char fw_version[32];
571#ifdef CONFIG_IGB_HWMON
572	struct hwmon_buff *igb_hwmon_buff;
573	bool ets;
574#endif
575	struct i2c_algo_bit_data i2c_algo;
576	struct i2c_adapter i2c_adap;
577	struct i2c_client *i2c_client;
578	u32 rss_indir_tbl_init;
579	u8 rss_indir_tbl[IGB_RETA_SIZE];
580
581	unsigned long link_check_timeout;
582	int copper_tries;
583	struct e1000_info ei;
584	u16 eee_advert;
585
586	/* RX network flow classification support */
587	struct hlist_head nfc_filter_list;
588	struct hlist_head cls_flower_list;
589	unsigned int nfc_filter_count;
590	/* lock for RX network flow classification filter */
591	spinlock_t nfc_lock;
592	bool etype_bitmap[MAX_ETYPE_FILTER];
593
594	struct igb_mac_addr *mac_table;
595	struct vf_mac_filter vf_macs;
596	struct vf_mac_filter *vf_mac_list;
597};
598
599/* flags controlling PTP/1588 function */
600#define IGB_PTP_ENABLED		BIT(0)
601#define IGB_PTP_OVERFLOW_CHECK	BIT(1)
602
603#define IGB_FLAG_HAS_MSI		BIT(0)
604#define IGB_FLAG_DCA_ENABLED		BIT(1)
605#define IGB_FLAG_QUAD_PORT_A		BIT(2)
606#define IGB_FLAG_QUEUE_PAIRS		BIT(3)
607#define IGB_FLAG_DMAC			BIT(4)
608#define IGB_FLAG_RSS_FIELD_IPV4_UDP	BIT(6)
609#define IGB_FLAG_RSS_FIELD_IPV6_UDP	BIT(7)
610#define IGB_FLAG_WOL_SUPPORTED		BIT(8)
611#define IGB_FLAG_NEED_LINK_UPDATE	BIT(9)
612#define IGB_FLAG_MEDIA_RESET		BIT(10)
613#define IGB_FLAG_MAS_CAPABLE		BIT(11)
614#define IGB_FLAG_MAS_ENABLE		BIT(12)
615#define IGB_FLAG_HAS_MSIX		BIT(13)
616#define IGB_FLAG_EEE			BIT(14)
617#define IGB_FLAG_VLAN_PROMISC		BIT(15)
618#define IGB_FLAG_RX_LEGACY		BIT(16)
619#define IGB_FLAG_FQTSS			BIT(17)
620
621/* Media Auto Sense */
622#define IGB_MAS_ENABLE_0		0X0001
623#define IGB_MAS_ENABLE_1		0X0002
624#define IGB_MAS_ENABLE_2		0X0004
625#define IGB_MAS_ENABLE_3		0X0008
626
627/* DMA Coalescing defines */
628#define IGB_MIN_TXPBSIZE	20408
629#define IGB_TX_BUF_4096		4096
630#define IGB_DMCTLX_DCFLUSH_DIS	0x80000000  /* Disable DMA Coal Flush */
631
632#define IGB_82576_TSYNC_SHIFT	19
633enum e1000_state_t {
634	__IGB_TESTING,
635	__IGB_RESETTING,
636	__IGB_DOWN,
637	__IGB_PTP_TX_IN_PROGRESS,
638};
639
640enum igb_boards {
641	board_82575,
642};
643
644extern char igb_driver_name[];
645extern char igb_driver_version[];
646
647int igb_open(struct net_device *netdev);
648int igb_close(struct net_device *netdev);
649int igb_up(struct igb_adapter *);
650void igb_down(struct igb_adapter *);
651void igb_reinit_locked(struct igb_adapter *);
652void igb_reset(struct igb_adapter *);
653int igb_reinit_queues(struct igb_adapter *);
654void igb_write_rss_indir_tbl(struct igb_adapter *);
655int igb_set_spd_dplx(struct igb_adapter *, u32, u8);
656int igb_setup_tx_resources(struct igb_ring *);
657int igb_setup_rx_resources(struct igb_ring *);
658void igb_free_tx_resources(struct igb_ring *);
659void igb_free_rx_resources(struct igb_ring *);
660void igb_configure_tx_ring(struct igb_adapter *, struct igb_ring *);
661void igb_configure_rx_ring(struct igb_adapter *, struct igb_ring *);
662void igb_setup_tctl(struct igb_adapter *);
663void igb_setup_rctl(struct igb_adapter *);
664void igb_setup_srrctl(struct igb_adapter *, struct igb_ring *);
665netdev_tx_t igb_xmit_frame_ring(struct sk_buff *, struct igb_ring *);
666void igb_alloc_rx_buffers(struct igb_ring *, u16);
667void igb_update_stats(struct igb_adapter *);
668bool igb_has_link(struct igb_adapter *adapter);
669void igb_set_ethtool_ops(struct net_device *);
670void igb_power_up_link(struct igb_adapter *);
671void igb_set_fw_version(struct igb_adapter *);
672void igb_ptp_init(struct igb_adapter *adapter);
673void igb_ptp_stop(struct igb_adapter *adapter);
674void igb_ptp_reset(struct igb_adapter *adapter);
675void igb_ptp_suspend(struct igb_adapter *adapter);
676void igb_ptp_rx_hang(struct igb_adapter *adapter);
677void igb_ptp_tx_hang(struct igb_adapter *adapter);
678void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector, struct sk_buff *skb);
679void igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector, void *va,
680			 struct sk_buff *skb);
681int igb_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr);
682int igb_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr);
683void igb_set_flag_queue_pairs(struct igb_adapter *, const u32);
684unsigned int igb_get_max_rss_queues(struct igb_adapter *);
685#ifdef CONFIG_IGB_HWMON
686void igb_sysfs_exit(struct igb_adapter *adapter);
687int igb_sysfs_init(struct igb_adapter *adapter);
688#endif
689static inline s32 igb_reset_phy(struct e1000_hw *hw)
690{
691	if (hw->phy.ops.reset)
692		return hw->phy.ops.reset(hw);
693
694	return 0;
695}
696
697static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data)
698{
699	if (hw->phy.ops.read_reg)
700		return hw->phy.ops.read_reg(hw, offset, data);
701
702	return 0;
703}
704
705static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)
706{
707	if (hw->phy.ops.write_reg)
708		return hw->phy.ops.write_reg(hw, offset, data);
709
710	return 0;
711}
712
713static inline s32 igb_get_phy_info(struct e1000_hw *hw)
714{
715	if (hw->phy.ops.get_phy_info)
716		return hw->phy.ops.get_phy_info(hw);
717
718	return 0;
719}
720
721static inline struct netdev_queue *txring_txq(const struct igb_ring *tx_ring)
722{
723	return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index);
724}
725
726int igb_add_filter(struct igb_adapter *adapter,
727		   struct igb_nfc_filter *input);
728int igb_erase_filter(struct igb_adapter *adapter,
729		     struct igb_nfc_filter *input);
730
731int igb_add_mac_steering_filter(struct igb_adapter *adapter,
732				const u8 *addr, u8 queue, u8 flags);
733int igb_del_mac_steering_filter(struct igb_adapter *adapter,
734				const u8 *addr, u8 queue, u8 flags);
735
736#endif /* _IGB_H_ */