/drivers/net/ethernet/intel/e1000e/ich8lan.c
C | 5952 lines | 3689 code | 779 blank | 1484 comment | 789 complexity | 03598df2fc875c966397072596100a82 MD5 | raw file
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1// SPDX-License-Identifier: GPL-2.0 2/* Copyright(c) 1999 - 2018 Intel Corporation. */ 3 4/* 82562G 10/100 Network Connection 5 * 82562G-2 10/100 Network Connection 6 * 82562GT 10/100 Network Connection 7 * 82562GT-2 10/100 Network Connection 8 * 82562V 10/100 Network Connection 9 * 82562V-2 10/100 Network Connection 10 * 82566DC-2 Gigabit Network Connection 11 * 82566DC Gigabit Network Connection 12 * 82566DM-2 Gigabit Network Connection 13 * 82566DM Gigabit Network Connection 14 * 82566MC Gigabit Network Connection 15 * 82566MM Gigabit Network Connection 16 * 82567LM Gigabit Network Connection 17 * 82567LF Gigabit Network Connection 18 * 82567V Gigabit Network Connection 19 * 82567LM-2 Gigabit Network Connection 20 * 82567LF-2 Gigabit Network Connection 21 * 82567V-2 Gigabit Network Connection 22 * 82567LF-3 Gigabit Network Connection 23 * 82567LM-3 Gigabit Network Connection 24 * 82567LM-4 Gigabit Network Connection 25 * 82577LM Gigabit Network Connection 26 * 82577LC Gigabit Network Connection 27 * 82578DM Gigabit Network Connection 28 * 82578DC Gigabit Network Connection 29 * 82579LM Gigabit Network Connection 30 * 82579V Gigabit Network Connection 31 * Ethernet Connection I217-LM 32 * Ethernet Connection I217-V 33 * Ethernet Connection I218-V 34 * Ethernet Connection I218-LM 35 * Ethernet Connection (2) I218-LM 36 * Ethernet Connection (2) I218-V 37 * Ethernet Connection (3) I218-LM 38 * Ethernet Connection (3) I218-V 39 */ 40 41#include "e1000.h" 42 43/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */ 44/* Offset 04h HSFSTS */ 45union ich8_hws_flash_status { 46 struct ich8_hsfsts { 47 u16 flcdone:1; /* bit 0 Flash Cycle Done */ 48 u16 flcerr:1; /* bit 1 Flash Cycle Error */ 49 u16 dael:1; /* bit 2 Direct Access error Log */ 50 u16 berasesz:2; /* bit 4:3 Sector Erase Size */ 51 u16 flcinprog:1; /* bit 5 flash cycle in Progress */ 52 u16 reserved1:2; /* bit 13:6 Reserved */ 53 u16 reserved2:6; /* bit 13:6 Reserved */ 54 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */ 55 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */ 56 } hsf_status; 57 u16 regval; 58}; 59 60/* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */ 61/* Offset 06h FLCTL */ 62union ich8_hws_flash_ctrl { 63 struct ich8_hsflctl { 64 u16 flcgo:1; /* 0 Flash Cycle Go */ 65 u16 flcycle:2; /* 2:1 Flash Cycle */ 66 u16 reserved:5; /* 7:3 Reserved */ 67 u16 fldbcount:2; /* 9:8 Flash Data Byte Count */ 68 u16 flockdn:6; /* 15:10 Reserved */ 69 } hsf_ctrl; 70 u16 regval; 71}; 72 73/* ICH Flash Region Access Permissions */ 74union ich8_hws_flash_regacc { 75 struct ich8_flracc { 76 u32 grra:8; /* 0:7 GbE region Read Access */ 77 u32 grwa:8; /* 8:15 GbE region Write Access */ 78 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */ 79 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */ 80 } hsf_flregacc; 81 u16 regval; 82}; 83 84/* ICH Flash Protected Region */ 85union ich8_flash_protected_range { 86 struct ich8_pr { 87 u32 base:13; /* 0:12 Protected Range Base */ 88 u32 reserved1:2; /* 13:14 Reserved */ 89 u32 rpe:1; /* 15 Read Protection Enable */ 90 u32 limit:13; /* 16:28 Protected Range Limit */ 91 u32 reserved2:2; /* 29:30 Reserved */ 92 u32 wpe:1; /* 31 Write Protection Enable */ 93 } range; 94 u32 regval; 95}; 96 97static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw); 98static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw); 99static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank); 100static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, 101 u32 offset, u8 byte); 102static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 103 u8 *data); 104static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, 105 u16 *data); 106static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 107 u8 size, u16 *data); 108static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset, 109 u32 *data); 110static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, 111 u32 offset, u32 *data); 112static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, 113 u32 offset, u32 data); 114static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw, 115 u32 offset, u32 dword); 116static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw); 117static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw); 118static s32 e1000_led_on_ich8lan(struct e1000_hw *hw); 119static s32 e1000_led_off_ich8lan(struct e1000_hw *hw); 120static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw); 121static s32 e1000_setup_led_pchlan(struct e1000_hw *hw); 122static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw); 123static s32 e1000_led_on_pchlan(struct e1000_hw *hw); 124static s32 e1000_led_off_pchlan(struct e1000_hw *hw); 125static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active); 126static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw); 127static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw); 128static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link); 129static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw); 130static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw); 131static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw); 132static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index); 133static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index); 134static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw); 135static s32 e1000_k1_workaround_lv(struct e1000_hw *hw); 136static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate); 137static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force); 138static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw); 139static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state); 140 141static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg) 142{ 143 return readw(hw->flash_address + reg); 144} 145 146static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg) 147{ 148 return readl(hw->flash_address + reg); 149} 150 151static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val) 152{ 153 writew(val, hw->flash_address + reg); 154} 155 156static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val) 157{ 158 writel(val, hw->flash_address + reg); 159} 160 161#define er16flash(reg) __er16flash(hw, (reg)) 162#define er32flash(reg) __er32flash(hw, (reg)) 163#define ew16flash(reg, val) __ew16flash(hw, (reg), (val)) 164#define ew32flash(reg, val) __ew32flash(hw, (reg), (val)) 165 166/** 167 * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers 168 * @hw: pointer to the HW structure 169 * 170 * Test access to the PHY registers by reading the PHY ID registers. If 171 * the PHY ID is already known (e.g. resume path) compare it with known ID, 172 * otherwise assume the read PHY ID is correct if it is valid. 173 * 174 * Assumes the sw/fw/hw semaphore is already acquired. 175 **/ 176static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw) 177{ 178 u16 phy_reg = 0; 179 u32 phy_id = 0; 180 s32 ret_val = 0; 181 u16 retry_count; 182 u32 mac_reg = 0; 183 184 for (retry_count = 0; retry_count < 2; retry_count++) { 185 ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg); 186 if (ret_val || (phy_reg == 0xFFFF)) 187 continue; 188 phy_id = (u32)(phy_reg << 16); 189 190 ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg); 191 if (ret_val || (phy_reg == 0xFFFF)) { 192 phy_id = 0; 193 continue; 194 } 195 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK); 196 break; 197 } 198 199 if (hw->phy.id) { 200 if (hw->phy.id == phy_id) 201 goto out; 202 } else if (phy_id) { 203 hw->phy.id = phy_id; 204 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK); 205 goto out; 206 } 207 208 /* In case the PHY needs to be in mdio slow mode, 209 * set slow mode and try to get the PHY id again. 210 */ 211 if (hw->mac.type < e1000_pch_lpt) { 212 hw->phy.ops.release(hw); 213 ret_val = e1000_set_mdio_slow_mode_hv(hw); 214 if (!ret_val) 215 ret_val = e1000e_get_phy_id(hw); 216 hw->phy.ops.acquire(hw); 217 } 218 219 if (ret_val) 220 return false; 221out: 222 if (hw->mac.type >= e1000_pch_lpt) { 223 /* Only unforce SMBus if ME is not active */ 224 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { 225 /* Unforce SMBus mode in PHY */ 226 e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg); 227 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS; 228 e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg); 229 230 /* Unforce SMBus mode in MAC */ 231 mac_reg = er32(CTRL_EXT); 232 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; 233 ew32(CTRL_EXT, mac_reg); 234 } 235 } 236 237 return true; 238} 239 240/** 241 * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value 242 * @hw: pointer to the HW structure 243 * 244 * Toggling the LANPHYPC pin value fully power-cycles the PHY and is 245 * used to reset the PHY to a quiescent state when necessary. 246 **/ 247static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw) 248{ 249 u32 mac_reg; 250 251 /* Set Phy Config Counter to 50msec */ 252 mac_reg = er32(FEXTNVM3); 253 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK; 254 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC; 255 ew32(FEXTNVM3, mac_reg); 256 257 /* Toggle LANPHYPC Value bit */ 258 mac_reg = er32(CTRL); 259 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE; 260 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE; 261 ew32(CTRL, mac_reg); 262 e1e_flush(); 263 usleep_range(10, 20); 264 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE; 265 ew32(CTRL, mac_reg); 266 e1e_flush(); 267 268 if (hw->mac.type < e1000_pch_lpt) { 269 msleep(50); 270 } else { 271 u16 count = 20; 272 273 do { 274 usleep_range(5000, 6000); 275 } while (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LPCD) && count--); 276 277 msleep(30); 278 } 279} 280 281/** 282 * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds 283 * @hw: pointer to the HW structure 284 * 285 * Workarounds/flow necessary for PHY initialization during driver load 286 * and resume paths. 287 **/ 288static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw) 289{ 290 struct e1000_adapter *adapter = hw->adapter; 291 u32 mac_reg, fwsm = er32(FWSM); 292 s32 ret_val; 293 294 /* Gate automatic PHY configuration by hardware on managed and 295 * non-managed 82579 and newer adapters. 296 */ 297 e1000_gate_hw_phy_config_ich8lan(hw, true); 298 299 /* It is not possible to be certain of the current state of ULP 300 * so forcibly disable it. 301 */ 302 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown; 303 e1000_disable_ulp_lpt_lp(hw, true); 304 305 ret_val = hw->phy.ops.acquire(hw); 306 if (ret_val) { 307 e_dbg("Failed to initialize PHY flow\n"); 308 goto out; 309 } 310 311 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is 312 * inaccessible and resetting the PHY is not blocked, toggle the 313 * LANPHYPC Value bit to force the interconnect to PCIe mode. 314 */ 315 switch (hw->mac.type) { 316 case e1000_pch_lpt: 317 case e1000_pch_spt: 318 case e1000_pch_cnp: 319 case e1000_pch_tgp: 320 case e1000_pch_adp: 321 if (e1000_phy_is_accessible_pchlan(hw)) 322 break; 323 324 /* Before toggling LANPHYPC, see if PHY is accessible by 325 * forcing MAC to SMBus mode first. 326 */ 327 mac_reg = er32(CTRL_EXT); 328 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS; 329 ew32(CTRL_EXT, mac_reg); 330 331 /* Wait 50 milliseconds for MAC to finish any retries 332 * that it might be trying to perform from previous 333 * attempts to acknowledge any phy read requests. 334 */ 335 msleep(50); 336 337 /* fall-through */ 338 case e1000_pch2lan: 339 if (e1000_phy_is_accessible_pchlan(hw)) 340 break; 341 342 /* fall-through */ 343 case e1000_pchlan: 344 if ((hw->mac.type == e1000_pchlan) && 345 (fwsm & E1000_ICH_FWSM_FW_VALID)) 346 break; 347 348 if (hw->phy.ops.check_reset_block(hw)) { 349 e_dbg("Required LANPHYPC toggle blocked by ME\n"); 350 ret_val = -E1000_ERR_PHY; 351 break; 352 } 353 354 /* Toggle LANPHYPC Value bit */ 355 e1000_toggle_lanphypc_pch_lpt(hw); 356 if (hw->mac.type >= e1000_pch_lpt) { 357 if (e1000_phy_is_accessible_pchlan(hw)) 358 break; 359 360 /* Toggling LANPHYPC brings the PHY out of SMBus mode 361 * so ensure that the MAC is also out of SMBus mode 362 */ 363 mac_reg = er32(CTRL_EXT); 364 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; 365 ew32(CTRL_EXT, mac_reg); 366 367 if (e1000_phy_is_accessible_pchlan(hw)) 368 break; 369 370 ret_val = -E1000_ERR_PHY; 371 } 372 break; 373 default: 374 break; 375 } 376 377 hw->phy.ops.release(hw); 378 if (!ret_val) { 379 380 /* Check to see if able to reset PHY. Print error if not */ 381 if (hw->phy.ops.check_reset_block(hw)) { 382 e_err("Reset blocked by ME\n"); 383 goto out; 384 } 385 386 /* Reset the PHY before any access to it. Doing so, ensures 387 * that the PHY is in a known good state before we read/write 388 * PHY registers. The generic reset is sufficient here, 389 * because we haven't determined the PHY type yet. 390 */ 391 ret_val = e1000e_phy_hw_reset_generic(hw); 392 if (ret_val) 393 goto out; 394 395 /* On a successful reset, possibly need to wait for the PHY 396 * to quiesce to an accessible state before returning control 397 * to the calling function. If the PHY does not quiesce, then 398 * return E1000E_BLK_PHY_RESET, as this is the condition that 399 * the PHY is in. 400 */ 401 ret_val = hw->phy.ops.check_reset_block(hw); 402 if (ret_val) 403 e_err("ME blocked access to PHY after reset\n"); 404 } 405 406out: 407 /* Ungate automatic PHY configuration on non-managed 82579 */ 408 if ((hw->mac.type == e1000_pch2lan) && 409 !(fwsm & E1000_ICH_FWSM_FW_VALID)) { 410 usleep_range(10000, 11000); 411 e1000_gate_hw_phy_config_ich8lan(hw, false); 412 } 413 414 return ret_val; 415} 416 417/** 418 * e1000_init_phy_params_pchlan - Initialize PHY function pointers 419 * @hw: pointer to the HW structure 420 * 421 * Initialize family-specific PHY parameters and function pointers. 422 **/ 423static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw) 424{ 425 struct e1000_phy_info *phy = &hw->phy; 426 s32 ret_val; 427 428 phy->addr = 1; 429 phy->reset_delay_us = 100; 430 431 phy->ops.set_page = e1000_set_page_igp; 432 phy->ops.read_reg = e1000_read_phy_reg_hv; 433 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked; 434 phy->ops.read_reg_page = e1000_read_phy_reg_page_hv; 435 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan; 436 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan; 437 phy->ops.write_reg = e1000_write_phy_reg_hv; 438 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked; 439 phy->ops.write_reg_page = e1000_write_phy_reg_page_hv; 440 phy->ops.power_up = e1000_power_up_phy_copper; 441 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; 442 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 443 444 phy->id = e1000_phy_unknown; 445 446 ret_val = e1000_init_phy_workarounds_pchlan(hw); 447 if (ret_val) 448 return ret_val; 449 450 if (phy->id == e1000_phy_unknown) 451 switch (hw->mac.type) { 452 default: 453 ret_val = e1000e_get_phy_id(hw); 454 if (ret_val) 455 return ret_val; 456 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK)) 457 break; 458 /* fall-through */ 459 case e1000_pch2lan: 460 case e1000_pch_lpt: 461 case e1000_pch_spt: 462 case e1000_pch_cnp: 463 case e1000_pch_tgp: 464 case e1000_pch_adp: 465 /* In case the PHY needs to be in mdio slow mode, 466 * set slow mode and try to get the PHY id again. 467 */ 468 ret_val = e1000_set_mdio_slow_mode_hv(hw); 469 if (ret_val) 470 return ret_val; 471 ret_val = e1000e_get_phy_id(hw); 472 if (ret_val) 473 return ret_val; 474 break; 475 } 476 phy->type = e1000e_get_phy_type_from_id(phy->id); 477 478 switch (phy->type) { 479 case e1000_phy_82577: 480 case e1000_phy_82579: 481 case e1000_phy_i217: 482 phy->ops.check_polarity = e1000_check_polarity_82577; 483 phy->ops.force_speed_duplex = 484 e1000_phy_force_speed_duplex_82577; 485 phy->ops.get_cable_length = e1000_get_cable_length_82577; 486 phy->ops.get_info = e1000_get_phy_info_82577; 487 phy->ops.commit = e1000e_phy_sw_reset; 488 break; 489 case e1000_phy_82578: 490 phy->ops.check_polarity = e1000_check_polarity_m88; 491 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88; 492 phy->ops.get_cable_length = e1000e_get_cable_length_m88; 493 phy->ops.get_info = e1000e_get_phy_info_m88; 494 break; 495 default: 496 ret_val = -E1000_ERR_PHY; 497 break; 498 } 499 500 return ret_val; 501} 502 503/** 504 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers 505 * @hw: pointer to the HW structure 506 * 507 * Initialize family-specific PHY parameters and function pointers. 508 **/ 509static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw) 510{ 511 struct e1000_phy_info *phy = &hw->phy; 512 s32 ret_val; 513 u16 i = 0; 514 515 phy->addr = 1; 516 phy->reset_delay_us = 100; 517 518 phy->ops.power_up = e1000_power_up_phy_copper; 519 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; 520 521 /* We may need to do this twice - once for IGP and if that fails, 522 * we'll set BM func pointers and try again 523 */ 524 ret_val = e1000e_determine_phy_address(hw); 525 if (ret_val) { 526 phy->ops.write_reg = e1000e_write_phy_reg_bm; 527 phy->ops.read_reg = e1000e_read_phy_reg_bm; 528 ret_val = e1000e_determine_phy_address(hw); 529 if (ret_val) { 530 e_dbg("Cannot determine PHY addr. Erroring out\n"); 531 return ret_val; 532 } 533 } 534 535 phy->id = 0; 536 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) && 537 (i++ < 100)) { 538 usleep_range(1000, 1100); 539 ret_val = e1000e_get_phy_id(hw); 540 if (ret_val) 541 return ret_val; 542 } 543 544 /* Verify phy id */ 545 switch (phy->id) { 546 case IGP03E1000_E_PHY_ID: 547 phy->type = e1000_phy_igp_3; 548 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 549 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked; 550 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked; 551 phy->ops.get_info = e1000e_get_phy_info_igp; 552 phy->ops.check_polarity = e1000_check_polarity_igp; 553 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp; 554 break; 555 case IFE_E_PHY_ID: 556 case IFE_PLUS_E_PHY_ID: 557 case IFE_C_E_PHY_ID: 558 phy->type = e1000_phy_ife; 559 phy->autoneg_mask = E1000_ALL_NOT_GIG; 560 phy->ops.get_info = e1000_get_phy_info_ife; 561 phy->ops.check_polarity = e1000_check_polarity_ife; 562 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife; 563 break; 564 case BME1000_E_PHY_ID: 565 phy->type = e1000_phy_bm; 566 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 567 phy->ops.read_reg = e1000e_read_phy_reg_bm; 568 phy->ops.write_reg = e1000e_write_phy_reg_bm; 569 phy->ops.commit = e1000e_phy_sw_reset; 570 phy->ops.get_info = e1000e_get_phy_info_m88; 571 phy->ops.check_polarity = e1000_check_polarity_m88; 572 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88; 573 break; 574 default: 575 return -E1000_ERR_PHY; 576 } 577 578 return 0; 579} 580 581/** 582 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers 583 * @hw: pointer to the HW structure 584 * 585 * Initialize family-specific NVM parameters and function 586 * pointers. 587 **/ 588static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw) 589{ 590 struct e1000_nvm_info *nvm = &hw->nvm; 591 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 592 u32 gfpreg, sector_base_addr, sector_end_addr; 593 u16 i; 594 u32 nvm_size; 595 596 nvm->type = e1000_nvm_flash_sw; 597 598 if (hw->mac.type >= e1000_pch_spt) { 599 /* in SPT, gfpreg doesn't exist. NVM size is taken from the 600 * STRAP register. This is because in SPT the GbE Flash region 601 * is no longer accessed through the flash registers. Instead, 602 * the mechanism has changed, and the Flash region access 603 * registers are now implemented in GbE memory space. 604 */ 605 nvm->flash_base_addr = 0; 606 nvm_size = (((er32(STRAP) >> 1) & 0x1F) + 1) 607 * NVM_SIZE_MULTIPLIER; 608 nvm->flash_bank_size = nvm_size / 2; 609 /* Adjust to word count */ 610 nvm->flash_bank_size /= sizeof(u16); 611 /* Set the base address for flash register access */ 612 hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR; 613 } else { 614 /* Can't read flash registers if register set isn't mapped. */ 615 if (!hw->flash_address) { 616 e_dbg("ERROR: Flash registers not mapped\n"); 617 return -E1000_ERR_CONFIG; 618 } 619 620 gfpreg = er32flash(ICH_FLASH_GFPREG); 621 622 /* sector_X_addr is a "sector"-aligned address (4096 bytes) 623 * Add 1 to sector_end_addr since this sector is included in 624 * the overall size. 625 */ 626 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK; 627 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1; 628 629 /* flash_base_addr is byte-aligned */ 630 nvm->flash_base_addr = sector_base_addr 631 << FLASH_SECTOR_ADDR_SHIFT; 632 633 /* find total size of the NVM, then cut in half since the total 634 * size represents two separate NVM banks. 635 */ 636 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr) 637 << FLASH_SECTOR_ADDR_SHIFT); 638 nvm->flash_bank_size /= 2; 639 /* Adjust to word count */ 640 nvm->flash_bank_size /= sizeof(u16); 641 } 642 643 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS; 644 645 /* Clear shadow ram */ 646 for (i = 0; i < nvm->word_size; i++) { 647 dev_spec->shadow_ram[i].modified = false; 648 dev_spec->shadow_ram[i].value = 0xFFFF; 649 } 650 651 return 0; 652} 653 654/** 655 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers 656 * @hw: pointer to the HW structure 657 * 658 * Initialize family-specific MAC parameters and function 659 * pointers. 660 **/ 661static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw) 662{ 663 struct e1000_mac_info *mac = &hw->mac; 664 665 /* Set media type function pointer */ 666 hw->phy.media_type = e1000_media_type_copper; 667 668 /* Set mta register count */ 669 mac->mta_reg_count = 32; 670 /* Set rar entry count */ 671 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES; 672 if (mac->type == e1000_ich8lan) 673 mac->rar_entry_count--; 674 /* FWSM register */ 675 mac->has_fwsm = true; 676 /* ARC subsystem not supported */ 677 mac->arc_subsystem_valid = false; 678 /* Adaptive IFS supported */ 679 mac->adaptive_ifs = true; 680 681 /* LED and other operations */ 682 switch (mac->type) { 683 case e1000_ich8lan: 684 case e1000_ich9lan: 685 case e1000_ich10lan: 686 /* check management mode */ 687 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan; 688 /* ID LED init */ 689 mac->ops.id_led_init = e1000e_id_led_init_generic; 690 /* blink LED */ 691 mac->ops.blink_led = e1000e_blink_led_generic; 692 /* setup LED */ 693 mac->ops.setup_led = e1000e_setup_led_generic; 694 /* cleanup LED */ 695 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan; 696 /* turn on/off LED */ 697 mac->ops.led_on = e1000_led_on_ich8lan; 698 mac->ops.led_off = e1000_led_off_ich8lan; 699 break; 700 case e1000_pch2lan: 701 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES; 702 mac->ops.rar_set = e1000_rar_set_pch2lan; 703 /* fall-through */ 704 case e1000_pch_lpt: 705 case e1000_pch_spt: 706 case e1000_pch_cnp: 707 case e1000_pch_tgp: 708 case e1000_pch_adp: 709 case e1000_pchlan: 710 /* check management mode */ 711 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan; 712 /* ID LED init */ 713 mac->ops.id_led_init = e1000_id_led_init_pchlan; 714 /* setup LED */ 715 mac->ops.setup_led = e1000_setup_led_pchlan; 716 /* cleanup LED */ 717 mac->ops.cleanup_led = e1000_cleanup_led_pchlan; 718 /* turn on/off LED */ 719 mac->ops.led_on = e1000_led_on_pchlan; 720 mac->ops.led_off = e1000_led_off_pchlan; 721 break; 722 default: 723 break; 724 } 725 726 if (mac->type >= e1000_pch_lpt) { 727 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES; 728 mac->ops.rar_set = e1000_rar_set_pch_lpt; 729 mac->ops.setup_physical_interface = 730 e1000_setup_copper_link_pch_lpt; 731 mac->ops.rar_get_count = e1000_rar_get_count_pch_lpt; 732 } 733 734 /* Enable PCS Lock-loss workaround for ICH8 */ 735 if (mac->type == e1000_ich8lan) 736 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true); 737 738 return 0; 739} 740 741/** 742 * __e1000_access_emi_reg_locked - Read/write EMI register 743 * @hw: pointer to the HW structure 744 * @addr: EMI address to program 745 * @data: pointer to value to read/write from/to the EMI address 746 * @read: boolean flag to indicate read or write 747 * 748 * This helper function assumes the SW/FW/HW Semaphore is already acquired. 749 **/ 750static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address, 751 u16 *data, bool read) 752{ 753 s32 ret_val; 754 755 ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address); 756 if (ret_val) 757 return ret_val; 758 759 if (read) 760 ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data); 761 else 762 ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, *data); 763 764 return ret_val; 765} 766 767/** 768 * e1000_read_emi_reg_locked - Read Extended Management Interface register 769 * @hw: pointer to the HW structure 770 * @addr: EMI address to program 771 * @data: value to be read from the EMI address 772 * 773 * Assumes the SW/FW/HW Semaphore is already acquired. 774 **/ 775s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data) 776{ 777 return __e1000_access_emi_reg_locked(hw, addr, data, true); 778} 779 780/** 781 * e1000_write_emi_reg_locked - Write Extended Management Interface register 782 * @hw: pointer to the HW structure 783 * @addr: EMI address to program 784 * @data: value to be written to the EMI address 785 * 786 * Assumes the SW/FW/HW Semaphore is already acquired. 787 **/ 788s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data) 789{ 790 return __e1000_access_emi_reg_locked(hw, addr, &data, false); 791} 792 793/** 794 * e1000_set_eee_pchlan - Enable/disable EEE support 795 * @hw: pointer to the HW structure 796 * 797 * Enable/disable EEE based on setting in dev_spec structure, the duplex of 798 * the link and the EEE capabilities of the link partner. The LPI Control 799 * register bits will remain set only if/when link is up. 800 * 801 * EEE LPI must not be asserted earlier than one second after link is up. 802 * On 82579, EEE LPI should not be enabled until such time otherwise there 803 * can be link issues with some switches. Other devices can have EEE LPI 804 * enabled immediately upon link up since they have a timer in hardware which 805 * prevents LPI from being asserted too early. 806 **/ 807s32 e1000_set_eee_pchlan(struct e1000_hw *hw) 808{ 809 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 810 s32 ret_val; 811 u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data; 812 813 switch (hw->phy.type) { 814 case e1000_phy_82579: 815 lpa = I82579_EEE_LP_ABILITY; 816 pcs_status = I82579_EEE_PCS_STATUS; 817 adv_addr = I82579_EEE_ADVERTISEMENT; 818 break; 819 case e1000_phy_i217: 820 lpa = I217_EEE_LP_ABILITY; 821 pcs_status = I217_EEE_PCS_STATUS; 822 adv_addr = I217_EEE_ADVERTISEMENT; 823 break; 824 default: 825 return 0; 826 } 827 828 ret_val = hw->phy.ops.acquire(hw); 829 if (ret_val) 830 return ret_val; 831 832 ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, &lpi_ctrl); 833 if (ret_val) 834 goto release; 835 836 /* Clear bits that enable EEE in various speeds */ 837 lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK; 838 839 /* Enable EEE if not disabled by user */ 840 if (!dev_spec->eee_disable) { 841 /* Save off link partner's EEE ability */ 842 ret_val = e1000_read_emi_reg_locked(hw, lpa, 843 &dev_spec->eee_lp_ability); 844 if (ret_val) 845 goto release; 846 847 /* Read EEE advertisement */ 848 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv); 849 if (ret_val) 850 goto release; 851 852 /* Enable EEE only for speeds in which the link partner is 853 * EEE capable and for which we advertise EEE. 854 */ 855 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED) 856 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE; 857 858 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) { 859 e1e_rphy_locked(hw, MII_LPA, &data); 860 if (data & LPA_100FULL) 861 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE; 862 else 863 /* EEE is not supported in 100Half, so ignore 864 * partner's EEE in 100 ability if full-duplex 865 * is not advertised. 866 */ 867 dev_spec->eee_lp_ability &= 868 ~I82579_EEE_100_SUPPORTED; 869 } 870 } 871 872 if (hw->phy.type == e1000_phy_82579) { 873 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT, 874 &data); 875 if (ret_val) 876 goto release; 877 878 data &= ~I82579_LPI_100_PLL_SHUT; 879 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT, 880 data); 881 } 882 883 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */ 884 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data); 885 if (ret_val) 886 goto release; 887 888 ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, lpi_ctrl); 889release: 890 hw->phy.ops.release(hw); 891 892 return ret_val; 893} 894 895/** 896 * e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP 897 * @hw: pointer to the HW structure 898 * @link: link up bool flag 899 * 900 * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications 901 * preventing further DMA write requests. Workaround the issue by disabling 902 * the de-assertion of the clock request when in 1Gpbs mode. 903 * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link 904 * speeds in order to avoid Tx hangs. 905 **/ 906static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link) 907{ 908 u32 fextnvm6 = er32(FEXTNVM6); 909 u32 status = er32(STATUS); 910 s32 ret_val = 0; 911 u16 reg; 912 913 if (link && (status & E1000_STATUS_SPEED_1000)) { 914 ret_val = hw->phy.ops.acquire(hw); 915 if (ret_val) 916 return ret_val; 917 918 ret_val = 919 e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 920 ®); 921 if (ret_val) 922 goto release; 923 924 ret_val = 925 e1000e_write_kmrn_reg_locked(hw, 926 E1000_KMRNCTRLSTA_K1_CONFIG, 927 reg & 928 ~E1000_KMRNCTRLSTA_K1_ENABLE); 929 if (ret_val) 930 goto release; 931 932 usleep_range(10, 20); 933 934 ew32(FEXTNVM6, fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK); 935 936 ret_val = 937 e1000e_write_kmrn_reg_locked(hw, 938 E1000_KMRNCTRLSTA_K1_CONFIG, 939 reg); 940release: 941 hw->phy.ops.release(hw); 942 } else { 943 /* clear FEXTNVM6 bit 8 on link down or 10/100 */ 944 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK; 945 946 if ((hw->phy.revision > 5) || !link || 947 ((status & E1000_STATUS_SPEED_100) && 948 (status & E1000_STATUS_FD))) 949 goto update_fextnvm6; 950 951 ret_val = e1e_rphy(hw, I217_INBAND_CTRL, ®); 952 if (ret_val) 953 return ret_val; 954 955 /* Clear link status transmit timeout */ 956 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK; 957 958 if (status & E1000_STATUS_SPEED_100) { 959 /* Set inband Tx timeout to 5x10us for 100Half */ 960 reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT; 961 962 /* Do not extend the K1 entry latency for 100Half */ 963 fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION; 964 } else { 965 /* Set inband Tx timeout to 50x10us for 10Full/Half */ 966 reg |= 50 << 967 I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT; 968 969 /* Extend the K1 entry latency for 10 Mbps */ 970 fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION; 971 } 972 973 ret_val = e1e_wphy(hw, I217_INBAND_CTRL, reg); 974 if (ret_val) 975 return ret_val; 976 977update_fextnvm6: 978 ew32(FEXTNVM6, fextnvm6); 979 } 980 981 return ret_val; 982} 983 984/** 985 * e1000_platform_pm_pch_lpt - Set platform power management values 986 * @hw: pointer to the HW structure 987 * @link: bool indicating link status 988 * 989 * Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like" 990 * GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed 991 * when link is up (which must not exceed the maximum latency supported 992 * by the platform), otherwise specify there is no LTR requirement. 993 * Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop 994 * latencies in the LTR Extended Capability Structure in the PCIe Extended 995 * Capability register set, on this device LTR is set by writing the 996 * equivalent snoop/no-snoop latencies in the LTRV register in the MAC and 997 * set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB) 998 * message to the PMC. 999 **/ 1000static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link) 1001{ 1002 u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) | 1003 link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND; 1004 u16 lat_enc = 0; /* latency encoded */ 1005 1006 if (link) { 1007 u16 speed, duplex, scale = 0; 1008 u16 max_snoop, max_nosnoop; 1009 u16 max_ltr_enc; /* max LTR latency encoded */ 1010 u64 value; 1011 u32 rxa; 1012 1013 if (!hw->adapter->max_frame_size) { 1014 e_dbg("max_frame_size not set.\n"); 1015 return -E1000_ERR_CONFIG; 1016 } 1017 1018 hw->mac.ops.get_link_up_info(hw, &speed, &duplex); 1019 if (!speed) { 1020 e_dbg("Speed not set.\n"); 1021 return -E1000_ERR_CONFIG; 1022 } 1023 1024 /* Rx Packet Buffer Allocation size (KB) */ 1025 rxa = er32(PBA) & E1000_PBA_RXA_MASK; 1026 1027 /* Determine the maximum latency tolerated by the device. 1028 * 1029 * Per the PCIe spec, the tolerated latencies are encoded as 1030 * a 3-bit encoded scale (only 0-5 are valid) multiplied by 1031 * a 10-bit value (0-1023) to provide a range from 1 ns to 1032 * 2^25*(2^10-1) ns. The scale is encoded as 0=2^0ns, 1033 * 1=2^5ns, 2=2^10ns,...5=2^25ns. 1034 */ 1035 rxa *= 512; 1036 value = (rxa > hw->adapter->max_frame_size) ? 1037 (rxa - hw->adapter->max_frame_size) * (16000 / speed) : 1038 0; 1039 1040 while (value > PCI_LTR_VALUE_MASK) { 1041 scale++; 1042 value = DIV_ROUND_UP(value, BIT(5)); 1043 } 1044 if (scale > E1000_LTRV_SCALE_MAX) { 1045 e_dbg("Invalid LTR latency scale %d\n", scale); 1046 return -E1000_ERR_CONFIG; 1047 } 1048 lat_enc = (u16)((scale << PCI_LTR_SCALE_SHIFT) | value); 1049 1050 /* Determine the maximum latency tolerated by the platform */ 1051 pci_read_config_word(hw->adapter->pdev, E1000_PCI_LTR_CAP_LPT, 1052 &max_snoop); 1053 pci_read_config_word(hw->adapter->pdev, 1054 E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop); 1055 max_ltr_enc = max_t(u16, max_snoop, max_nosnoop); 1056 1057 if (lat_enc > max_ltr_enc) 1058 lat_enc = max_ltr_enc; 1059 } 1060 1061 /* Set Snoop and No-Snoop latencies the same */ 1062 reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT); 1063 ew32(LTRV, reg); 1064 1065 return 0; 1066} 1067 1068/** 1069 * e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP 1070 * @hw: pointer to the HW structure 1071 * @to_sx: boolean indicating a system power state transition to Sx 1072 * 1073 * When link is down, configure ULP mode to significantly reduce the power 1074 * to the PHY. If on a Manageability Engine (ME) enabled system, tell the 1075 * ME firmware to start the ULP configuration. If not on an ME enabled 1076 * system, configure the ULP mode by software. 1077 */ 1078s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx) 1079{ 1080 u32 mac_reg; 1081 s32 ret_val = 0; 1082 u16 phy_reg; 1083 u16 oem_reg = 0; 1084 1085 if ((hw->mac.type < e1000_pch_lpt) || 1086 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) || 1087 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) || 1088 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) || 1089 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) || 1090 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on)) 1091 return 0; 1092 1093 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) { 1094 /* Request ME configure ULP mode in the PHY */ 1095 mac_reg = er32(H2ME); 1096 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS; 1097 ew32(H2ME, mac_reg); 1098 1099 goto out; 1100 } 1101 1102 if (!to_sx) { 1103 int i = 0; 1104 1105 /* Poll up to 5 seconds for Cable Disconnected indication */ 1106 while (!(er32(FEXT) & E1000_FEXT_PHY_CABLE_DISCONNECTED)) { 1107 /* Bail if link is re-acquired */ 1108 if (er32(STATUS) & E1000_STATUS_LU) 1109 return -E1000_ERR_PHY; 1110 1111 if (i++ == 100) 1112 break; 1113 1114 msleep(50); 1115 } 1116 e_dbg("CABLE_DISCONNECTED %s set after %dmsec\n", 1117 (er32(FEXT) & 1118 E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not", i * 50); 1119 } 1120 1121 ret_val = hw->phy.ops.acquire(hw); 1122 if (ret_val) 1123 goto out; 1124 1125 /* Force SMBus mode in PHY */ 1126 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg); 1127 if (ret_val) 1128 goto release; 1129 phy_reg |= CV_SMB_CTRL_FORCE_SMBUS; 1130 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg); 1131 1132 /* Force SMBus mode in MAC */ 1133 mac_reg = er32(CTRL_EXT); 1134 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS; 1135 ew32(CTRL_EXT, mac_reg); 1136 1137 /* Si workaround for ULP entry flow on i127/rev6 h/w. Enable 1138 * LPLU and disable Gig speed when entering ULP 1139 */ 1140 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) { 1141 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS, 1142 &oem_reg); 1143 if (ret_val) 1144 goto release; 1145 1146 phy_reg = oem_reg; 1147 phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS; 1148 1149 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS, 1150 phy_reg); 1151 1152 if (ret_val) 1153 goto release; 1154 } 1155 1156 /* Set Inband ULP Exit, Reset to SMBus mode and 1157 * Disable SMBus Release on PERST# in PHY 1158 */ 1159 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg); 1160 if (ret_val) 1161 goto release; 1162 phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS | 1163 I218_ULP_CONFIG1_DISABLE_SMB_PERST); 1164 if (to_sx) { 1165 if (er32(WUFC) & E1000_WUFC_LNKC) 1166 phy_reg |= I218_ULP_CONFIG1_WOL_HOST; 1167 else 1168 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST; 1169 1170 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP; 1171 phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT; 1172 } else { 1173 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT; 1174 phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP; 1175 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST; 1176 } 1177 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1178 1179 /* Set Disable SMBus Release on PERST# in MAC */ 1180 mac_reg = er32(FEXTNVM7); 1181 mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST; 1182 ew32(FEXTNVM7, mac_reg); 1183 1184 /* Commit ULP changes in PHY by starting auto ULP configuration */ 1185 phy_reg |= I218_ULP_CONFIG1_START; 1186 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1187 1188 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) && 1189 to_sx && (er32(STATUS) & E1000_STATUS_LU)) { 1190 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS, 1191 oem_reg); 1192 if (ret_val) 1193 goto release; 1194 } 1195 1196release: 1197 hw->phy.ops.release(hw); 1198out: 1199 if (ret_val) 1200 e_dbg("Error in ULP enable flow: %d\n", ret_val); 1201 else 1202 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on; 1203 1204 return ret_val; 1205} 1206 1207/** 1208 * e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP 1209 * @hw: pointer to the HW structure 1210 * @force: boolean indicating whether or not to force disabling ULP 1211 * 1212 * Un-configure ULP mode when link is up, the system is transitioned from 1213 * Sx or the driver is unloaded. If on a Manageability Engine (ME) enabled 1214 * system, poll for an indication from ME that ULP has been un-configured. 1215 * If not on an ME enabled system, un-configure the ULP mode by software. 1216 * 1217 * During nominal operation, this function is called when link is acquired 1218 * to disable ULP mode (force=false); otherwise, for example when unloading 1219 * the driver or during Sx->S0 transitions, this is called with force=true 1220 * to forcibly disable ULP. 1221 */ 1222static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force) 1223{ 1224 s32 ret_val = 0; 1225 u32 mac_reg; 1226 u16 phy_reg; 1227 int i = 0; 1228 1229 if ((hw->mac.type < e1000_pch_lpt) || 1230 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) || 1231 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) || 1232 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) || 1233 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) || 1234 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off)) 1235 return 0; 1236 1237 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) { 1238 if (force) { 1239 /* Request ME un-configure ULP mode in the PHY */ 1240 mac_reg = er32(H2ME); 1241 mac_reg &= ~E1000_H2ME_ULP; 1242 mac_reg |= E1000_H2ME_ENFORCE_SETTINGS; 1243 ew32(H2ME, mac_reg); 1244 } 1245 1246 /* Poll up to 300msec for ME to clear ULP_CFG_DONE. */ 1247 while (er32(FWSM) & E1000_FWSM_ULP_CFG_DONE) { 1248 if (i++ == 30) { 1249 ret_val = -E1000_ERR_PHY; 1250 goto out; 1251 } 1252 1253 usleep_range(10000, 11000); 1254 } 1255 e_dbg("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10); 1256 1257 if (force) { 1258 mac_reg = er32(H2ME); 1259 mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS; 1260 ew32(H2ME, mac_reg); 1261 } else { 1262 /* Clear H2ME.ULP after ME ULP configuration */ 1263 mac_reg = er32(H2ME); 1264 mac_reg &= ~E1000_H2ME_ULP; 1265 ew32(H2ME, mac_reg); 1266 } 1267 1268 goto out; 1269 } 1270 1271 ret_val = hw->phy.ops.acquire(hw); 1272 if (ret_val) 1273 goto out; 1274 1275 if (force) 1276 /* Toggle LANPHYPC Value bit */ 1277 e1000_toggle_lanphypc_pch_lpt(hw); 1278 1279 /* Unforce SMBus mode in PHY */ 1280 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg); 1281 if (ret_val) { 1282 /* The MAC might be in PCIe mode, so temporarily force to 1283 * SMBus mode in order to access the PHY. 1284 */ 1285 mac_reg = er32(CTRL_EXT); 1286 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS; 1287 ew32(CTRL_EXT, mac_reg); 1288 1289 msleep(50); 1290 1291 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, 1292 &phy_reg); 1293 if (ret_val) 1294 goto release; 1295 } 1296 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS; 1297 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg); 1298 1299 /* Unforce SMBus mode in MAC */ 1300 mac_reg = er32(CTRL_EXT); 1301 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; 1302 ew32(CTRL_EXT, mac_reg); 1303 1304 /* When ULP mode was previously entered, K1 was disabled by the 1305 * hardware. Re-Enable K1 in the PHY when exiting ULP. 1306 */ 1307 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg); 1308 if (ret_val) 1309 goto release; 1310 phy_reg |= HV_PM_CTRL_K1_ENABLE; 1311 e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg); 1312 1313 /* Clear ULP enabled configuration */ 1314 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg); 1315 if (ret_val) 1316 goto release; 1317 phy_reg &= ~(I218_ULP_CONFIG1_IND | 1318 I218_ULP_CONFIG1_STICKY_ULP | 1319 I218_ULP_CONFIG1_RESET_TO_SMBUS | 1320 I218_ULP_CONFIG1_WOL_HOST | 1321 I218_ULP_CONFIG1_INBAND_EXIT | 1322 I218_ULP_CONFIG1_EN_ULP_LANPHYPC | 1323 I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST | 1324 I218_ULP_CONFIG1_DISABLE_SMB_PERST); 1325 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1326 1327 /* Commit ULP changes by starting auto ULP configuration */ 1328 phy_reg |= I218_ULP_CONFIG1_START; 1329 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1330 1331 /* Clear Disable SMBus Release on PERST# in MAC */ 1332 mac_reg = er32(FEXTNVM7); 1333 mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST; 1334 ew32(FEXTNVM7, mac_reg); 1335 1336release: 1337 hw->phy.ops.release(hw); 1338 if (force) { 1339 e1000_phy_hw_reset(hw); 1340 msleep(50); 1341 } 1342out: 1343 if (ret_val) 1344 e_dbg("Error in ULP disable flow: %d\n", ret_val); 1345 else 1346 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off; 1347 1348 return ret_val; 1349} 1350 1351/** 1352 * e1000_check_for_copper_link_ich8lan - Check for link (Copper) 1353 * @hw: pointer to the HW structure 1354 * 1355 * Checks to see of the link status of the hardware has changed. If a 1356 * change in link status has been detected, then we read the PHY registers 1357 * to get the current speed/duplex if link exists. 1358 **/ 1359static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw) 1360{ 1361 struct e1000_mac_info *mac = &hw->mac; 1362 s32 ret_val, tipg_reg = 0; 1363 u16 emi_addr, emi_val = 0; 1364 bool link; 1365 u16 phy_reg; 1366 1367 /* We only want to go out to the PHY registers to see if Auto-Neg 1368 * has completed and/or if our link status has changed. The 1369 * get_link_status flag is set upon receiving a Link Status 1370 * Change or Rx Sequence Error interrupt. 1371 */ 1372 if (!mac->get_link_status) 1373 return 0; 1374 mac->get_link_status = false; 1375 1376 /* First we want to see if the MII Status Register reports 1377 * link. If so, then we want to get the current speed/duplex 1378 * of the PHY. 1379 */ 1380 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 1381 if (ret_val) 1382 goto out; 1383 1384 if (hw->mac.type == e1000_pchlan) { 1385 ret_val = e1000_k1_gig_workaround_hv(hw, link); 1386 if (ret_val) 1387 goto out; 1388 } 1389 1390 /* When connected at 10Mbps half-duplex, some parts are excessively 1391 * aggressive resulting in many collisions. To avoid this, increase 1392 * the IPG and reduce Rx latency in the PHY. 1393 */ 1394 if ((hw->mac.type >= e1000_pch2lan) && link) { 1395 u16 speed, duplex; 1396 1397 e1000e_get_speed_and_duplex_copper(hw, &speed, &duplex); 1398 tipg_reg = er32(TIPG); 1399 tipg_reg &= ~E1000_TIPG_IPGT_MASK; 1400 1401 if (duplex == HALF_DUPLEX && speed == SPEED_10) { 1402 tipg_reg |= 0xFF; 1403 /* Reduce Rx latency in analog PHY */ 1404 emi_val = 0; 1405 } else if (hw->mac.type >= e1000_pch_spt && 1406 duplex == FULL_DUPLEX && speed != SPEED_1000) { 1407 tipg_reg |= 0xC; 1408 emi_val = 1; 1409 } else { 1410 1411 /* Roll back the default values */ 1412 tipg_reg |= 0x08; 1413 emi_val = 1; 1414 } 1415 1416 ew32(TIPG, tipg_reg); 1417 1418 ret_val = hw->phy.ops.acquire(hw); 1419 if (ret_val) 1420 goto out; 1421 1422 if (hw->mac.type == e1000_pch2lan) 1423 emi_addr = I82579_RX_CONFIG; 1424 else 1425 emi_addr = I217_RX_CONFIG; 1426 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val); 1427 1428 if (hw->mac.type >= e1000_pch_lpt) { 1429 u16 phy_reg; 1430 1431 e1e_rphy_locked(hw, I217_PLL_CLOCK_GATE_REG, &phy_reg); 1432 phy_reg &= ~I217_PLL_CLOCK_GATE_MASK; 1433 if (speed == SPEED_100 || speed == SPEED_10) 1434 phy_reg |= 0x3E8; 1435 else 1436 phy_reg |= 0xFA; 1437 e1e_wphy_locked(hw, I217_PLL_CLOCK_GATE_REG, phy_reg); 1438 1439 if (speed == SPEED_1000) { 1440 hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL, 1441 &phy_reg); 1442 1443 phy_reg |= HV_PM_CTRL_K1_CLK_REQ; 1444 1445 hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL, 1446 phy_reg); 1447 } 1448 } 1449 hw->phy.ops.release(hw); 1450 1451 if (ret_val) 1452 goto out; 1453 1454 if (hw->mac.type >= e1000_pch_spt) { 1455 u16 data; 1456 u16 ptr_gap; 1457 1458 if (speed == SPEED_1000) { 1459 ret_val = hw->phy.ops.acquire(hw); 1460 if (ret_val) 1461 goto out; 1462 1463 ret_val = e1e_rphy_locked(hw, 1464 PHY_REG(776, 20), 1465 &data); 1466 if (ret_val) { 1467 hw->phy.ops.release(hw); 1468 goto out; 1469 } 1470 1471 ptr_gap = (data & (0x3FF << 2)) >> 2; 1472 if (ptr_gap < 0x18) { 1473 data &= ~(0x3FF << 2); 1474 data |= (0x18 << 2); 1475 ret_val = 1476 e1e_wphy_locked(hw, 1477 PHY_REG(776, 20), 1478 data); 1479 } 1480 hw->phy.ops.release(hw); 1481 if (ret_val) 1482 goto out; 1483 } else { 1484 ret_val = hw->phy.ops.acquire(hw); 1485 if (ret_val) 1486 goto out; 1487 1488 ret_val = e1e_wphy_locked(hw, 1489 PHY_REG(776, 20), 1490 0xC023); 1491 hw->phy.ops.release(hw); 1492 if (ret_val) 1493 goto out; 1494 1495 } 1496 } 1497 } 1498 1499 /* I217 Packet Loss issue: 1500 * ensure that FEXTNVM4 Beacon Duration is set correctly 1501 * on power up. 1502 * Set the Beacon Duration for I217 to 8 usec 1503 */ 1504 if (hw->mac.type >= e1000_pch_lpt) { 1505 u32 mac_reg; 1506 1507 mac_reg = er32(FEXTNVM4); 1508 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK; 1509 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC; 1510 ew32(FEXTNVM4, mac_reg); 1511 } 1512 1513 /* Work-around I218 hang issue */ 1514 if ((hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_LM) || 1515 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_V) || 1516 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM3) || 1517 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V3)) { 1518 ret_val = e1000_k1_workaround_lpt_lp(hw, link); 1519 if (ret_val) 1520 goto out; 1521 } 1522 if (hw->mac.type >= e1000_pch_lpt) { 1523 /* Set platform power management values for 1524 * Latency Tolerance Reporting (LTR) 1525 */ 1526 ret_val = e1000_platform_pm_pch_lpt(hw, link); 1527 if (ret_val) 1528 goto out; 1529 } 1530 1531 /* Clear link partner's EEE ability */ 1532 hw->dev_spec.ich8lan.eee_lp_ability = 0; 1533 1534 if (hw->mac.type >= e1000_pch_lpt) { 1535 u32 fextnvm6 = er32(FEXTNVM6); 1536 1537 if (hw->mac.type == e1000_pch_spt) { 1538 /* FEXTNVM6 K1-off workaround - for SPT only */ 1539 u32 pcieanacfg = er32(PCIEANACFG); 1540 1541 if (pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE) 1542 fextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE; 1543 else 1544 fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE; 1545 } 1546 1547 ew32(FEXTNVM6, fextnvm6); 1548 } 1549 1550 if (!link) 1551 goto out; 1552 1553 switch (hw->mac.type) { 1554 case e1000_pch2lan: 1555 ret_val = e1000_k1_workaround_lv(hw); 1556 if (ret_val) 1557 return ret_val; 1558 /* fall-thru */ 1559 case e1000_pchlan: 1560 if (hw->phy.type == e1000_phy_82578) { 1561 ret_val = e1000_link_stall_workaround_hv(hw); 1562 if (ret_val) 1563 return ret_val; 1564 } 1565 1566 /* Workaround for PCHx parts in half-duplex: 1567 * Set the number of preambles removed from the packet 1568 * when it is passed from the PHY to the MAC to prevent 1569 * the MAC from misinterpreting the packet type. 1570 */ 1571 e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg); 1572 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK; 1573 1574 if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD) 1575 phy_reg |= BIT(HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT); 1576 1577 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg); 1578 break; 1579 default: 1580 break; 1581 } 1582 1583 /* Check if there was DownShift, must be checked 1584 * immediately after link-up 1585 */ 1586 e1000e_check_downshift(hw); 1587 1588 /* Enable/Disable EEE after link up */ 1589 if (hw->phy.type > e1000_phy_82579) { 1590 ret_val = e1000_set_eee_pchlan(hw); 1591 if (ret_val) 1592 return ret_val; 1593 } 1594 1595 /* If we are forcing speed/duplex, then we simply return since 1596 * we have already determined whether we have link or not. 1597 */ 1598 if (!mac->autoneg) 1599 return -E1000_ERR_CONFIG; 1600 1601 /* Auto-Neg is enabled. Auto Speed Detection takes care 1602 * of MAC speed/duplex configuration. So we only need to 1603 * configure Collision Distance in the MAC. 1604 */ 1605 mac->ops.config_collision_dist(hw); 1606 1607 /* Configure Flow Control now that Auto-Neg has completed. 1608 * First, we need to restore the desired flow control 1609 * settings because we may have had to re-autoneg with a 1610 * different link partner. 1611 */ 1612 ret_val = e1000e_config_fc_after_link_up(hw); 1613 if (ret_val) 1614 e_dbg("Error configuring flow control\n"); 1615 1616 return ret_val; 1617 1618out: 1619 mac->get_link_status = true; 1620 return ret_val; 1621} 1622 1623static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter) 1624{ 1625 struct e1000_hw *hw = &adapter->hw; 1626 s32 rc; 1627 1628 rc = e1000_init_mac_params_ich8lan(hw); 1629 if (rc) 1630 return rc; 1631 1632 rc = e1000_init_nvm_params_ich8lan(hw); 1633 if (rc) 1634 return rc; 1635 1636 switch (hw->mac.type) { 1637 case e1000_ich8lan: 1638 case e1000_ich9lan: 1639 case e1000_ich10lan: 1640 rc = e1000_init_phy_params_ich8lan(hw); 1641 break; 1642 case e1000_pchlan: 1643 case e1000_pch2lan: 1644 case e1000_pch_lpt: 1645 case e1000_pch_spt: 1646 case e1000_pch_cnp: 1647 case e1000_pch_tgp: 1648 case e1000_pch_adp: 1649 rc = e1000_init_phy_params_pchlan(hw); 1650 break; 1651 default: 1652 break; 1653 } 1654 if (rc) 1655 return rc; 1656 1657 /* Disable Jumbo Frame support on parts with Intel 10/100 PHY or 1658 * on parts with MACsec enabled in NVM (reflected in CTRL_EXT). 1659 */ 1660 if ((adapter->hw.phy.type == e1000_phy_ife) || 1661 ((adapter->hw.mac.type >= e1000_pch2lan) && 1662 (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) { 1663 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES; 1664 adapter->max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN; 1665 1666 hw->mac.ops.blink_led = NULL; 1667 } 1668 1669 if ((adapter->hw.mac.type == e1000_ich8lan) && 1670 (adapter->hw.phy.type != e1000_phy_ife)) 1671 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP; 1672 1673 /* Enable workaround for 82579 w/ ME enabled */ 1674 if ((adapter->hw.mac.type == e1000_pch2lan) && 1675 (er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) 1676 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA; 1677 1678 return 0; 1679} 1680 1681static DEFINE_MUTEX(nvm_mutex); 1682 1683/** 1684 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex 1685 * @hw: pointer to the HW structure 1686 * 1687 * Acquires the mutex for performing NVM operations. 1688 **/ 1689static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw __always_unused *hw) 1690{ 1691 mutex_lock(&nvm_mutex); 1692 1693 return 0; 1694} 1695 1696/** 1697 * e1000_release_nvm_ich8lan - Release NVM mutex 1698 * @hw: pointer to the HW structure 1699 * 1700 * Releases the mutex used while performing NVM operations. 1701 **/ 1702static void e1000_release_nvm_ich8lan(struct e1000_hw __always_unused *hw) 1703{ 1704 mutex_unlock(&nvm_mutex); 1705} 1706 1707/** 1708 * e1000_acquire_swflag_ich8lan - Acquire software control flag 1709 * @hw: pointer to the HW structure 1710 * 1711 * Acquires the software control flag for performing PHY and select 1712 * MAC CSR accesses. 1713 **/ 1714static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw) 1715{ 1716 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT; 1717 s32 ret_val = 0; 1718 1719 if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE, 1720 &hw->adapter->state)) { 1721 e_dbg("contention for Phy access\n"); 1722 return -E1000_ERR_PHY; 1723 } 1724 1725 while (timeout) { 1726 extcnf_ctrl = er32(EXTCNF_CTRL); 1727 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)) 1728 break; 1729 1730 mdelay(1); 1731 timeout--; 1732 } 1733 1734 if (!timeout) { 1735 e_dbg("SW has alre…
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