/drivers/net/ethernet/intel/ixgb/ixgb_ee.h

http://github.com/mirrors/linux · C Header · 79 lines · 54 code · 15 blank · 10 comment · 0 complexity · 4e57a93d717216306d75a5d272875d4d MD5 · raw file 

    

  1. /* SPDX-License-Identifier: GPL-2.0 */
    2. 

  2. /* Copyright(c) 1999 - 2008 Intel Corporation. */
    3. 

  3. 

  4. #ifndef _IXGB_EE_H_
    5. 

  5. #define _IXGB_EE_H_
    6. 

  6. 

  7. #define IXGB_EEPROM_SIZE    64	/* Size in words */
    8. 

  8. 

  9. /* EEPROM Commands */
    10. 

  10. #define EEPROM_READ_OPCODE  0x6	/* EEPROM read opcode */
    11. 

  11. #define EEPROM_WRITE_OPCODE 0x5	/* EEPROM write opcode */
    12. 

  12. #define EEPROM_ERASE_OPCODE 0x7	/* EEPROM erase opcode */
    13. 

  13. #define EEPROM_EWEN_OPCODE  0x13	/* EEPROM erase/write enable */
    14. 

  14. #define EEPROM_EWDS_OPCODE  0x10	/* EEPROM erase/write disable */
    15. 

  15. 

  16. /* EEPROM MAP (Word Offsets) */
    17. 

  17. #define EEPROM_IA_1_2_REG        0x0000
    18. 

  18. #define EEPROM_IA_3_4_REG        0x0001
    19. 

  19. #define EEPROM_IA_5_6_REG        0x0002
    20. 

  20. #define EEPROM_COMPATIBILITY_REG 0x0003
    21. 

  21. #define EEPROM_PBA_1_2_REG       0x0008
    22. 

  22. #define EEPROM_PBA_3_4_REG       0x0009
    23. 

  23. #define EEPROM_INIT_CONTROL1_REG 0x000A
    24. 

  24. #define EEPROM_SUBSYS_ID_REG     0x000B
    25. 

  25. #define EEPROM_SUBVEND_ID_REG    0x000C
    26. 

  26. #define EEPROM_DEVICE_ID_REG     0x000D
    27. 

  27. #define EEPROM_VENDOR_ID_REG     0x000E
    28. 

  28. #define EEPROM_INIT_CONTROL2_REG 0x000F
    29. 

  29. #define EEPROM_SWDPINS_REG       0x0020
    30. 

  30. #define EEPROM_CIRCUIT_CTRL_REG  0x0021
    31. 

  31. #define EEPROM_D0_D3_POWER_REG   0x0022
    32. 

  32. #define EEPROM_FLASH_VERSION     0x0032
    33. 

  33. #define EEPROM_CHECKSUM_REG      0x003F
    34. 

  34. 

  35. /* Mask bits for fields in Word 0x0a of the EEPROM */
    36. 

  36. 

  37. #define EEPROM_ICW1_SIGNATURE_MASK  0xC000
    38. 

  38. #define EEPROM_ICW1_SIGNATURE_VALID 0x4000
    39. 

  39. #define EEPROM_ICW1_SIGNATURE_CLEAR 0x0000
    40. 

  40. 

  41. /* For checksumming, the sum of all words in the EEPROM should equal 0xBABA. */
    42. 

  42. #define EEPROM_SUM 0xBABA
    43. 

  43. 

  44. /* EEPROM Map Sizes (Byte Counts) */
    45. 

  45. #define PBA_SIZE 4
    46. 

  46. 

  47. /* EEPROM Map defines (WORD OFFSETS)*/
    48. 

  48. 

  49. /* EEPROM structure */
    50. 

  50. struct ixgb_ee_map_type {
    51. 

  51. 	u8 mac_addr[ETH_ALEN];
    52. 

  52. 	__le16 compatibility;
    53. 

  53. 	__le16 reserved1[4];
    54. 

  54. 	__le32 pba_number;
    55. 

  55. 	__le16 init_ctrl_reg_1;
    56. 

  56. 	__le16 subsystem_id;
    57. 

  57. 	__le16 subvendor_id;
    58. 

  58. 	__le16 device_id;
    59. 

  59. 	__le16 vendor_id;
    60. 

  60. 	__le16 init_ctrl_reg_2;
    61. 

  61. 	__le16 oem_reserved[16];
    62. 

  62. 	__le16 swdpins_reg;
    63. 

  63. 	__le16 circuit_ctrl_reg;
    64. 

  64. 	u8 d3_power;
    65. 

  65. 	u8 d0_power;
    66. 

  66. 	__le16 reserved2[28];
    67. 

  67. 	__le16 checksum;
    68. 

  68. };
    69. 

  69. 

  70. /* EEPROM Functions */
    71. 

  71. u16 ixgb_read_eeprom(struct ixgb_hw *hw, u16 reg);
    72. 

  72. 

  73. bool ixgb_validate_eeprom_checksum(struct ixgb_hw *hw);
    74. 

  74. 

  75. void ixgb_update_eeprom_checksum(struct ixgb_hw *hw);
    76. 

  76. 

  77. void ixgb_write_eeprom(struct ixgb_hw *hw, u16 reg, u16 data);
    78. 

  78. 

  79. #endif				/* IXGB_EE_H */
    80.